driver-avalon4.c 93 KB

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  1. /*
  2. * Copyright 2014-2015 Mikeqin <Fengling.Qin@gmail.com>
  3. * Copyright 2013-2015 Con Kolivas <kernel@kolivas.org>
  4. * Copyright 2012-2015 Xiangfu <xiangfu@openmobilefree.com>
  5. * Copyright 2012 Luke Dashjr
  6. * Copyright 2012 Andrew Smith
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the Free
  10. * Software Foundation; either version 3 of the License, or (at your option)
  11. * any later version. See COPYING for more details.
  12. */
  13. #include <math.h>
  14. #include "config.h"
  15. #include "miner.h"
  16. #include "driver-avalon4.h"
  17. #include "crc.h"
  18. #include "sha2.h"
  19. #include "hexdump.c"
  20. #define get_fan_pwm(v) (AVA4_PWM_MAX - (v) * AVA4_PWM_MAX / 100)
  21. int opt_avalon4_temp_target = AVA4_DEFAULT_TEMP_TARGET;
  22. int opt_avalon4_overheat = AVA4_DEFAULT_TEMP_OVERHEAT;
  23. int opt_avalon4_fan_min = AVA4_DEFAULT_FAN_MIN;
  24. int opt_avalon4_fan_max = AVA4_DEFAULT_FAN_MAX;
  25. bool opt_avalon4_autov;
  26. bool opt_avalon4_freezesafe;
  27. int opt_avalon4_voltage_min = AVA4_DEFAULT_VOLTAGE;
  28. int opt_avalon4_voltage_max = AVA4_DEFAULT_VOLTAGE;
  29. unsigned int opt_avalon4_freq[3] = {AVA4_DEFAULT_FREQUENCY,
  30. AVA4_DEFAULT_FREQUENCY,
  31. AVA4_DEFAULT_FREQUENCY};
  32. int opt_avalon4_polling_delay = AVA4_DEFAULT_POLLING_DELAY;
  33. int opt_avalon4_aucspeed = AVA4_AUC_SPEED;
  34. int opt_avalon4_aucxdelay = AVA4_AUC_XDELAY;
  35. int opt_avalon4_ntime_offset = AVA4_DEFAULT_ASIC_MAX;
  36. int opt_avalon4_miningmode = AVA4_MOD_CUSTOM;
  37. int opt_avalon4_ntcb = AVA4_DEFAULT_NTCB;
  38. int opt_avalon4_freq_min = AVA4_DEFAULT_FREQUENCY_MIN;
  39. int opt_avalon4_freq_max = AVA4_DEFAULT_FREQUENCY_MAX;
  40. bool opt_avalon4_noncecheck = AVA4_DEFAULT_NCHECK;
  41. int opt_avalon4_smart_speed = AVA4_DEFAULT_SMART_SPEED;
  42. /*
  43. * smart speed have 3 modes
  44. * 1. auto speed by A3218 chips
  45. * 2. option 1 + adjust by least pll count
  46. * option 1 + adjust by most pll count
  47. * 3. option 1 + adjust by average frequency
  48. */
  49. int opt_avalon4_least_pll_check = AVA4_DEFAULT_LEAST_PLL;
  50. int opt_avalon4_most_pll_check = AVA4_DEFAULT_MOST_PLL;
  51. int opt_avalon4_speed_bingo = AVA4_DEFAULT_SPEED_BINGO;
  52. int opt_avalon4_speed_error = AVA4_DEFAULT_SPEED_ERROR;
  53. bool opt_avalon4_iic_detect = AVA4_DEFAULT_IIC_DETECT;
  54. int opt_avalon4_freqadj_time = AVA4_DEFAULT_FREQADJ_TIME;
  55. int opt_avalon4_delta_temp = AVA4_DEFAULT_DELTA_T;
  56. int opt_avalon4_delta_freq = AVA4_DEFAULT_DELTA_FREQ;
  57. int opt_avalon4_freqadj_temp = AVA4_MM60_TEMP_FREQADJ;
  58. static uint8_t avalon4_freezsafemode = 0;
  59. /* Only for Avalon4 */
  60. static uint32_t g_freq_array[][2] = {
  61. {100, 0x1e678447},
  62. {113, 0x22688447},
  63. {125, 0x1c470447},
  64. {138, 0x2a6a8447},
  65. {150, 0x22488447},
  66. {163, 0x326c8447},
  67. {175, 0x1a268447},
  68. {188, 0x1c270447},
  69. {200, 0x1e278447},
  70. {213, 0x20280447},
  71. {225, 0x22288447},
  72. {238, 0x24290447},
  73. {250, 0x26298447},
  74. {263, 0x282a0447},
  75. {275, 0x2a2a8447},
  76. {288, 0x2c2b0447},
  77. {300, 0x2e2b8447},
  78. {313, 0x302c0447},
  79. {325, 0x322c8447},
  80. {338, 0x342d0447},
  81. {350, 0x1a068447},
  82. {363, 0x382e0447},
  83. {375, 0x1c070447},
  84. {388, 0x3c2f0447},
  85. {400, 0x1e078447},
  86. {413, 0x40300447},
  87. {425, 0x20080447},
  88. {438, 0x44310447},
  89. {450, 0x22088447},
  90. {463, 0x48320447},
  91. {475, 0x24090447},
  92. {488, 0x4c330447},
  93. {500, 0x26098447},
  94. {513, 0x50340447},
  95. {525, 0x280a0447},
  96. {538, 0x54350447},
  97. {550, 0x2a0a8447},
  98. {563, 0x58360447},
  99. {575, 0x2c0b0447},
  100. {588, 0x5c370447},
  101. {600, 0x2e0b8447},
  102. {613, 0x60380447},
  103. {625, 0x300c0447},
  104. {638, 0x64390447},
  105. {650, 0x320c8447},
  106. {663, 0x683a0447},
  107. {675, 0x340d0447},
  108. {688, 0x6c3b0447},
  109. {700, 0x360d8447},
  110. {713, 0x703c0447},
  111. {725, 0x380e0447},
  112. {738, 0x743d0447},
  113. {750, 0x3a0e8447},
  114. {763, 0x783e0447},
  115. {775, 0x3c0f0447},
  116. {788, 0x7c3f0447},
  117. {800, 0x3e0f8447},
  118. {813, 0x3e0f8447},
  119. {825, 0x40100447},
  120. {838, 0x40100447},
  121. {850, 0x42108447},
  122. {863, 0x42108447},
  123. {875, 0x44110447},
  124. {888, 0x44110447},
  125. {900, 0x46118447},
  126. {913, 0x46118447},
  127. {925, 0x48120447},
  128. {938, 0x48120447},
  129. {950, 0x4a128447},
  130. {963, 0x4a128447},
  131. {975, 0x4c130447},
  132. {988, 0x4c130447},
  133. {1000, 0x4e138447}
  134. };
  135. #define UNPACK32(x, str) \
  136. { \
  137. *((str) + 3) = (uint8_t) ((x) ); \
  138. *((str) + 2) = (uint8_t) ((x) >> 8); \
  139. *((str) + 1) = (uint8_t) ((x) >> 16); \
  140. *((str) + 0) = (uint8_t) ((x) >> 24); \
  141. }
  142. static inline void sha256_prehash(const unsigned char *message, unsigned int len, unsigned char *digest)
  143. {
  144. sha256_ctx ctx;
  145. int i;
  146. sha256_init(&ctx);
  147. sha256_update(&ctx, message, len);
  148. for (i = 0; i < 8; i++) {
  149. UNPACK32(ctx.h[i], &digest[i << 2]);
  150. }
  151. }
  152. static inline uint8_t rev8(uint8_t d)
  153. {
  154. int i;
  155. uint8_t out = 0;
  156. /* (from left to right) */
  157. for (i = 0; i < 8; i++)
  158. if (d & (1 << i))
  159. out |= (1 << (7 - i));
  160. return out;
  161. }
  162. #define R_REF 10000
  163. #define R0 10000
  164. #define T0 25
  165. static float convert_temp(uint16_t adc)
  166. {
  167. float ret, resistance;
  168. if (!adc || adc >= AVA4_ADC_MAX)
  169. return -273.15;
  170. resistance = (AVA4_ADC_MAX * 1.0 / adc) - 1;
  171. resistance = R_REF / resistance;
  172. ret = resistance / R0;
  173. ret = logf(ret);
  174. ret /= opt_avalon4_ntcb;
  175. ret += 1.0 / (T0 + 273.15);
  176. ret = 1.0 / ret;
  177. ret -= 273.15;
  178. return ret;
  179. }
  180. #define V_REF 3.3
  181. static float convert_voltage(uint16_t adc, float percent)
  182. {
  183. float voltage;
  184. voltage = adc * V_REF * 1.0 / AVA4_ADC_MAX / percent;
  185. return voltage + 0.4;
  186. }
  187. char *set_avalon4_fan(char *arg)
  188. {
  189. int val1, val2, ret;
  190. ret = sscanf(arg, "%d-%d", &val1, &val2);
  191. if (ret < 1)
  192. return "No values passed to avalon4-fan";
  193. if (ret == 1)
  194. val2 = val1;
  195. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  196. return "Invalid value passed to avalon4-fan";
  197. opt_avalon4_fan_min = val1;
  198. opt_avalon4_fan_max = val2;
  199. return NULL;
  200. }
  201. char *set_avalon4_freq(char *arg)
  202. {
  203. char *colon1, *colon2;
  204. int val1 = 0, val2 = 0, val3 = 0;
  205. if (!(*arg))
  206. return NULL;
  207. colon1 = strchr(arg, ':');
  208. if (colon1)
  209. *(colon1++) = '\0';
  210. if (*arg) {
  211. val1 = atoi(arg);
  212. if (val1 < AVA4_DEFAULT_FREQUENCY_MIN || val1 > AVA4_DEFAULT_FREQUENCY_MAX)
  213. return "Invalid value1 passed to avalon4-freq";
  214. }
  215. if (colon1 && *colon1) {
  216. colon2 = strchr(colon1, ':');
  217. if (colon2)
  218. *(colon2++) = '\0';
  219. if (*colon1) {
  220. val2 = atoi(colon1);
  221. if (val2 < AVA4_DEFAULT_FREQUENCY_MIN || val2 > AVA4_DEFAULT_FREQUENCY_MAX)
  222. return "Invalid value2 passed to avalon4-freq";
  223. }
  224. if (colon2 && *colon2) {
  225. val3 = atoi(colon2);
  226. if (val3 < AVA4_DEFAULT_FREQUENCY_MIN || val3 > AVA4_DEFAULT_FREQUENCY_MAX)
  227. return "Invalid value3 passed to avalon4-freq";
  228. }
  229. }
  230. if (!val1)
  231. val3 = val2 = val1 = AVA4_DEFAULT_FREQUENCY;
  232. if (!val2)
  233. val3 = val2 = val1;
  234. if (!val3)
  235. val3 = val2;
  236. opt_avalon4_freq[0] = val1;
  237. opt_avalon4_freq[1] = val2;
  238. opt_avalon4_freq[2] = val3;
  239. return NULL;
  240. }
  241. char *set_avalon4_voltage(char *arg)
  242. {
  243. int val1, val2, ret;
  244. ret = sscanf(arg, "%d-%d", &val1, &val2);
  245. if (ret < 1)
  246. return "No values passed to avalon4-voltage";
  247. if (ret == 1)
  248. val2 = val1;
  249. if (val1 < AVA4_DEFAULT_VOLTAGE_MIN || val1 > AVA4_DEFAULT_VOLTAGE_MAX ||
  250. val2 < AVA4_DEFAULT_VOLTAGE_MIN || val2 > AVA4_DEFAULT_VOLTAGE_MAX ||
  251. val2 < val1)
  252. return "Invalid value passed to avalon4-voltage";
  253. opt_avalon4_voltage_min = val1;
  254. opt_avalon4_voltage_max = val2;
  255. return NULL;
  256. }
  257. static int avalon4_init_pkg(struct avalon4_pkg *pkg, uint8_t type, uint8_t idx, uint8_t cnt)
  258. {
  259. unsigned short crc;
  260. pkg->head[0] = AVA4_H1;
  261. pkg->head[1] = AVA4_H2;
  262. pkg->type = type;
  263. pkg->opt = 0;
  264. pkg->idx = idx;
  265. pkg->cnt = cnt;
  266. crc = crc16(pkg->data, AVA4_P_DATA_LEN);
  267. pkg->crc[0] = (crc & 0xff00) >> 8;
  268. pkg->crc[1] = crc & 0x00ff;
  269. return 0;
  270. }
  271. static int job_idcmp(uint8_t *job_id, char *pool_job_id)
  272. {
  273. int job_id_len;
  274. unsigned short crc, crc_expect;
  275. if (!pool_job_id)
  276. return 1;
  277. job_id_len = strlen(pool_job_id);
  278. crc_expect = crc16((unsigned char *)pool_job_id, job_id_len);
  279. crc = job_id[0] << 8 | job_id[1];
  280. if (crc_expect == crc)
  281. return 0;
  282. applog(LOG_DEBUG, "Avalon4: job_id doesn't match! [%04x:%04x (%s)]",
  283. crc, crc_expect, pool_job_id);
  284. return 1;
  285. }
  286. static inline int get_current_temp_max(struct avalon4_info *info)
  287. {
  288. int i;
  289. int t = info->temp[0];
  290. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  291. if (info->enable[i] && info->temp[i] > t)
  292. t = info->temp[i];
  293. }
  294. return t;
  295. }
  296. static inline int get_temp_max(struct avalon4_info *info, int addr)
  297. {
  298. int i;
  299. int t = -273, t1 = -273;
  300. if (info->enable[addr]) {
  301. t = info->temp[addr];
  302. for (i = 0; i < 2; i++) {
  303. t1 = convert_temp(info->adc[addr][i]);
  304. if (t1 > t)
  305. t = t1;
  306. }
  307. }
  308. return t;
  309. }
  310. /* http://www.onsemi.com/pub_link/Collateral/ADP3208D.PDF */
  311. static uint32_t encode_voltage_adp3208d(uint32_t v)
  312. {
  313. return rev8((0x78 - v / 125) << 1 | 1) << 8;
  314. }
  315. static uint32_t decode_voltage_adp3208d(uint32_t v)
  316. {
  317. return (0x78 - (rev8(v >> 8) >> 1)) * 125;
  318. }
  319. /* http://www.onsemi.com/pub/Collateral/NCP5392P-D.PDF */
  320. static uint32_t encode_voltage_ncp5392p(uint32_t v)
  321. {
  322. if (v == 0)
  323. return 0xff00;
  324. return rev8(((0x59 - (v - 5000) / 125) & 0xff) << 1 | 1) << 8;
  325. }
  326. static uint32_t decode_voltage_ncp5392p(uint32_t v)
  327. {
  328. if (v == 0xff00)
  329. return 0;
  330. return (0x59 - (rev8(v >> 8) >> 1)) * 125 + 5000;
  331. }
  332. static inline uint32_t adjust_fan(struct avalon4_info *info, int id)
  333. {
  334. uint32_t pwm;
  335. int t = info->temp[id], diff, fandiff = opt_avalon4_fan_max - opt_avalon4_fan_min;;
  336. if (info->mod_type[id] == AVA4_TYPE_MM60) {
  337. int t1, t2;
  338. t1 = (int)convert_temp(info->adc[id][0]),
  339. t2 = (int)convert_temp(info->adc[id][1]),
  340. t = t > t1 ? t : t1;
  341. t = t > t2 ? t : t2;
  342. }
  343. if (avalon4_freezsafemode) {
  344. pwm = get_fan_pwm(AVA4_FREEZESAFE_FAN);
  345. return pwm;
  346. }
  347. /* Scale fan% non linearly relatively to target temperature. It will
  348. * not try to keep the temperature at temp_target that accurately but
  349. * avoids temperature overshoot in both directions. */
  350. diff = t - opt_avalon4_temp_target + 30;
  351. if (diff > 32)
  352. diff = 32;
  353. else if (diff < 0)
  354. diff = 0;
  355. diff *= diff;
  356. fandiff = fandiff * diff / 1024;
  357. info->fan_pct[id] = opt_avalon4_fan_min + fandiff;
  358. pwm = get_fan_pwm(info->fan_pct[id]);
  359. if ((info->mod_type[id] == AVA4_TYPE_MM60) &&
  360. (info->freq_mode[id] == AVA4_FREQ_TEMPADJ_MODE))
  361. pwm = get_fan_pwm(opt_avalon4_fan_max);
  362. if (info->cutoff[id])
  363. pwm = get_fan_pwm(opt_avalon4_fan_max);
  364. applog(LOG_DEBUG, "[%d], Adjust_fan: %dC-%d%%(%03x)", id, t, info->fan_pct[id], pwm);
  365. return pwm;
  366. }
  367. static int decode_pkg(struct thr_info *thr, struct avalon4_ret *ar, int modular_id)
  368. {
  369. struct cgpu_info *avalon4 = thr->cgpu;
  370. struct avalon4_info *info = avalon4->device_data;
  371. struct pool *pool, *real_pool;
  372. struct pool *pool_stratum0 = &info->pool0;
  373. struct pool *pool_stratum1 = &info->pool1;
  374. struct pool *pool_stratum2 = &info->pool2;
  375. unsigned int expected_crc;
  376. unsigned int actual_crc;
  377. uint32_t nonce, nonce2, ntime, miner, chip_id, volt, tmp;
  378. uint8_t job_id[4];
  379. int pool_no, i;
  380. uint32_t val[AVA4_DEFAULT_MINER_MAX];
  381. if (ar->head[0] != AVA4_H1 && ar->head[1] != AVA4_H2) {
  382. applog(LOG_DEBUG, "%s-%d-%d: H1 %02x, H2 %02x",
  383. avalon4->drv->name, avalon4->device_id, modular_id,
  384. ar->head[0], ar->head[1]);
  385. hexdump(ar->data, 32);
  386. return 1;
  387. }
  388. expected_crc = crc16(ar->data, AVA4_P_DATA_LEN);
  389. actual_crc = (ar->crc[0] & 0xff) | ((ar->crc[1] & 0xff) << 8);
  390. if (expected_crc != actual_crc) {
  391. applog(LOG_DEBUG, "%s-%d-%d: %02x: expected crc(%04x), actual_crc(%04x)",
  392. avalon4->drv->name, avalon4->device_id, modular_id,
  393. ar->type, expected_crc, actual_crc);
  394. return 1;
  395. }
  396. switch(ar->type) {
  397. case AVA4_P_NONCE:
  398. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_NONCE", avalon4->drv->name, avalon4->device_id, modular_id);
  399. memcpy(&miner, ar->data + 0, 4);
  400. memcpy(&pool_no, ar->data + 4, 4);
  401. memcpy(&nonce2, ar->data + 8, 4);
  402. memcpy(&ntime, ar->data + 12, 4);
  403. memcpy(&nonce, ar->data + 16, 4);
  404. memcpy(job_id, ar->data + 20, 4);
  405. miner = be32toh(miner);
  406. chip_id = (miner >> 16) & 0xffff;
  407. miner &= 0xffff;
  408. pool_no = be32toh(pool_no);
  409. ntime = be32toh(ntime);
  410. if (miner >= info->miner_count[modular_id] ||
  411. pool_no >= total_pools || pool_no < 0) {
  412. applog(LOG_DEBUG, "%s-%d-%d: Wrong miner/pool_no %d/%d",
  413. avalon4->drv->name, avalon4->device_id, modular_id,
  414. miner, pool_no);
  415. break;
  416. }
  417. nonce2 = be32toh(nonce2);
  418. nonce = be32toh(nonce);
  419. if ((info->mod_type[modular_id] == AVA4_TYPE_MM40) ||
  420. (info->mod_type[modular_id] == AVA4_TYPE_MM41) ||
  421. (info->mod_type[modular_id] == AVA4_TYPE_MM50))
  422. nonce -= 0x4000;
  423. applog(LOG_DEBUG, "%s-%d-%d: Found! P:%d - N2:%08x N:%08x NR:%d [M:%d - MW: %d(%d,%d,%d,%d)]",
  424. avalon4->drv->name, avalon4->device_id, modular_id,
  425. pool_no, nonce2, nonce, ntime,
  426. miner, info->matching_work[modular_id][miner],
  427. info->chipmatching_work[modular_id][miner][0],
  428. info->chipmatching_work[modular_id][miner][1],
  429. info->chipmatching_work[modular_id][miner][2],
  430. info->chipmatching_work[modular_id][miner][3]);
  431. real_pool = pool = pools[pool_no];
  432. if (job_idcmp(job_id, pool->swork.job_id)) {
  433. if (!job_idcmp(job_id, pool_stratum0->swork.job_id)) {
  434. applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum0! (%s)",
  435. avalon4->drv->name, avalon4->device_id, modular_id,
  436. pool_stratum0->swork.job_id);
  437. pool = pool_stratum0;
  438. } else if (!job_idcmp(job_id, pool_stratum1->swork.job_id)) {
  439. applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum1! (%s)",
  440. avalon4->drv->name, avalon4->device_id, modular_id,
  441. pool_stratum1->swork.job_id);
  442. pool = pool_stratum1;
  443. } else if (!job_idcmp(job_id, pool_stratum2->swork.job_id)) {
  444. applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum2! (%s)",
  445. avalon4->drv->name, avalon4->device_id, modular_id,
  446. pool_stratum2->swork.job_id);
  447. pool = pool_stratum2;
  448. } else {
  449. applog(LOG_ERR, "%s-%d-%d: Cannot match to any stratum! (%s)",
  450. avalon4->drv->name, avalon4->device_id, modular_id,
  451. pool->swork.job_id);
  452. inc_hw_errors(thr);
  453. if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
  454. info->hw_works_i[modular_id][miner]++;
  455. info->hw5_i[modular_id][miner][info->i_5s]++;
  456. }
  457. break;
  458. }
  459. }
  460. if (!submit_nonce2_nonce(thr, pool, real_pool, nonce2, nonce, ntime)) {
  461. if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
  462. info->hw_works_i[modular_id][miner]++;
  463. info->hw5_i[modular_id][miner][info->i_5s]++;
  464. }
  465. } else {
  466. info->matching_work[modular_id][miner]++;
  467. info->chipmatching_work[modular_id][miner][chip_id]++;
  468. }
  469. break;
  470. case AVA4_P_STATUS:
  471. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS", avalon4->drv->name, avalon4->device_id, modular_id);
  472. hexdump(ar->data, 32);
  473. memcpy(&tmp, ar->data, 4);
  474. tmp = be32toh(tmp);
  475. info->temp[modular_id] = tmp;
  476. memcpy(&tmp, ar->data + 4, 4);
  477. tmp = be32toh(tmp);
  478. info->fan[modular_id] = tmp;
  479. memcpy(&(info->get_frequency[modular_id]), ar->data + 8, 4);
  480. memcpy(&(info->get_voltage[modular_id]), ar->data + 12, 4);
  481. memcpy(&(info->local_work[modular_id]), ar->data + 16, 4);
  482. memcpy(&(info->hw_work[modular_id]), ar->data + 20, 4);
  483. memcpy(&(info->power_good[modular_id]), ar->data + 24, 4);
  484. memcpy(&(info->error_code[modular_id]), ar->data + 28, 4);
  485. if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
  486. if (info->total_asics[modular_id])
  487. info->get_frequency[modular_id] = be32toh(info->get_frequency[modular_id]) / info->total_asics[modular_id];
  488. } else
  489. info->get_frequency[modular_id] = be32toh(info->get_frequency[modular_id]) * 3968 / 65;
  490. info->get_voltage[modular_id] = be32toh(info->get_voltage[modular_id]);
  491. info->local_work[modular_id] = be32toh(info->local_work[modular_id]);
  492. info->hw_work[modular_id] = be32toh(info->hw_work[modular_id]);
  493. info->power_good[modular_id] = be32toh(info->power_good[modular_id]);
  494. info->error_code[modular_id] = be32toh(info->error_code[modular_id]);
  495. volt = info->get_voltage[modular_id];
  496. if (info->mod_type[modular_id] == AVA4_TYPE_MM40)
  497. tmp = decode_voltage_adp3208d(volt);
  498. if (info->mod_type[modular_id] == AVA4_TYPE_MM41)
  499. tmp = decode_voltage_ncp5392p(volt);
  500. if (info->mod_type[modular_id] == AVA4_TYPE_MM50)
  501. tmp = decode_voltage_ncp5392p(volt);
  502. /* TODO: fix it with the actual board */
  503. if (info->mod_type[modular_id] == AVA4_TYPE_MM60)
  504. tmp = decode_voltage_ncp5392p(volt);
  505. info->get_voltage[modular_id] = tmp;
  506. info->local_works[modular_id] += info->local_work[modular_id];
  507. info->hw_works[modular_id] += info->hw_work[modular_id];
  508. info->lw5[modular_id][info->i_5s] += info->local_work[modular_id];
  509. info->hw5[modular_id][info->i_5s] += info->hw_work[modular_id];
  510. avalon4->temp = get_current_temp_max(info);
  511. break;
  512. case AVA4_P_STATUS_LW:
  513. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_LW", avalon4->drv->name, avalon4->device_id, modular_id);
  514. for (i = 0; i < info->miner_count[modular_id]; i++) {
  515. info->local_works_i[modular_id][i] += ((ar->data[i * 3] << 16) |
  516. (ar->data[i * 3 + 1] << 8) |
  517. (ar->data[i * 3 + 2]));
  518. info->lw5_i[modular_id][i][info->i_5s] += ((ar->data[i * 3] << 16) |
  519. (ar->data[i * 3 + 1] << 8) |
  520. (ar->data[i * 3 + 2]));
  521. }
  522. break;
  523. case AVA4_P_STATUS_HW:
  524. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_HW", avalon4->drv->name, avalon4->device_id, modular_id);
  525. if (info->mod_type[modular_id] == AVA4_TYPE_MM60) {
  526. applog(LOG_NOTICE, "%s-%d-%d: AVA4_P_STATUS_HW found on Avalon6!", avalon4->drv->name, avalon4->device_id, modular_id);
  527. break;
  528. }
  529. for (i = 0; i < info->miner_count[modular_id]; i++) {
  530. info->hw_works_i[modular_id][i] += ((ar->data[i * 3] << 16) |
  531. (ar->data[i * 3 + 1] << 8) |
  532. (ar->data[i * 3 + 2]));
  533. info->hw5_i[modular_id][i][info->i_5s] += ((ar->data[i * 3] << 16) |
  534. (ar->data[i * 3 + 1] << 8) |
  535. (ar->data[i * 3 + 2]));
  536. }
  537. break;
  538. case AVA4_P_ACKDETECT:
  539. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_ACKDETECT", avalon4->drv->name, avalon4->device_id, modular_id);
  540. break;
  541. case AVA4_P_STATUS_VOLT:
  542. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_VOLT", avalon4->drv->name, avalon4->device_id, modular_id);
  543. hexdump(ar->data, 32);
  544. for(i = 0; i < info->miner_count[modular_id]; i++) {
  545. tmp = (ar->data[i * 2] << 8) + ar->data[i * 2 + 1];
  546. if (info->mod_type[modular_id] == AVA4_TYPE_MM40)
  547. tmp = decode_voltage_adp3208d(tmp);
  548. if (info->mod_type[modular_id] == AVA4_TYPE_MM41)
  549. tmp = decode_voltage_ncp5392p(tmp);
  550. if (info->mod_type[modular_id] == AVA4_TYPE_MM50)
  551. tmp = decode_voltage_ncp5392p(tmp);
  552. /* TODO: fix it with the actual board */
  553. if (info->mod_type[modular_id] == AVA4_TYPE_MM60)
  554. tmp = decode_voltage_ncp5392p(tmp);
  555. if (tmp < AVA4_DEFAULT_VOLTAGE_MIN || tmp > AVA4_DEFAULT_VOLTAGE_MAX) {
  556. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_VOLT invalid voltage %d", avalon4->drv->name, avalon4->device_id, modular_id, tmp);
  557. return 1;
  558. }
  559. val[((4 + i / 5 * 5) - i + (i / 5 * 5))] = tmp;
  560. }
  561. if (i == info->miner_count[modular_id]) {
  562. for (i = 0; i < info->miner_count[modular_id]; i++) {
  563. info->get_voltage_i[modular_id][i] = val[i];
  564. }
  565. }
  566. break;
  567. case AVA4_P_STATUS_MA:
  568. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_MA", avalon4->drv->name, avalon4->device_id, modular_id);
  569. for (i = 0; i < info->asic_count[modular_id]; i++)
  570. info->ma_sum[modular_id][ar->opt][i] = ar->data[i];
  571. break;
  572. case AVA4_P_STATUS_M:
  573. applog(LOG_DEBUG, "%s-%d-%d: AVA4_P_STATUS_M", avalon4->drv->name, avalon4->device_id, modular_id);
  574. for (i = 0; i < AVA4_DEFAULT_ADC_MAX; i++)
  575. info->adc[modular_id][i] = (ar->data[2 * i] << 8) | ar->data[(2 * i) + 1];
  576. /* MCU LED status --> data[2 * AVA4_DEFAULT_ADC : 2 * AVA4_DEFAULT_ADC_MAX + 3] */
  577. for (i = 0; i < AVA4_DEFAULT_PLL_MAX; i++)
  578. info->pll_sel[modular_id][i] = (ar->data[2 * (AVA4_DEFAULT_ADC_MAX + 2 + i)] << 8) |
  579. ar->data[(2 * (AVA4_DEFAULT_ADC_MAX + 2 + i)) + 1];
  580. break;
  581. default:
  582. applog(LOG_DEBUG, "%s-%d-%d: Unknown response", avalon4->drv->name, avalon4->device_id, modular_id);
  583. break;
  584. }
  585. return 0;
  586. }
  587. /*
  588. # IIC packet format: length[1]+transId[1]+sesId[1]+req[1]+data[60]
  589. # length: 4+len(data)
  590. # transId: 0
  591. # sesId: 0
  592. # req: checkout the header file
  593. # data:
  594. # INIT: clock_rate[4] + reserved[4] + payload[52]
  595. # XFER: txSz[1]+rxSz[1]+options[1]+slaveAddr[1] + payload[56]
  596. */
  597. static int avalon4_auc_init_pkg(uint8_t *iic_pkg, struct avalon4_iic_info *iic_info, uint8_t *buf, int wlen, int rlen)
  598. {
  599. memset(iic_pkg, 0, AVA4_AUC_P_SIZE);
  600. switch (iic_info->iic_op) {
  601. case AVA4_IIC_INIT:
  602. iic_pkg[0] = 12; /* 4 bytes IIC header + 4 bytes speed + 4 bytes xfer delay */
  603. iic_pkg[3] = AVA4_IIC_INIT;
  604. iic_pkg[4] = iic_info->iic_param.aucParam[0] & 0xff;
  605. iic_pkg[5] = (iic_info->iic_param.aucParam[0] >> 8) & 0xff;
  606. iic_pkg[6] = (iic_info->iic_param.aucParam[0] >> 16) & 0xff;
  607. iic_pkg[7] = iic_info->iic_param.aucParam[0] >> 24;
  608. iic_pkg[8] = iic_info->iic_param.aucParam[1] & 0xff;
  609. iic_pkg[9] = (iic_info->iic_param.aucParam[1] >> 8) & 0xff;
  610. iic_pkg[10] = (iic_info->iic_param.aucParam[1] >> 16) & 0xff;
  611. iic_pkg[11] = iic_info->iic_param.aucParam[1] >> 24;
  612. break;
  613. case AVA4_IIC_XFER:
  614. iic_pkg[0] = 8 + wlen;
  615. iic_pkg[3] = AVA4_IIC_XFER;
  616. iic_pkg[4] = wlen;
  617. iic_pkg[5] = rlen;
  618. iic_pkg[7] = iic_info->iic_param.slave_addr;
  619. if (buf && wlen)
  620. memcpy(iic_pkg + 8, buf, wlen);
  621. break;
  622. case AVA4_IIC_RESET:
  623. case AVA4_IIC_DEINIT:
  624. case AVA4_IIC_INFO:
  625. iic_pkg[0] = 4;
  626. iic_pkg[3] = iic_info->iic_op;
  627. break;
  628. default:
  629. break;
  630. }
  631. return 0;
  632. }
  633. static int avalon4_iic_xfer(struct cgpu_info *avalon4, uint8_t slave_addr,
  634. uint8_t *wbuf, int wlen,
  635. uint8_t *rbuf, int rlen)
  636. {
  637. struct avalon4_info *info = avalon4->device_data;
  638. struct i2c_ctx *pctx = NULL;
  639. int err = 1;
  640. bool ret = false;
  641. pctx = info->i2c_slaves[slave_addr];
  642. if (!pctx) {
  643. applog(LOG_ERR, "%s-%d: IIC xfer i2c slaves null!", avalon4->drv->name, avalon4->device_id);
  644. goto out;
  645. }
  646. if (wbuf) {
  647. ret = pctx->write_raw(pctx, wbuf, wlen);
  648. if (!ret) {
  649. applog(LOG_DEBUG, "%s-%d: IIC xfer write raw failed!", avalon4->drv->name, avalon4->device_id);
  650. goto out;
  651. }
  652. }
  653. cgsleep_ms(5);
  654. if (rbuf) {
  655. ret = pctx->read_raw(pctx, rbuf, rlen);
  656. if (!ret) {
  657. applog(LOG_DEBUG, "%s-%d: IIC xfer read raw failed!", avalon4->drv->name, avalon4->device_id);
  658. hexdump(rbuf, rlen);
  659. goto out;
  660. }
  661. }
  662. return 0;
  663. out:
  664. return err;
  665. }
  666. static int avalon4_auc_xfer(struct cgpu_info *avalon4,
  667. uint8_t *wbuf, int wlen, int *write,
  668. uint8_t *rbuf, int rlen, int *read)
  669. {
  670. int err = -1;
  671. if (unlikely(avalon4->usbinfo.nodev))
  672. goto out;
  673. usb_buffer_clear(avalon4);
  674. err = usb_write(avalon4, (char *)wbuf, wlen, write, C_AVA4_WRITE);
  675. if (err || *write != wlen) {
  676. applog(LOG_DEBUG, "%s-%d: AUC xfer %d, w(%d-%d)!", avalon4->drv->name, avalon4->device_id, err, wlen, *write);
  677. usb_nodev(avalon4);
  678. goto out;
  679. }
  680. cgsleep_ms(opt_avalon4_aucxdelay / 4800 + 1);
  681. rlen += 4; /* Add 4 bytes IIC header */
  682. err = usb_read(avalon4, (char *)rbuf, rlen, read, C_AVA4_READ);
  683. if (err || *read != rlen || *read != rbuf[0]) {
  684. applog(LOG_DEBUG, "%s-%d: AUC xfer %d, r(%d-%d-%d)!", avalon4->drv->name, avalon4->device_id, err, rlen - 4, *read, rbuf[0]);
  685. hexdump(rbuf, rlen);
  686. return -1;
  687. }
  688. *read = rbuf[0] - 4; /* Remove 4 bytes IIC header */
  689. out:
  690. return err;
  691. }
  692. static int avalon4_auc_init(struct cgpu_info *avalon4, char *ver)
  693. {
  694. struct avalon4_iic_info iic_info;
  695. int err, wlen, rlen;
  696. uint8_t wbuf[AVA4_AUC_P_SIZE];
  697. uint8_t rbuf[AVA4_AUC_P_SIZE];
  698. if (unlikely(avalon4->usbinfo.nodev))
  699. return 1;
  700. /* Try to clean the AUC buffer */
  701. usb_buffer_clear(avalon4);
  702. err = usb_read(avalon4, (char *)rbuf, AVA4_AUC_P_SIZE, &rlen, C_AVA4_READ);
  703. applog(LOG_DEBUG, "%s-%d: AUC usb_read %d, %d!", avalon4->drv->name, avalon4->device_id, err, rlen);
  704. hexdump(rbuf, AVA4_AUC_P_SIZE);
  705. /* Reset */
  706. iic_info.iic_op = AVA4_IIC_RESET;
  707. rlen = 0;
  708. avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  709. memset(rbuf, 0, AVA4_AUC_P_SIZE);
  710. err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  711. if (err) {
  712. applog(LOG_ERR, "%s-%d: Failed to reset Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id);
  713. return 1;
  714. }
  715. /* Deinit */
  716. iic_info.iic_op = AVA4_IIC_DEINIT;
  717. rlen = 0;
  718. avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  719. memset(rbuf, 0, AVA4_AUC_P_SIZE);
  720. err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  721. if (err) {
  722. applog(LOG_ERR, "%s-%d: Failed to deinit Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id);
  723. return 1;
  724. }
  725. /* Init */
  726. iic_info.iic_op = AVA4_IIC_INIT;
  727. iic_info.iic_param.aucParam[0] = opt_avalon4_aucspeed;
  728. iic_info.iic_param.aucParam[1] = opt_avalon4_aucxdelay;
  729. rlen = AVA4_AUC_VER_LEN;
  730. avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  731. memset(rbuf, 0, AVA4_AUC_P_SIZE);
  732. err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  733. if (err) {
  734. applog(LOG_ERR, "%s-%d: Failed to init Avalon USB2IIC Converter", avalon4->drv->name, avalon4->device_id);
  735. return 1;
  736. }
  737. hexdump(rbuf, AVA4_AUC_P_SIZE);
  738. memcpy(ver, rbuf + 4, AVA4_AUC_VER_LEN);
  739. ver[AVA4_AUC_VER_LEN] = '\0';
  740. applog(LOG_DEBUG, "%s-%d: USB2IIC Converter version: %s!", avalon4->drv->name, avalon4->device_id, ver);
  741. return 0;
  742. }
  743. static int avalon4_auc_getinfo(struct cgpu_info *avalon4)
  744. {
  745. struct avalon4_iic_info iic_info;
  746. int err, wlen, rlen;
  747. uint8_t wbuf[AVA4_AUC_P_SIZE];
  748. uint8_t rbuf[AVA4_AUC_P_SIZE];
  749. uint8_t *pdata = rbuf + 4;
  750. uint16_t adc_val;
  751. struct avalon4_info *info = avalon4->device_data;
  752. iic_info.iic_op = AVA4_IIC_INFO;
  753. /* Device info: (9 bytes)
  754. * tempadc(2), reqRdIndex, reqWrIndex,
  755. * respRdIndex, respWrIndex, tx_flags, state
  756. * */
  757. rlen = 7;
  758. avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  759. memset(rbuf, 0, AVA4_AUC_P_SIZE);
  760. err = avalon4_auc_xfer(avalon4, wbuf, AVA4_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  761. if (err) {
  762. applog(LOG_ERR, "%s-%d: AUC Failed to get info ", avalon4->drv->name, avalon4->device_id);
  763. return 1;
  764. }
  765. applog(LOG_DEBUG, "%s-%d: AUC tempADC(%03d), reqcnt(%d), respcnt(%d), txflag(%d), state(%d)",
  766. avalon4->drv->name, avalon4->device_id,
  767. pdata[1] << 8 | pdata[0],
  768. pdata[2],
  769. pdata[3],
  770. pdata[5] << 8 | pdata[4],
  771. pdata[6]);
  772. adc_val = pdata[1] << 8 | pdata[0];
  773. info->auc_temp = 3.3 * adc_val * 10000 / 1023;
  774. return 0;
  775. }
  776. static int avalon4_iic_xfer_pkg(struct cgpu_info *avalon4, uint8_t slave_addr,
  777. const struct avalon4_pkg *pkg, struct avalon4_ret *ret)
  778. {
  779. struct avalon4_iic_info iic_info;
  780. int err, wcnt, rcnt, rlen = 0;
  781. uint8_t wbuf[AVA4_AUC_P_SIZE];
  782. uint8_t rbuf[AVA4_AUC_P_SIZE];
  783. struct avalon4_info *info = avalon4->device_data;
  784. if (ret)
  785. rlen = AVA4_READ_SIZE;
  786. if (info->connecter == AVA4_CONNECTER_AUC) {
  787. if (unlikely(avalon4->usbinfo.nodev))
  788. return AVA4_SEND_ERROR;
  789. iic_info.iic_op = AVA4_IIC_XFER;
  790. iic_info.iic_param.slave_addr = slave_addr;
  791. avalon4_auc_init_pkg(wbuf, &iic_info, (uint8_t *)pkg, AVA4_WRITE_SIZE, rlen);
  792. err = avalon4_auc_xfer(avalon4, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt);
  793. if ((pkg->type != AVA4_P_DETECT) && err == -7 && !rcnt && rlen) {
  794. avalon4_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  795. err = avalon4_auc_xfer(avalon4, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt);
  796. applog(LOG_DEBUG, "%s-%d-%d: AUC read again!(type:0x%x, err:%d)", avalon4->drv->name, avalon4->device_id, slave_addr, pkg->type, err);
  797. }
  798. if (err || rcnt != rlen) {
  799. if (info->xfer_err_cnt++ == 100) {
  800. applog(LOG_DEBUG, "%s-%d-%d: AUC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d",
  801. avalon4->drv->name, avalon4->device_id, slave_addr,
  802. err, rcnt, rlen);
  803. cgsleep_ms(5 * 1000); /* Wait MM reset */
  804. avalon4_auc_init(avalon4, info->auc_version);
  805. }
  806. return AVA4_SEND_ERROR;
  807. }
  808. if (ret)
  809. memcpy((char *)ret, rbuf + 4, AVA4_READ_SIZE);
  810. info->xfer_err_cnt = 0;
  811. }
  812. if (info->connecter == AVA4_CONNECTER_IIC) {
  813. err = avalon4_iic_xfer(avalon4, slave_addr, (uint8_t *)pkg, AVA4_WRITE_SIZE, (uint8_t *)ret, AVA4_READ_SIZE);
  814. if ((pkg->type != AVA4_P_DETECT) && err) {
  815. err = avalon4_iic_xfer(avalon4, slave_addr, (uint8_t *)pkg, AVA4_WRITE_SIZE, (uint8_t *)ret, AVA4_READ_SIZE);
  816. applog(LOG_DEBUG, "%s-%d-%d: IIC read again!(type:0x%x, err:%d)", avalon4->drv->name, avalon4->device_id, slave_addr, pkg->type, err);
  817. }
  818. if (err) {
  819. /* FIXME: Don't care broadcast message with no reply, or it will block other thread when called by avalon4_send_bc_pkgs */
  820. if ((pkg->type != AVA4_P_DETECT) && (slave_addr == AVA4_MODULE_BROADCAST))
  821. return AVA4_SEND_OK;
  822. if (info->xfer_err_cnt++ == 100) {
  823. info->xfer_err_cnt = 0;
  824. applog(LOG_DEBUG, "%s-%d-%d: IIC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d",
  825. avalon4->drv->name, avalon4->device_id, slave_addr,
  826. err, rcnt, rlen);
  827. cgsleep_ms(5 * 1000); /* Wait MM reset */
  828. }
  829. return AVA4_SEND_ERROR;
  830. }
  831. info->xfer_err_cnt = 0;
  832. }
  833. return AVA4_SEND_OK;
  834. }
  835. static int avalon4_send_bc_pkgs(struct cgpu_info *avalon4, const struct avalon4_pkg *pkg)
  836. {
  837. int ret;
  838. do {
  839. ret = avalon4_iic_xfer_pkg(avalon4, AVA4_MODULE_BROADCAST, pkg, NULL);
  840. } while (ret != AVA4_SEND_OK);
  841. return 0;
  842. }
  843. static void avalon4_stratum_pkgs(struct cgpu_info *avalon4, struct pool *pool)
  844. {
  845. struct avalon4_info *info = avalon4->device_data;
  846. const int merkle_offset = 36;
  847. struct avalon4_pkg pkg;
  848. int i, a, b, tmp;
  849. unsigned char target[32];
  850. int job_id_len, n2size;
  851. unsigned short crc;
  852. int coinbase_len_posthash, coinbase_len_prehash;
  853. uint8_t coinbase_prehash[32];
  854. /* Send out the first stratum message STATIC */
  855. applog(LOG_DEBUG, "%s-%d: Pool stratum message STATIC: %d, %d, %d, %d, %d",
  856. avalon4->drv->name, avalon4->device_id,
  857. pool->coinbase_len,
  858. pool->nonce2_offset,
  859. pool->n2size,
  860. merkle_offset,
  861. pool->merkles);
  862. memset(pkg.data, 0, AVA4_P_DATA_LEN);
  863. tmp = be32toh(pool->coinbase_len);
  864. memcpy(pkg.data, &tmp, 4);
  865. tmp = be32toh(pool->nonce2_offset);
  866. memcpy(pkg.data + 4, &tmp, 4);
  867. n2size = pool->n2size >= 4 ? 4 : pool->n2size;
  868. tmp = be32toh(n2size);
  869. memcpy(pkg.data + 8, &tmp, 4);
  870. tmp = be32toh(merkle_offset);
  871. memcpy(pkg.data + 12, &tmp, 4);
  872. tmp = be32toh(pool->merkles);
  873. memcpy(pkg.data + 16, &tmp, 4);
  874. tmp = be32toh((int)pool->swork.diff);
  875. memcpy(pkg.data + 20, &tmp, 4);
  876. tmp = be32toh((int)pool->pool_no);
  877. memcpy(pkg.data + 24, &tmp, 4);
  878. avalon4_init_pkg(&pkg, AVA4_P_STATIC, 1, 1);
  879. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  880. return;
  881. if (pool->sdiff <= AVA4_DRV_DIFFMAX)
  882. set_target(target, pool->sdiff);
  883. else
  884. set_target(target, AVA4_DRV_DIFFMAX);
  885. memcpy(pkg.data, target, 32);
  886. if (opt_debug) {
  887. char *target_str;
  888. target_str = bin2hex(target, 32);
  889. applog(LOG_DEBUG, "%s-%d: Pool stratum target: %s", avalon4->drv->name, avalon4->device_id, target_str);
  890. free(target_str);
  891. }
  892. avalon4_init_pkg(&pkg, AVA4_P_TARGET, 1, 1);
  893. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  894. return;
  895. memset(pkg.data, 0, AVA4_P_DATA_LEN);
  896. job_id_len = strlen(pool->swork.job_id);
  897. crc = crc16((unsigned char *)pool->swork.job_id, job_id_len);
  898. applog(LOG_DEBUG, "%s-%d: Pool stratum message JOBS_ID[%04x]: %s",
  899. avalon4->drv->name, avalon4->device_id,
  900. crc, pool->swork.job_id);
  901. pkg.data[0] = (crc & 0xff00) >> 8;
  902. pkg.data[1] = crc & 0x00ff;
  903. avalon4_init_pkg(&pkg, AVA4_P_JOB_ID, 1, 1);
  904. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  905. return;
  906. coinbase_len_prehash = pool->nonce2_offset - (pool->nonce2_offset % SHA256_BLOCK_SIZE);
  907. coinbase_len_posthash = pool->coinbase_len - coinbase_len_prehash;
  908. sha256_prehash(pool->coinbase, coinbase_len_prehash, coinbase_prehash);
  909. a = (coinbase_len_posthash / AVA4_P_DATA_LEN) + 1;
  910. b = coinbase_len_posthash % AVA4_P_DATA_LEN;
  911. memcpy(pkg.data, coinbase_prehash, 32);
  912. avalon4_init_pkg(&pkg, AVA4_P_COINBASE, 1, a + (b ? 1 : 0));
  913. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  914. return;
  915. applog(LOG_DEBUG, "%s-%d: Pool stratum message modified COINBASE: %d %d",
  916. avalon4->drv->name, avalon4->device_id,
  917. a, b);
  918. for (i = 1; i < a; i++) {
  919. memcpy(pkg.data, pool->coinbase + coinbase_len_prehash + i * 32 - 32, 32);
  920. avalon4_init_pkg(&pkg, AVA4_P_COINBASE, i + 1, a + (b ? 1 : 0));
  921. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  922. return;
  923. }
  924. if (b) {
  925. memset(pkg.data, 0, AVA4_P_DATA_LEN);
  926. memcpy(pkg.data, pool->coinbase + coinbase_len_prehash + i * 32 - 32, b);
  927. avalon4_init_pkg(&pkg, AVA4_P_COINBASE, i + 1, i + 1);
  928. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  929. return;
  930. }
  931. b = pool->merkles;
  932. applog(LOG_DEBUG, "%s-%d: Pool stratum message MERKLES: %d", avalon4->drv->name, avalon4->device_id, b);
  933. for (i = 0; i < b; i++) {
  934. memset(pkg.data, 0, AVA4_P_DATA_LEN);
  935. memcpy(pkg.data, pool->swork.merkle_bin[i], 32);
  936. avalon4_init_pkg(&pkg, AVA4_P_MERKLES, i + 1, b);
  937. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  938. return;
  939. }
  940. applog(LOG_DEBUG, "%s-%d: Pool stratum message HEADER: 4", avalon4->drv->name, avalon4->device_id);
  941. for (i = 0; i < 4; i++) {
  942. memset(pkg.data, 0, AVA4_P_DATA_LEN);
  943. memcpy(pkg.data, pool->header_bin + i * 32, 32);
  944. avalon4_init_pkg(&pkg, AVA4_P_HEADER, i + 1, 4);
  945. if (avalon4_send_bc_pkgs(avalon4, &pkg))
  946. return;
  947. }
  948. if (info->connecter == AVA4_CONNECTER_AUC)
  949. avalon4_auc_getinfo(avalon4);
  950. }
  951. static struct cgpu_info *avalon4_iic_detect(void)
  952. {
  953. int i;
  954. struct avalon4_info *info;
  955. struct cgpu_info *avalon4 = NULL;
  956. struct i2c_ctx *i2c_slave = NULL;
  957. i2c_slave = i2c_slave_open(I2C_BUS, 0);
  958. if (!i2c_slave) {
  959. applog(LOG_ERR, "Avalon4 init iic failed\n");
  960. return NULL;
  961. }
  962. i2c_slave->exit(i2c_slave);
  963. i2c_slave = NULL;
  964. avalon4 = cgcalloc(1, sizeof(*avalon4));
  965. avalon4->drv = &avalon4_drv;
  966. avalon4->deven = DEV_ENABLED;
  967. avalon4->threads = 1;
  968. add_cgpu(avalon4);
  969. applog(LOG_INFO, "%s-%d: Found at %s", avalon4->drv->name, avalon4->device_id,
  970. I2C_BUS);
  971. avalon4->device_data = cgcalloc(sizeof(struct avalon4_info), 1);
  972. info = avalon4->device_data;
  973. info->polling_first = 1;
  974. info->newnonce = 0;
  975. for (i = 0; i < AVA4_DEFAULT_MODULARS; i++) {
  976. info->enable[i] = 0;
  977. info->mod_type[i] = AVA4_TYPE_NULL;
  978. info->fan_pct[i] = AVA4_DEFAULT_FAN_START;
  979. info->set_voltage[i] = opt_avalon4_voltage_min;
  980. memcpy(info->set_smart_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  981. memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  982. info->i2c_slaves[i] = i2c_slave_open(I2C_BUS, i);
  983. if (!info->i2c_slaves[i]) {
  984. applog(LOG_ERR, "Avalon4 init i2c slaves failed\n");
  985. free(avalon4->device_data);
  986. avalon4->device_data = NULL;
  987. free(avalon4);
  988. avalon4 = NULL;
  989. return NULL;
  990. }
  991. }
  992. info->enable[0] = 1;
  993. info->mod_type[0] = AVA4_TYPE_MM40;
  994. info->temp[0] = -273;
  995. info->speed_bingo[0] = opt_avalon4_speed_bingo;
  996. info->speed_error[0] = opt_avalon4_speed_error;
  997. info->connecter = AVA4_CONNECTER_IIC;
  998. return avalon4;
  999. }
  1000. static struct cgpu_info *avalon4_auc_detect(struct libusb_device *dev, struct usb_find_devices *found)
  1001. {
  1002. int i;
  1003. struct avalon4_info *info;
  1004. struct cgpu_info *avalon4 = usb_alloc_cgpu(&avalon4_drv, 1);
  1005. char auc_ver[AVA4_AUC_VER_LEN];
  1006. if (!usb_init(avalon4, dev, found)) {
  1007. applog(LOG_ERR, "Avalon4 failed usb_init");
  1008. avalon4 = usb_free_cgpu(avalon4);
  1009. return NULL;
  1010. }
  1011. /* Avalon4 prefers not to use zero length packets */
  1012. avalon4->nozlp = true;
  1013. /* We try twice on AUC init */
  1014. if (avalon4_auc_init(avalon4, auc_ver) && avalon4_auc_init(avalon4, auc_ver))
  1015. return NULL;
  1016. /* We have an Avalon4 AUC connected */
  1017. avalon4->threads = 1;
  1018. add_cgpu(avalon4);
  1019. update_usb_stats(avalon4);
  1020. applog(LOG_INFO, "%s-%d: Found at %s", avalon4->drv->name, avalon4->device_id,
  1021. avalon4->device_path);
  1022. avalon4->device_data = cgcalloc(sizeof(struct avalon4_info), 1);
  1023. info = avalon4->device_data;
  1024. memcpy(info->auc_version, auc_ver, AVA4_AUC_VER_LEN);
  1025. info->auc_version[AVA4_AUC_VER_LEN] = '\0';
  1026. info->auc_speed = opt_avalon4_aucspeed;
  1027. info->auc_xdelay = opt_avalon4_aucxdelay;
  1028. info->polling_first = 1;
  1029. info->newnonce = 0;
  1030. for (i = 0; i < AVA4_DEFAULT_MODULARS; i++) {
  1031. info->enable[i] = 0;
  1032. info->mod_type[i] = AVA4_TYPE_NULL;
  1033. info->fan_pct[i] = AVA4_DEFAULT_FAN_START;
  1034. info->set_voltage[i] = opt_avalon4_voltage_min;
  1035. memcpy(info->set_smart_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  1036. memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  1037. }
  1038. info->enable[0] = 1;
  1039. info->mod_type[0] = AVA4_TYPE_MM40;
  1040. info->temp[0] = -273;
  1041. info->speed_bingo[0] = opt_avalon4_speed_bingo;
  1042. info->speed_error[0] = opt_avalon4_speed_error;
  1043. info->connecter = AVA4_CONNECTER_AUC;
  1044. return avalon4;
  1045. }
  1046. static inline void avalon4_detect(bool __maybe_unused hotplug)
  1047. {
  1048. usb_detect(&avalon4_drv, avalon4_auc_detect);
  1049. if (!hotplug && opt_avalon4_iic_detect)
  1050. avalon4_iic_detect();
  1051. }
  1052. static bool avalon4_prepare(struct thr_info *thr)
  1053. {
  1054. int i;
  1055. struct cgpu_info *avalon4 = thr->cgpu;
  1056. struct avalon4_info *info = avalon4->device_data;
  1057. info->polling_first = 1;
  1058. memset(&(info->firsthash), 0, sizeof(info->firsthash));
  1059. cgtime(&(info->last_fan));
  1060. cgtime(&(info->last_30s));
  1061. cgtime(&(info->last_5s));
  1062. cgtime(&info->last_stratum);
  1063. cgtime(&info->last_fadj);
  1064. cgtime(&info->last_tcheck);
  1065. cglock_init(&info->update_lock);
  1066. cglock_init(&info->pool0.data_lock);
  1067. cglock_init(&info->pool1.data_lock);
  1068. cglock_init(&info->pool2.data_lock);
  1069. for (i = 0; i < AVA4_DEFAULT_MODULARS; i++)
  1070. info->fan_pct[i] = AVA4_DEFAULT_FAN_START;
  1071. switch (opt_avalon4_miningmode) {
  1072. case AVA4_MOD_ECO:
  1073. opt_avalon4_fan_min = 20;
  1074. opt_avalon4_overheat = 60;
  1075. break;
  1076. case AVA4_MOD_NORMAL:
  1077. opt_avalon4_fan_min = 30;
  1078. opt_avalon4_overheat = 50;
  1079. break;
  1080. case AVA4_MOD_TURBO:
  1081. opt_avalon4_fan_min = 60;
  1082. opt_avalon4_overheat = 49;
  1083. break;
  1084. default:
  1085. break;
  1086. }
  1087. return true;
  1088. }
  1089. static int check_module_exits(struct cgpu_info *avalon4, uint8_t mm_dna[AVA4_MM_DNA_LEN + 1])
  1090. {
  1091. struct avalon4_info *info = avalon4->device_data;
  1092. int i;
  1093. for (i = 0; i < AVA4_DEFAULT_MODULARS; i++) {
  1094. if (info->enable[i]) {
  1095. /* last byte is \0 */
  1096. if (!memcmp(info->mm_dna[i], mm_dna, AVA4_MM_DNA_LEN))
  1097. return 1;
  1098. }
  1099. }
  1100. return 0;
  1101. }
  1102. static void detect_modules(struct cgpu_info *avalon4)
  1103. {
  1104. struct avalon4_info *info = avalon4->device_data;
  1105. struct thr_info *thr = avalon4->thr[0];
  1106. struct avalon4_pkg send_pkg;
  1107. struct avalon4_ret ret_pkg;
  1108. uint32_t tmp;
  1109. int i, j, k, err;
  1110. /* Detect new modules here */
  1111. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  1112. if (info->enable[i])
  1113. continue;
  1114. /* Send out detect pkg */
  1115. applog(LOG_DEBUG, "%s-%d: AVA4_P_DETECT ID[%d]",
  1116. avalon4->drv->name, avalon4->device_id, i);
  1117. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1118. tmp = be32toh(opt_avalon4_freq_min);
  1119. memcpy(send_pkg.data, &tmp, 4);
  1120. tmp = be32toh(opt_avalon4_freq_max);
  1121. memcpy(send_pkg.data + 4, &tmp, 4);
  1122. send_pkg.data[8] = opt_avalon4_ntcb >> 8;
  1123. send_pkg.data[9] = opt_avalon4_ntcb & 0xff;
  1124. tmp = be32toh(i); /* ID */
  1125. memcpy(send_pkg.data + 28, &tmp, 4);
  1126. avalon4_init_pkg(&send_pkg, AVA4_P_DETECT, 1, 1);
  1127. err = avalon4_iic_xfer_pkg(avalon4, AVA4_MODULE_BROADCAST, &send_pkg, &ret_pkg);
  1128. if (err == AVA4_SEND_OK) {
  1129. if (decode_pkg(thr, &ret_pkg, AVA4_MODULE_BROADCAST)) {
  1130. applog(LOG_DEBUG, "%s-%d: Should be AVA4_P_ACKDETECT(%d), but %d",
  1131. avalon4->drv->name, avalon4->device_id, AVA4_P_ACKDETECT, ret_pkg.type);
  1132. continue;
  1133. }
  1134. }
  1135. if (err != AVA4_SEND_OK) {
  1136. applog(LOG_DEBUG, "%s-%d: AVA4_P_DETECT: Failed AUC xfer data with err %d",
  1137. avalon4->drv->name, avalon4->device_id, err);
  1138. break;
  1139. }
  1140. applog(LOG_DEBUG, "%s-%d: Module detect ID[%d]: %d",
  1141. avalon4->drv->name, avalon4->device_id, i, ret_pkg.type);
  1142. if (ret_pkg.type != AVA4_P_ACKDETECT)
  1143. break;
  1144. if (check_module_exits(avalon4, ret_pkg.data))
  1145. continue;
  1146. cgtime(&info->elapsed[i]);
  1147. cgtime(&info->last_finc[i]);
  1148. cgtime(&info->last_fdec[i]);
  1149. cgtime(&info->last_favg[i]);
  1150. info->enable[i] = 1;
  1151. memcpy(info->mm_dna[i], ret_pkg.data, AVA4_MM_DNA_LEN);
  1152. info->mm_dna[i][AVA4_MM_DNA_LEN] = '\0';
  1153. memcpy(info->mm_version[i], ret_pkg.data + AVA4_MM_DNA_LEN, AVA4_MM_VER_LEN);
  1154. memcpy(&tmp, ret_pkg.data + AVA4_MM_DNA_LEN + AVA4_MM_VER_LEN, 4);
  1155. tmp = be32toh(tmp);
  1156. info->mm_version[i][AVA4_MM_VER_LEN] = '\0';
  1157. info->miner_count[i] = AVA4_DEFAULT_MINER_CNT;
  1158. info->asic_count[i] = AVA4_DEFAULT_ASIC_CNT;
  1159. info->total_asics[i] = tmp;
  1160. info->autov[i] = opt_avalon4_autov;
  1161. info->toverheat[i] = opt_avalon4_overheat;
  1162. if (info->toverheat[i] > AVA4_MM40_TEMP_OVERHEAT)
  1163. info->toverheat[i] = AVA4_MM40_TEMP_OVERHEAT;
  1164. info->temp_target[i] = opt_avalon4_temp_target;
  1165. if (info->temp_target[i] > AVA4_MM40_TEMP_TARGET)
  1166. info->temp_target[i] = AVA4_MM40_TEMP_TARGET;
  1167. if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM40_PREFIXSTR, 2))
  1168. info->mod_type[i] = AVA4_TYPE_MM40;
  1169. if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM41_PREFIXSTR, 2))
  1170. info->mod_type[i] = AVA4_TYPE_MM41;
  1171. if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM50_PREFIXSTR, 2)) {
  1172. info->miner_count[i] = AVA4_MM50_MINER_CNT;
  1173. info->asic_count[i] = AVA4_MM50_ASIC_CNT;
  1174. if (opt_avalon4_autov)
  1175. applog(LOG_NOTICE, "%s-%d-%d: Module do not support autov",
  1176. avalon4->drv->name, avalon4->device_id, i);
  1177. info->autov[i] = false;
  1178. info->mod_type[i] = AVA4_TYPE_MM50;
  1179. }
  1180. if (!strncmp((char *)&(info->mm_version[i]), AVA4_MM60_PREFIXSTR, 2)) {
  1181. info->miner_count[i] = AVA4_MM60_MINER_CNT;
  1182. info->asic_count[i] = AVA4_MM60_ASIC_CNT;
  1183. if (opt_avalon4_autov)
  1184. applog(LOG_NOTICE, "%s-%d-%d: Module do not support autov",
  1185. avalon4->drv->name, avalon4->device_id, i);
  1186. info->autov[i] = false;
  1187. info->toverheat[i] = opt_avalon4_overheat;
  1188. if (info->toverheat[i] > AVA4_DEFAULT_TEMP_OVERHEAT)
  1189. info->toverheat[i] = AVA4_DEFAULT_TEMP_OVERHEAT;
  1190. info->temp_target[i] = opt_avalon4_temp_target;
  1191. if (info->temp_target[i] > AVA4_DEFAULT_TEMP_TARGET)
  1192. info->temp_target[i] = AVA4_DEFAULT_TEMP_TARGET;
  1193. info->mod_type[i] = AVA4_TYPE_MM60;
  1194. }
  1195. info->ntime_offset[i] = (opt_avalon4_ntime_offset > info->asic_count[i]) ? info->asic_count[i] : opt_avalon4_ntime_offset;
  1196. info->fan_pct[i] = AVA4_DEFAULT_FAN_START;
  1197. info->set_voltage[i] = opt_avalon4_voltage_min;
  1198. for (j = 0; j < info->miner_count[i]; j++) {
  1199. info->set_voltage_i[i][j] = opt_avalon4_voltage_min;
  1200. info->set_voltage_offset[i][j] = 0;
  1201. info->adjflag[i][j] = 0;
  1202. memset(info->ma_sum[i][j], 0, sizeof(uint8_t) * info->asic_count[i]);
  1203. for (k = 0; k < info->asic_count[i]; k++)
  1204. memset(info->set_frequency_i[i][j][k], 0, sizeof(int) * 3);
  1205. }
  1206. info->led_red[i] = 0;
  1207. for (j = 0; j < AVA4_DEFAULT_ADC_MAX; j++)
  1208. info->adc[i][j] = AVA4_ADC_MAX;
  1209. memset(info->pll_sel, 0, sizeof(info->pll_sel));
  1210. info->saved[i] = 0;
  1211. info->cutoff[i] = 0;
  1212. info->get_frequency[i] = 0;
  1213. memcpy(info->set_smart_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  1214. info->speed_bingo[i] = opt_avalon4_speed_bingo;
  1215. info->speed_error[i] = opt_avalon4_speed_error;
  1216. info->freq_mode[i] = AVA4_FREQ_INIT_MODE;
  1217. applog(LOG_NOTICE, "%s-%d: New module detect! ID[%d]",
  1218. avalon4->drv->name, avalon4->device_id, i);
  1219. if (opt_avalon4_miningmode != AVA4_MOD_CUSTOM) {
  1220. applog(LOG_DEBUG, "%s-%d-%d: Load mm config",
  1221. avalon4->drv->name, avalon4->device_id, i);
  1222. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1223. avalon4_init_pkg(&send_pkg, AVA4_P_GET_VOLT, 1, 1);
  1224. send_pkg.opt = ((1 << 4) | opt_avalon4_miningmode);
  1225. err = avalon4_iic_xfer_pkg(avalon4, i, &send_pkg, &ret_pkg);
  1226. if (err == AVA4_SEND_OK) {
  1227. err = decode_pkg(thr, &ret_pkg, i);
  1228. if (err == 0 && ret_pkg.type == AVA4_P_STATUS_VOLT) {
  1229. applog(LOG_DEBUG, "%s-%d-%d: Load mm config success",
  1230. avalon4->drv->name, avalon4->device_id, i);
  1231. for (j = 0; j < info->miner_count[i]; j++) {
  1232. applog(LOG_DEBUG, "%s-%d-%d: vol-%d = %d",
  1233. avalon4->drv->name, avalon4->device_id, i,
  1234. j, info->get_voltage_i[i][j]);
  1235. info->set_voltage_i[i][j] = info->get_voltage_i[i][j];
  1236. }
  1237. } else {
  1238. applog(LOG_DEBUG, "%s-%d-%d: Load mm config invalid! err = %d, ret_pkg.type 0x%x",
  1239. avalon4->drv->name, avalon4->device_id, i,
  1240. err, ret_pkg.type);
  1241. }
  1242. } else {
  1243. applog(LOG_DEBUG, "%s-%d-%d: Load mm config failed!",
  1244. avalon4->drv->name, avalon4->device_id, i);
  1245. }
  1246. }
  1247. }
  1248. }
  1249. static void detach_module(struct cgpu_info *avalon4, int addr)
  1250. {
  1251. struct avalon4_info *info = avalon4->device_data;
  1252. int i, j;
  1253. info->polling_err_cnt[addr] = 0;
  1254. info->mod_type[addr] = AVA4_TYPE_NULL;
  1255. info->enable[addr] = 0;
  1256. info->get_voltage[addr] = 0;
  1257. info->get_frequency[addr] = 0;
  1258. info->power_good[addr] = 0;
  1259. info->error_code[addr] = 0;
  1260. info->local_work[addr] = 0;
  1261. info->local_works[addr] = 0;
  1262. info->hw_work[addr] = 0;
  1263. info->hw_works[addr] = 0;
  1264. info->total_asics[addr] = 0;
  1265. info->toverheat[addr] = opt_avalon4_overheat;
  1266. info->temp_target[addr] = opt_avalon4_temp_target;
  1267. info->speed_bingo[addr] = opt_avalon4_speed_bingo;
  1268. info->speed_error[addr] = opt_avalon4_speed_error;
  1269. memset(info->set_frequency[addr], 0, sizeof(int) * 3);
  1270. for (i = 0; i < AVA4_DEFAULT_ADJ_TIMES; i++) {
  1271. info->lw5[addr][i] = 0;
  1272. info->hw5[addr][i] = 0;
  1273. }
  1274. for (i = 0; i < info->miner_count[addr]; i++) {
  1275. info->matching_work[addr][i] = 0;
  1276. memset(info->chipmatching_work[addr][i], 0, sizeof(int) * info->asic_count[addr]);
  1277. info->local_works_i[addr][i] = 0;
  1278. info->hw_works_i[addr][i] = 0;
  1279. memset(info->lw5_i[addr][i], 0, AVA4_DEFAULT_ADJ_TIMES * sizeof(uint32_t));
  1280. memset(info->hw5_i[addr][i], 0, AVA4_DEFAULT_ADJ_TIMES * sizeof(uint32_t));
  1281. memset(info->ma_sum[addr][i], 0, sizeof(uint8_t) * info->asic_count[addr]);
  1282. for (j = 0; j < info->asic_count[addr]; j++)
  1283. memset(info->set_frequency_i[addr][i][j], 0, sizeof(int) * 3);
  1284. }
  1285. info->freq_mode[addr] = AVA4_FREQ_INIT_MODE;
  1286. applog(LOG_NOTICE, "%s-%d: Module detached! ID[%d]",
  1287. avalon4->drv->name, avalon4->device_id, addr);
  1288. }
  1289. static int polling(struct cgpu_info *avalon4)
  1290. {
  1291. struct avalon4_info *info = avalon4->device_data;
  1292. struct thr_info *thr = avalon4->thr[0];
  1293. struct avalon4_pkg send_pkg;
  1294. struct avalon4_ret ar;
  1295. int i, tmp, ret, decode_err = 0, do_polling = 0;
  1296. struct timeval current_fan;
  1297. int do_adjust_fan = 0;
  1298. uint32_t fan_pwm;
  1299. double device_tdiff;
  1300. if (info->polling_first) {
  1301. cgsleep_ms(600);
  1302. info->polling_first = 0;
  1303. }
  1304. cgtime(&current_fan);
  1305. device_tdiff = tdiff(&current_fan, &(info->last_fan));
  1306. if (device_tdiff > 2.0 || device_tdiff < 0) {
  1307. cgtime(&info->last_fan);
  1308. do_adjust_fan = 1;
  1309. }
  1310. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  1311. if (!info->enable[i])
  1312. continue;
  1313. do_polling = 1;
  1314. cgsleep_ms(opt_avalon4_polling_delay);
  1315. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1316. /* Red LED */
  1317. tmp = be32toh(info->led_red[i]);
  1318. memcpy(send_pkg.data, &tmp, 4);
  1319. /* Adjust fan every 10 seconds*/
  1320. if (do_adjust_fan) {
  1321. fan_pwm = adjust_fan(info, i);
  1322. fan_pwm |= 0x80000000;
  1323. tmp = be32toh(fan_pwm);
  1324. memcpy(send_pkg.data + 4, &tmp, 4);
  1325. }
  1326. avalon4_init_pkg(&send_pkg, AVA4_P_POLLING, 1, 1);
  1327. ret = avalon4_iic_xfer_pkg(avalon4, i, &send_pkg, &ar);
  1328. if (ret == AVA4_SEND_OK)
  1329. decode_err = decode_pkg(thr, &ar, i);
  1330. if (ret != AVA4_SEND_OK || decode_err) {
  1331. info->polling_err_cnt[i]++;
  1332. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1333. avalon4_init_pkg(&send_pkg, AVA4_P_RSTMMTX, 1, 1);
  1334. avalon4_iic_xfer_pkg(avalon4, i, &send_pkg, NULL);
  1335. if (info->polling_err_cnt[i] >= 4)
  1336. detach_module(avalon4, i);
  1337. }
  1338. if (ret == AVA4_SEND_OK && !decode_err) {
  1339. info->polling_err_cnt[i] = 0;
  1340. if (info->mm_dna[i][AVA4_MM_DNA_LEN - 1] != ar.opt) {
  1341. applog(LOG_ERR, "%s-%d-%d: Dup address found %d-%d",
  1342. avalon4->drv->name, avalon4->device_id, i,
  1343. info->mm_dna[i][AVA4_MM_DNA_LEN - 1], ar.opt);
  1344. hexdump((uint8_t *)&ar, sizeof(ar));
  1345. detach_module(avalon4, i);
  1346. }
  1347. }
  1348. }
  1349. if (!do_polling)
  1350. detect_modules(avalon4);
  1351. return 0;
  1352. }
  1353. static void copy_pool_stratum(struct pool *pool_stratum, struct pool *pool)
  1354. {
  1355. int i;
  1356. int merkles = pool->merkles, job_id_len;
  1357. size_t coinbase_len = pool->coinbase_len;
  1358. unsigned short crc;
  1359. if (!pool->swork.job_id)
  1360. return;
  1361. if (pool_stratum->swork.job_id) {
  1362. job_id_len = strlen(pool->swork.job_id);
  1363. crc = crc16((unsigned char *)pool->swork.job_id, job_id_len);
  1364. job_id_len = strlen(pool_stratum->swork.job_id);
  1365. if (crc16((unsigned char *)pool_stratum->swork.job_id, job_id_len) == crc)
  1366. return;
  1367. }
  1368. cg_wlock(&pool_stratum->data_lock);
  1369. free(pool_stratum->swork.job_id);
  1370. free(pool_stratum->nonce1);
  1371. free(pool_stratum->coinbase);
  1372. pool_stratum->coinbase = cgcalloc(coinbase_len, 1);
  1373. memcpy(pool_stratum->coinbase, pool->coinbase, coinbase_len);
  1374. for (i = 0; i < pool_stratum->merkles; i++)
  1375. free(pool_stratum->swork.merkle_bin[i]);
  1376. if (merkles) {
  1377. pool_stratum->swork.merkle_bin = cgrealloc(pool_stratum->swork.merkle_bin,
  1378. sizeof(char *) * merkles + 1);
  1379. for (i = 0; i < merkles; i++) {
  1380. pool_stratum->swork.merkle_bin[i] = cgmalloc(32);
  1381. memcpy(pool_stratum->swork.merkle_bin[i], pool->swork.merkle_bin[i], 32);
  1382. }
  1383. }
  1384. pool_stratum->sdiff = pool->sdiff;
  1385. pool_stratum->coinbase_len = pool->coinbase_len;
  1386. pool_stratum->nonce2_offset = pool->nonce2_offset;
  1387. pool_stratum->n2size = pool->n2size;
  1388. pool_stratum->merkles = pool->merkles;
  1389. pool_stratum->swork.job_id = strdup(pool->swork.job_id);
  1390. pool_stratum->nonce1 = strdup(pool->nonce1);
  1391. memcpy(pool_stratum->ntime, pool->ntime, sizeof(pool_stratum->ntime));
  1392. memcpy(pool_stratum->header_bin, pool->header_bin, sizeof(pool_stratum->header_bin));
  1393. cg_wunlock(&pool_stratum->data_lock);
  1394. }
  1395. static inline int mm_cmp_1512(struct avalon4_info *info, int addr)
  1396. {
  1397. /* >= 1512 return 1 */
  1398. return strncmp(info->mm_version[addr] + 2, "1512", 4) >= 0 ? 1 : 0;
  1399. }
  1400. static inline int mm_cmp_1501(struct avalon4_info *info, int addr)
  1401. {
  1402. /* >= 1501 return 1 */
  1403. return strncmp(info->mm_version[addr] + 2, "1501", 4) >= 0 ? 1 : 0;
  1404. }
  1405. static inline int mm_cmp_d17f4a(struct avalon4_info *info, int addr)
  1406. {
  1407. /* == d17f4a return 1 */
  1408. return strncmp(info->mm_version[addr] + 7, "d17f4a", 6) == 0 ? 1 : 0;
  1409. }
  1410. static void avalon4_set_voltage(struct cgpu_info *avalon4, int addr, int opt)
  1411. {
  1412. struct avalon4_info *info = avalon4->device_data;
  1413. struct avalon4_pkg send_pkg;
  1414. uint16_t tmp;
  1415. uint8_t i;
  1416. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1417. /* Use shifter to set voltage */
  1418. for (i = 0; i < info->miner_count[addr]; i++) {
  1419. tmp = info->set_voltage_i[addr][i] + info->set_voltage_offset[addr][i];
  1420. if (avalon4_freezsafemode)
  1421. tmp = AVA4_FREEZESAFE_VOLTAGE;
  1422. if (info->cutoff[addr])
  1423. tmp = 0;
  1424. if (info->mod_type[addr] == AVA4_TYPE_MM40)
  1425. tmp = encode_voltage_adp3208d(tmp);
  1426. if (info->mod_type[addr] == AVA4_TYPE_MM41)
  1427. tmp = encode_voltage_ncp5392p(tmp);
  1428. if (info->mod_type[addr] == AVA4_TYPE_MM50)
  1429. tmp = encode_voltage_ncp5392p(tmp);
  1430. /* TODO: fix it with the actual board */
  1431. if (info->mod_type[addr] == AVA4_TYPE_MM60)
  1432. tmp = encode_voltage_ncp5392p(tmp);
  1433. tmp = htobe16(tmp);
  1434. memcpy(send_pkg.data + 2 * ((4 + i / 5 * 5) - i + (i / 5 * 5)), &tmp, 2);
  1435. }
  1436. /* Package the data */
  1437. avalon4_init_pkg(&send_pkg, AVA4_P_SET_VOLT, 1, 1);
  1438. send_pkg.opt = opt;
  1439. if (addr == AVA4_MODULE_BROADCAST)
  1440. avalon4_send_bc_pkgs(avalon4, &send_pkg);
  1441. else
  1442. avalon4_iic_xfer_pkg(avalon4, addr, &send_pkg, NULL);
  1443. }
  1444. static uint32_t avalon4_get_cpm(unsigned int freq)
  1445. {
  1446. unsigned int i;
  1447. for (i = 0; i < sizeof(g_freq_array) / sizeof(g_freq_array[0]); i++)
  1448. if (freq >= g_freq_array[i][0] && freq < g_freq_array[i+1][0])
  1449. return g_freq_array[i][1];
  1450. /* return the lowest freq if not found */
  1451. return g_freq_array[0][1];
  1452. }
  1453. static void avalon4_set_freq(struct cgpu_info *avalon4, int addr, uint8_t miner_id, uint8_t chip_id, unsigned int freq[])
  1454. {
  1455. struct avalon4_info *info = avalon4->device_data;
  1456. struct avalon4_pkg send_pkg;
  1457. uint32_t tmp;
  1458. uint8_t set = 0;
  1459. int i, j;
  1460. /* Note: 0 (miner_id and chip_id) is reserved for all devices */
  1461. if (!miner_id || !chip_id) {
  1462. if (memcmp(freq, info->set_frequency[addr], sizeof(int) * 3) || !info->get_frequency[addr]) {
  1463. memcpy(info->set_frequency[addr], freq, sizeof(int) * 3);
  1464. for (i = 0; i < info->miner_count[addr]; i++) {
  1465. for (j = 0; j < info->asic_count[addr]; j++)
  1466. memcpy(info->set_frequency_i[addr][i][j], info->set_frequency[addr], sizeof(int) * 3);
  1467. }
  1468. set = 1;
  1469. }
  1470. } else {
  1471. if (memcmp(freq, info->set_frequency_i[addr][miner_id - 1][chip_id - 1], sizeof(int) * 3)) {
  1472. memcpy(info->set_frequency_i[addr][miner_id - 1][chip_id - 1], freq, sizeof(int) * 3);
  1473. set = 1;
  1474. }
  1475. }
  1476. if (avalon4_freezsafemode) {
  1477. info->set_frequency[addr][0] = info->set_frequency[addr][1] = info->set_frequency[addr][2] = AVA4_FREEZESAFE_FREQUENCY;
  1478. memcpy(freq, info->set_frequency[addr], sizeof(int) * 3);
  1479. miner_id = 0;
  1480. chip_id = 0;
  1481. set = 1;
  1482. }
  1483. if (info->cutoff[addr]) {
  1484. info->set_frequency[addr][0] = AVA4_DEFAULT_FREQUENCY_MIN;
  1485. info->set_frequency[addr][1] = AVA4_DEFAULT_FREQUENCY_MIN;
  1486. info->set_frequency[addr][2] = AVA4_DEFAULT_FREQUENCY_MIN;
  1487. memcpy(freq, info->set_frequency[addr], sizeof(int) * 3);
  1488. miner_id = 0;
  1489. chip_id = 0;
  1490. set = 1;
  1491. }
  1492. if (!set)
  1493. return;
  1494. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1495. if (info->mod_type[addr] == AVA4_TYPE_MM60) {
  1496. tmp = be32toh(freq[0]);
  1497. memcpy(send_pkg.data, &tmp, 4);
  1498. tmp = be32toh(freq[1]);
  1499. memcpy(send_pkg.data + 4, &tmp, 4);
  1500. tmp = be32toh(freq[2]);
  1501. memcpy(send_pkg.data + 8, &tmp, 4);
  1502. } else {
  1503. tmp = avalon4_get_cpm(freq[0]);
  1504. tmp = be32toh(tmp);
  1505. memcpy(send_pkg.data, &tmp, 4);
  1506. tmp = avalon4_get_cpm(freq[1]);
  1507. tmp = be32toh(tmp);
  1508. memcpy(send_pkg.data + 4, &tmp, 4);
  1509. tmp = avalon4_get_cpm(freq[2]);
  1510. tmp = be32toh(tmp);
  1511. memcpy(send_pkg.data + 8, &tmp, 4);
  1512. }
  1513. applog(LOG_DEBUG, "%s-%d-%d: avalon4 set freq (%d-%d-%d)",
  1514. avalon4->drv->name, avalon4->device_id, addr,
  1515. freq[0],
  1516. freq[1],
  1517. freq[2]);
  1518. send_pkg.data[12] = miner_id;
  1519. /* Package the data */
  1520. avalon4_init_pkg(&send_pkg, AVA4_P_SET_FREQ, 1, 1);
  1521. send_pkg.opt = chip_id;
  1522. if (addr == AVA4_MODULE_BROADCAST)
  1523. avalon4_send_bc_pkgs(avalon4, &send_pkg);
  1524. else
  1525. avalon4_iic_xfer_pkg(avalon4, addr, &send_pkg, NULL);
  1526. }
  1527. static void avalon4_stratum_set(struct cgpu_info *avalon4, struct pool *pool, int addr)
  1528. {
  1529. struct avalon4_info *info = avalon4->device_data;
  1530. struct avalon4_pkg send_pkg;
  1531. uint32_t tmp = 0, range, start, volt;
  1532. /* Set the NTime, Voltage and Frequency */
  1533. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1534. if (info->ntime_offset[addr] != info->asic_count[addr]) {
  1535. tmp = info->ntime_offset[addr] | 0x80000000;
  1536. tmp = be32toh(tmp);
  1537. memcpy(send_pkg.data, &tmp, 4);
  1538. }
  1539. volt = info->set_voltage[addr];
  1540. if (avalon4_freezsafemode)
  1541. volt = AVA4_FREEZESAFE_VOLTAGE;
  1542. if (info->cutoff[addr])
  1543. volt = 0;
  1544. if (info->mod_type[addr] == AVA4_TYPE_MM40)
  1545. tmp = encode_voltage_adp3208d(volt);
  1546. if (info->mod_type[addr] == AVA4_TYPE_MM41)
  1547. tmp = encode_voltage_ncp5392p(volt);
  1548. if (info->mod_type[addr] == AVA4_TYPE_MM50)
  1549. tmp = encode_voltage_ncp5392p(volt);
  1550. /* TODO: fix it with the actual board */
  1551. if (info->mod_type[addr] == AVA4_TYPE_MM60)
  1552. tmp = encode_voltage_ncp5392p(volt);
  1553. tmp = be32toh(tmp);
  1554. memcpy(send_pkg.data + 4, &tmp, 4);
  1555. tmp = info->set_frequency[addr][0] | (info->set_frequency[addr][1] << 10) | (info->set_frequency[addr][2] << 20);
  1556. if (avalon4_freezsafemode)
  1557. tmp = AVA4_FREEZESAFE_FREQUENCY | (AVA4_FREEZESAFE_FREQUENCY << 10) | (AVA4_FREEZESAFE_FREQUENCY << 20);
  1558. if (info->cutoff[addr])
  1559. tmp = AVA4_DEFAULT_FREQUENCY_MIN | (AVA4_DEFAULT_FREQUENCY_MIN << 10) | (AVA4_DEFAULT_FREQUENCY_MIN << 20);
  1560. tmp = be32toh(tmp);
  1561. memcpy(send_pkg.data + 8, &tmp, 4);
  1562. /* Configure the nonce2 offset and range */
  1563. if (pool->n2size == 3)
  1564. range = 0xffffff / (total_devices ? total_devices : 1);
  1565. else
  1566. range = 0xffffffff / (total_devices ? total_devices : 1);
  1567. start = range * avalon4->device_id;
  1568. tmp = be32toh(start);
  1569. memcpy(send_pkg.data + 12, &tmp, 4);
  1570. tmp = be32toh(range);
  1571. memcpy(send_pkg.data + 16, &tmp, 4);
  1572. /* adjust flag [0-5]: reserved, 6: nonce check, 7: autof*/
  1573. tmp = 1;
  1574. if (!opt_avalon4_smart_speed)
  1575. tmp = 0;
  1576. if (opt_avalon4_noncecheck)
  1577. tmp |= 2;
  1578. send_pkg.data[20] = tmp & 0xff;
  1579. send_pkg.data[21] = info->speed_bingo[addr];
  1580. send_pkg.data[22] = info->speed_error[addr];
  1581. /* Package the data */
  1582. avalon4_init_pkg(&send_pkg, AVA4_P_SET, 1, 1);
  1583. if (addr == AVA4_MODULE_BROADCAST)
  1584. avalon4_send_bc_pkgs(avalon4, &send_pkg);
  1585. else
  1586. avalon4_iic_xfer_pkg(avalon4, addr, &send_pkg, NULL);
  1587. }
  1588. static void avalon4_stratum_finish(struct cgpu_info *avalon4)
  1589. {
  1590. struct avalon4_pkg send_pkg;
  1591. memset(send_pkg.data, 0, AVA4_P_DATA_LEN);
  1592. avalon4_init_pkg(&send_pkg, AVA4_P_FINISH, 1, 1);
  1593. avalon4_send_bc_pkgs(avalon4, &send_pkg);
  1594. }
  1595. static void avalon4_adjust_vf(struct cgpu_info *avalon4, int addr, uint8_t save)
  1596. {
  1597. struct avalon4_info *info = avalon4->device_data;
  1598. if (info->mod_type[addr] == AVA4_TYPE_MM50) {
  1599. avalon4_set_voltage(avalon4, addr, ((save << 4) | opt_avalon4_miningmode));
  1600. avalon4_set_freq(avalon4, addr, 0, 0, opt_avalon4_freq);
  1601. }
  1602. if ((info->mod_type[addr] == AVA4_TYPE_MM41) &&
  1603. mm_cmp_1501(info, addr)) {
  1604. avalon4_set_voltage(avalon4, addr, ((save << 4) | opt_avalon4_miningmode));
  1605. avalon4_set_freq(avalon4, addr, 0, 0, opt_avalon4_freq);
  1606. }
  1607. if ((info->mod_type[addr] == AVA4_TYPE_MM40) &&
  1608. mm_cmp_1501(info, addr)) {
  1609. if (!mm_cmp_d17f4a(info, addr)) {
  1610. avalon4_set_voltage(avalon4, addr, ((save << 4) | opt_avalon4_miningmode));
  1611. avalon4_set_freq(avalon4, addr, 0, 0, opt_avalon4_freq);
  1612. }
  1613. }
  1614. }
  1615. static void avalon4_freq_inc(struct cgpu_info *avalon4, int addr, unsigned int freq[], unsigned int val)
  1616. {
  1617. struct avalon4_info *info = avalon4->device_data;
  1618. int i;
  1619. if (info->mod_type[addr] == AVA4_TYPE_MM60) {
  1620. for (i = 0; i < 3; i++) {
  1621. if ((freq[i] + val) < AVA4_MM60_FREQUENCY_MAX)
  1622. freq[i] += val;
  1623. else
  1624. freq[i] = AVA4_MM60_FREQUENCY_MAX;
  1625. }
  1626. }
  1627. }
  1628. static void avalon4_freq_dec(struct cgpu_info *avalon4, int addr, unsigned int freq[], unsigned int val)
  1629. {
  1630. struct avalon4_info *info = avalon4->device_data;
  1631. int i;
  1632. if (info->mod_type[addr] == AVA4_TYPE_MM60) {
  1633. for (i = 0; i < 3; i++) {
  1634. if (freq[i] <= val) {
  1635. freq[i] = AVA4_DEFAULT_FREQUENCY_MIN;
  1636. continue;
  1637. }
  1638. if ((freq[i] - val) >= AVA4_DEFAULT_FREQUENCY_MIN)
  1639. freq[i] -= val;
  1640. else
  1641. freq[i] = AVA4_DEFAULT_FREQUENCY_MIN;
  1642. }
  1643. }
  1644. }
  1645. static void avalon4_update(struct cgpu_info *avalon4)
  1646. {
  1647. struct avalon4_info *info = avalon4->device_data;
  1648. struct thr_info *thr = avalon4->thr[0];
  1649. struct work *work;
  1650. struct pool *pool;
  1651. int coinbase_len_posthash, coinbase_len_prehash;
  1652. int i;
  1653. int max_temp;
  1654. applog(LOG_DEBUG, "%s-%d: New stratum: restart: %d, update: %d",
  1655. avalon4->drv->name, avalon4->device_id,
  1656. thr->work_restart, thr->work_update);
  1657. thr->work_update = false;
  1658. thr->work_restart = false;
  1659. /* Step 1: Make sure pool is ready */
  1660. work = get_work(thr, thr->id);
  1661. discard_work(work); /* Don't leak memory */
  1662. /* Step 2: MM protocol check */
  1663. pool = current_pool();
  1664. if (!pool->has_stratum)
  1665. quit(1, "%s-%d: MM has to use stratum pools", avalon4->drv->name, avalon4->device_id);
  1666. coinbase_len_prehash = pool->nonce2_offset - (pool->nonce2_offset % SHA256_BLOCK_SIZE);
  1667. coinbase_len_posthash = pool->coinbase_len - coinbase_len_prehash;
  1668. if (coinbase_len_posthash + SHA256_BLOCK_SIZE > AVA4_P_COINBASE_SIZE) {
  1669. applog(LOG_ERR, "%s-%d: MM pool modified coinbase length(%d) is more than %d",
  1670. avalon4->drv->name, avalon4->device_id,
  1671. coinbase_len_posthash + SHA256_BLOCK_SIZE, AVA4_P_COINBASE_SIZE);
  1672. return;
  1673. }
  1674. if (pool->merkles > AVA4_P_MERKLES_COUNT) {
  1675. applog(LOG_ERR, "%s-%d: MM merkles has to be less then %d", avalon4->drv->name, avalon4->device_id, AVA4_P_MERKLES_COUNT);
  1676. return;
  1677. }
  1678. if (pool->n2size < 3) {
  1679. applog(LOG_ERR, "%s-%d: MM nonce2 size has to be >= 3 (%d)", avalon4->drv->name, avalon4->device_id, pool->n2size);
  1680. return;
  1681. }
  1682. cg_wlock(&info->update_lock);
  1683. /* Step 3: Try to detect new modules */
  1684. detect_modules(avalon4);
  1685. /* Step 4: Send out stratum pkgs */
  1686. cg_rlock(&pool->data_lock);
  1687. cgtime(&info->last_stratum);
  1688. info->pool_no = pool->pool_no;
  1689. copy_pool_stratum(&info->pool2, &info->pool1);
  1690. copy_pool_stratum(&info->pool1, &info->pool0);
  1691. copy_pool_stratum(&info->pool0, pool);
  1692. avalon4_stratum_pkgs(avalon4, pool);
  1693. cg_runlock(&pool->data_lock);
  1694. /* Step 5: Configure the parameter from outside */
  1695. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  1696. if (!info->enable[i])
  1697. continue;
  1698. max_temp = get_temp_max(info, i);
  1699. if (max_temp >= info->toverheat[i])
  1700. info->cutoff[i] = 1;
  1701. if (info->cutoff[i] && (max_temp <= (info->toverheat[i] - 10)))
  1702. info->cutoff[i] = 0;
  1703. if (info->cutoff[i])
  1704. info->polling_first = 1;
  1705. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  1706. switch (info->freq_mode[i]) {
  1707. case AVA4_FREQ_INIT_MODE:
  1708. memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  1709. memcpy(info->set_smart_frequency[i], info->set_frequency[i], sizeof(info->set_frequency[i]));
  1710. if (info->cutoff[i]) {
  1711. info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN;
  1712. info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN;
  1713. info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN;
  1714. info->freq_mode[i] = AVA4_FREQ_CUTOFF_MODE;
  1715. break;
  1716. }
  1717. if (mm_cmp_1512(info, i) && (opt_avalon4_smart_speed != AVA4_DEFAULT_SMARTSPEED_OFF))
  1718. info->freq_mode[i] = AVA4_FREQ_PLLADJ_MODE;
  1719. break;
  1720. case AVA4_FREQ_CUTOFF_MODE:
  1721. info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN;
  1722. info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN;
  1723. info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN;
  1724. if (!info->cutoff[i]) {
  1725. memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  1726. memcpy(info->set_smart_frequency[i], info->set_frequency[i], sizeof(info->set_frequency[i]));
  1727. info->freq_mode[i] = AVA4_FREQ_INIT_MODE;
  1728. }
  1729. break;
  1730. case AVA4_FREQ_TEMPADJ_MODE:
  1731. if (info->cutoff[i]) {
  1732. info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN;
  1733. info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN;
  1734. info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN;
  1735. info->freq_mode[i] = AVA4_FREQ_CUTOFF_MODE;
  1736. break;
  1737. }
  1738. if (get_temp_max(info, i) <= (info->temp_target[i] - opt_avalon4_delta_temp)) {
  1739. memcpy(info->set_frequency[i], opt_avalon4_freq, sizeof(opt_avalon4_freq));
  1740. memcpy(info->set_smart_frequency[i], info->set_frequency[i], sizeof(info->set_frequency[i]));
  1741. info->freq_mode[i] = AVA4_FREQ_INIT_MODE;
  1742. break;
  1743. }
  1744. /* Adjust frequency when scanhash */
  1745. break;
  1746. case AVA4_FREQ_PLLADJ_MODE:
  1747. if (info->cutoff[i]) {
  1748. info->set_frequency[i][0] = AVA4_DEFAULT_FREQUENCY_MIN;
  1749. info->set_frequency[i][1] = AVA4_DEFAULT_FREQUENCY_MIN;
  1750. info->set_frequency[i][2] = AVA4_DEFAULT_FREQUENCY_MIN;
  1751. info->freq_mode[i] = AVA4_FREQ_CUTOFF_MODE;
  1752. break;
  1753. }
  1754. break;
  1755. default:
  1756. applog(LOG_ERR, "%s-%d-%d: Invalid frequency mode %d",
  1757. avalon4->drv->name, avalon4->device_id, i, info->freq_mode[i]);
  1758. break;
  1759. }
  1760. avalon4_stratum_set(avalon4, pool, i);
  1761. } else {
  1762. avalon4_stratum_set(avalon4, pool, i);
  1763. avalon4_adjust_vf(avalon4, i, 0);
  1764. }
  1765. }
  1766. /* Step 6: Send out finish pkg */
  1767. avalon4_stratum_finish(avalon4);
  1768. cg_wunlock(&info->update_lock);
  1769. }
  1770. static int64_t avalon4_scanhash(struct thr_info *thr)
  1771. {
  1772. struct cgpu_info *avalon4 = thr->cgpu;
  1773. struct avalon4_info *info = avalon4->device_data;
  1774. struct timeval current;
  1775. double device_tdiff, hwp;
  1776. uint32_t a = 0, b = 0;
  1777. int64_t h;
  1778. int i, j, k, count = 0;
  1779. uint32_t tmp;
  1780. int max_temp;
  1781. if ((info->connecter == AVA4_CONNECTER_AUC) &&
  1782. (unlikely(avalon4->usbinfo.nodev))) {
  1783. applog(LOG_ERR, "%s-%d: Device disappeared, shutting down thread",
  1784. avalon4->drv->name, avalon4->device_id);
  1785. return -1;
  1786. }
  1787. /* Step 1: Stop polling the device if there is no stratum in 3 minutes, network is down */
  1788. cgtime(&current);
  1789. avalon4_freezsafemode = 0;
  1790. if (tdiff(&current, &(info->last_stratum)) > 180.0) {
  1791. if(!opt_avalon4_freezesafe)
  1792. return 0;
  1793. if(opt_avalon4_freezesafe)
  1794. avalon4_freezsafemode = 1;
  1795. }
  1796. /* Step 2: Polling */
  1797. cg_rlock(&info->update_lock);
  1798. polling(avalon4);
  1799. cg_runlock(&info->update_lock);
  1800. /* Step 3: Adjust voltage */
  1801. cgtime(&current);
  1802. device_tdiff = tdiff(&current, &(info->last_5s));
  1803. if (device_tdiff >= 5.0 || device_tdiff < 0) {
  1804. copy_time(&info->last_5s, &current);
  1805. if (++info->i_5s >= AVA4_DEFAULT_ADJ_TIMES)
  1806. info->i_5s = 0;
  1807. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  1808. if (!info->enable[i])
  1809. continue;
  1810. info->lw5[i][info->i_5s] = 0;
  1811. info->hw5[i][info->i_5s] = 0;
  1812. for(j = 0; j < info->miner_count[i]; j++) {
  1813. info->lw5_i[i][j][info->i_5s] = 0;
  1814. info->hw5_i[i][j][info->i_5s] = 0;
  1815. }
  1816. }
  1817. }
  1818. cgtime(&current);
  1819. device_tdiff = tdiff(&current, &(info->last_30s));
  1820. if (opt_avalon4_autov && (device_tdiff > 30.0 || device_tdiff < 0)) {
  1821. copy_time(&info->last_30s, &current);
  1822. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  1823. uint8_t individual = 0;
  1824. if (!info->enable[i])
  1825. continue;
  1826. if (!info->autov[i])
  1827. continue;
  1828. if (info->mod_type[i] == AVA4_TYPE_MM60)
  1829. continue;
  1830. if (info->mod_type[i] == AVA4_TYPE_MM50)
  1831. individual = 1;
  1832. if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i))
  1833. individual = 1;
  1834. if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) {
  1835. if (!mm_cmp_d17f4a(info, i))
  1836. individual = 1;
  1837. }
  1838. if (info->cutoff[i]) {
  1839. for (j = 0; j < info->miner_count[i]; j++)
  1840. info->adjflag[i][j] = 0;
  1841. continue;
  1842. }
  1843. if (!individual) {
  1844. a = 0;
  1845. b = 0;
  1846. for (j = 0; j < AVA4_DEFAULT_ADJ_TIMES; j++) {
  1847. a += info->lw5[i][j];
  1848. b += info->hw5[i][j];
  1849. }
  1850. hwp = a ? (double)b / (double)a : 0;
  1851. if (hwp > AVA4_DH_INC && (info->set_voltage[i] < info->set_voltage[0] + 125)) {
  1852. info->set_voltage[i] += 125;
  1853. for (j = 0; j < info->miner_count[i]; j++) {
  1854. info->set_voltage_i[i][j] += 125;
  1855. }
  1856. info->adjflag[i][0] = 1;
  1857. applog(LOG_NOTICE, "%s-%d: Automatic increase module[%d] voltage to %d",
  1858. avalon4->drv->name, avalon4->device_id, i, info->set_voltage[i]);
  1859. }
  1860. if (!info->adjflag[i][0] && hwp < AVA4_DH_DEC && (info->set_voltage[i] > info->set_voltage[0] - (4 * 125))) {
  1861. info->set_voltage[i] -= 125;
  1862. for (j = 0; j < info->miner_count[i]; j++) {
  1863. info->set_voltage_i[i][j] -= 125;
  1864. }
  1865. applog(LOG_NOTICE, "%s-%d: Automatic decrease module[%d] voltage to %d",
  1866. avalon4->drv->name, avalon4->device_id, i, info->set_voltage[i]);
  1867. }
  1868. } else {
  1869. for (j = 0; j < info->miner_count[i]; j++) {
  1870. a = 0;
  1871. b = 0;
  1872. for (k = 0; k < AVA4_DEFAULT_ADJ_TIMES; k++) {
  1873. a += info->lw5_i[i][j][k];
  1874. b += info->hw5_i[i][j][k];
  1875. }
  1876. hwp = a ? (double)b / (double)a : 0;
  1877. if (hwp > AVA4_DH_INC && (info->set_voltage_i[i][j] < info->set_voltage[0] + (2 * 125))) {
  1878. //FIX ME: How to deal with set_voltage ?
  1879. info->set_voltage_i[i][j] += 125;
  1880. info->adjflag[i][j] = 1;
  1881. applog(LOG_NOTICE, "%s-%d: Automatic increase module[%d-%d] voltage to %d",
  1882. avalon4->drv->name, avalon4->device_id, i, j, info->set_voltage_i[i][j]);
  1883. }
  1884. if (!info->adjflag[i][j] && hwp < AVA4_DH_DEC && (info->set_voltage_i[i][j] > info->set_voltage[0] - (12 * 125))) {
  1885. //FIX ME: How to deal with set_voltage ?
  1886. info->set_voltage_i[i][j] -= 125;
  1887. applog(LOG_NOTICE, "%s-%d: Automatic decrease module[%d-%d] voltage to %d",
  1888. avalon4->drv->name, avalon4->device_id, i, j, info->set_voltage_i[i][j]);
  1889. }
  1890. }
  1891. }
  1892. /* Save config when run 10m */
  1893. cgtime(&current);
  1894. device_tdiff = tdiff(&current, &(info->elapsed[i]));
  1895. if (device_tdiff >= 600.0) {
  1896. if (!info->saved[i]) {
  1897. applog(LOG_NOTICE, "%s-%d-%d: Avalon4 saved voltage !",
  1898. avalon4->drv->name, avalon4->device_id, i);
  1899. avalon4_adjust_vf(avalon4, i, 1);
  1900. info->saved[i] = 1;
  1901. } else
  1902. avalon4_adjust_vf(avalon4, i, 0);
  1903. } else
  1904. avalon4_adjust_vf(avalon4, i, 0);
  1905. if (((int)device_tdiff % 3600) >= 0 || ((int)device_tdiff % 3600) < 3) {
  1906. for (j = 0; j < info->miner_count[i]; j++)
  1907. info->adjflag[i][j] = 0;
  1908. }
  1909. }
  1910. }
  1911. /* Step 4: Adjust frequency */
  1912. cgtime(&current);
  1913. device_tdiff = tdiff(&current, &(info->last_tcheck));
  1914. if (device_tdiff > 3.0 || device_tdiff < 0) {
  1915. copy_time(&info->last_tcheck, &current);
  1916. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  1917. if (!info->enable[i])
  1918. continue;
  1919. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  1920. max_temp = get_temp_max(info, i);
  1921. if (info->freq_mode[i] != AVA4_FREQ_TEMPADJ_MODE) {
  1922. if (max_temp >= opt_avalon4_freqadj_temp) {
  1923. info->last_maxtemp[i] = max_temp;
  1924. cg_wlock(&info->update_lock);
  1925. avalon4_freq_dec(avalon4, i, info->set_smart_frequency[i], opt_avalon4_delta_freq + 50);
  1926. avalon4_set_freq(avalon4, i, 0, 0, info->set_smart_frequency[i]);
  1927. applog(LOG_DEBUG, "%s-%d-%d: set freq after temp check (%d-%d-%d)",
  1928. avalon4->drv->name, avalon4->device_id, i,
  1929. info->set_smart_frequency[i][0],
  1930. info->set_smart_frequency[i][1],
  1931. info->set_smart_frequency[i][2]);
  1932. info->freq_mode[i] = AVA4_FREQ_TEMPADJ_MODE;
  1933. /* Update time for frequency adjustment */
  1934. copy_time(&info->last_fadj, &current);
  1935. cg_wunlock(&info->update_lock);
  1936. }
  1937. }
  1938. }
  1939. }
  1940. }
  1941. device_tdiff = tdiff(&current, &(info->last_fadj));
  1942. if (device_tdiff > opt_avalon4_freqadj_time || device_tdiff < 0) {
  1943. copy_time(&info->last_fadj, &current);
  1944. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  1945. if (!info->enable[i])
  1946. continue;
  1947. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  1948. switch (info->freq_mode[i]) {
  1949. case AVA4_FREQ_TEMPADJ_MODE:
  1950. if (info->cutoff[i])
  1951. break;
  1952. max_temp = get_temp_max(info, i);
  1953. if (max_temp <= info->temp_target[i]) {
  1954. applog(LOG_DEBUG, "AVA4_FREQ_TEMPADJ_MODE -> AVA4_FREQ_INIT_MODE");
  1955. break;
  1956. }
  1957. /* if max_temp goes down ,then we don't need adjust frequency */
  1958. if (info->last_maxtemp[i] > max_temp) {
  1959. applog(LOG_DEBUG, "AVA4_FREQ_TEMPADJ_MODE temp goes down");
  1960. info->last_maxtemp[i] = get_temp_max(info, i);
  1961. break;
  1962. }
  1963. info->last_maxtemp[i] = get_temp_max(info, i);
  1964. cg_wlock(&info->update_lock);
  1965. avalon4_freq_dec(avalon4, i, info->set_smart_frequency[i], opt_avalon4_delta_freq);
  1966. avalon4_set_freq(avalon4, i, 0, 0, info->set_smart_frequency[i]);
  1967. applog(LOG_DEBUG, "%s-%d-%d: update freq (%d-%d-%d) AVA4_FREQ_PLLADJ_MODE",
  1968. avalon4->drv->name, avalon4->device_id, i,
  1969. info->set_smart_frequency[i][0],
  1970. info->set_smart_frequency[i][1],
  1971. info->set_smart_frequency[i][2]);
  1972. cg_wunlock(&info->update_lock);
  1973. break;
  1974. case AVA4_FREQ_PLLADJ_MODE:
  1975. /* AVA4_DEFAULT_SMARTSPEED_MODE1: auto speed by A3218 chips */
  1976. cgtime(&current);
  1977. if (opt_avalon4_smart_speed == AVA4_DEFAULT_SMARTSPEED_MODE2) {
  1978. device_tdiff = tdiff(&current, &(info->last_fdec[i]));
  1979. if ((device_tdiff >= AVA4_DEFAULT_FDEC_TIME) ||
  1980. (device_tdiff < 0)) {
  1981. copy_time(&info->last_fdec[i], &current);
  1982. if ((opt_avalon4_least_pll_check && (info->pll_sel[i][0] >= opt_avalon4_least_pll_check)) ||
  1983. (opt_avalon4_most_pll_check && (info->pll_sel[i][AVA4_DEFAULT_PLL_MAX - 1] <= opt_avalon4_most_pll_check)))
  1984. avalon4_freq_dec(avalon4, i, info->set_smart_frequency[i], 25);
  1985. }
  1986. device_tdiff = tdiff(&current, &(info->last_finc[i]));
  1987. if ((device_tdiff >= AVA4_DEFAULT_FINC_TIME) ||
  1988. (device_tdiff < 0)) {
  1989. copy_time(&info->last_finc[i], &current);
  1990. if ((opt_avalon4_least_pll_check && (info->pll_sel[i][0] < opt_avalon4_least_pll_check)) ||
  1991. (opt_avalon4_most_pll_check && (info->pll_sel[i][AVA4_DEFAULT_PLL_MAX - 1] > opt_avalon4_most_pll_check)))
  1992. avalon4_freq_inc(avalon4, i, info->set_smart_frequency[i], 25);
  1993. }
  1994. }
  1995. if (opt_avalon4_smart_speed == AVA4_DEFAULT_SMARTSPEED_MODE3) {
  1996. device_tdiff = tdiff(&current, &(info->last_favg[i]));
  1997. if ((device_tdiff >= AVA4_DEFAULT_FAVG_TIME) ||
  1998. (device_tdiff < 0)) {
  1999. copy_time(&info->last_favg[i], &current);
  2000. tmp = (info->get_frequency[i] / 96);
  2001. tmp = (uint32_t)ceil(tmp / 25.0) * 25 + 25;
  2002. if (tmp < AVA4_DEFAULT_FREQUENCY_MIN)
  2003. tmp = AVA4_DEFAULT_FREQUENCY_MIN;
  2004. if (tmp > AVA4_MM60_FREQUENCY_MAX)
  2005. tmp = AVA4_MM60_FREQUENCY_MAX;
  2006. info->set_smart_frequency[i][0] = info->set_smart_frequency[i][1] = info->set_smart_frequency[i][2] = tmp;
  2007. }
  2008. }
  2009. cg_wlock(&info->update_lock);
  2010. avalon4_set_freq(avalon4, i, 0, 0, info->set_smart_frequency[i]);
  2011. applog(LOG_DEBUG, "%s-%d-%d: update freq (%d-%d-%d) AVA4_FREQ_PLLADJ_MODE",
  2012. avalon4->drv->name, avalon4->device_id, i,
  2013. info->set_smart_frequency[i][0],
  2014. info->set_smart_frequency[i][1],
  2015. info->set_smart_frequency[i][2]);
  2016. cg_wunlock(&info->update_lock);
  2017. break;
  2018. default:
  2019. break;
  2020. }
  2021. }
  2022. }
  2023. }
  2024. /* Step 5: Calculate mm count and hash */
  2025. h = 0;
  2026. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2027. if (info->enable[i]) {
  2028. count++;
  2029. if (info->local_work[i] > info->hw_work[i]) {
  2030. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  2031. h += avalon4->diff1 - info->newnonce;
  2032. info->newnonce = avalon4->diff1;
  2033. } else {
  2034. h += (info->local_work[i] - info->hw_work[i]);
  2035. info->local_work[i] = 0;
  2036. info->hw_work[i] = 0;
  2037. }
  2038. }
  2039. }
  2040. }
  2041. info->mm_count = count;
  2042. if (h && !info->firsthash.tv_sec) {
  2043. cgtime(&info->firsthash);
  2044. copy_time(&(avalon4->dev_start_tv), &(info->firsthash));
  2045. }
  2046. return h * 0xffffffffull;
  2047. }
  2048. #define STATBUFLEN (6 * 1024)
  2049. static struct api_data *avalon4_api_stats(struct cgpu_info *cgpu)
  2050. {
  2051. struct api_data *root = NULL;
  2052. struct avalon4_info *info = cgpu->device_data;
  2053. int i, j, k;
  2054. uint32_t a, b, lw5_i[AVA4_DEFAULT_MINER_MAX], hw5_i[AVA4_DEFAULT_MINER_MAX];
  2055. double hwp, diff;
  2056. char buf[256];
  2057. char statbuf[AVA4_DEFAULT_MODULARS][STATBUFLEN];
  2058. struct timeval current;
  2059. bool has_a6 = false;
  2060. memset(statbuf, 0, AVA4_DEFAULT_MODULARS * STATBUFLEN);
  2061. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2062. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2063. continue;
  2064. if (info->mod_type[i] == AVA4_TYPE_MM60)
  2065. has_a6 = true;
  2066. sprintf(buf, "Ver[%s]", info->mm_version[i]);
  2067. strcat(statbuf[i], buf);
  2068. }
  2069. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2070. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2071. continue;
  2072. sprintf(buf, " DNA[%02x%02x%02x%02x%02x%02x%02x%02x]",
  2073. info->mm_dna[i][0],
  2074. info->mm_dna[i][1],
  2075. info->mm_dna[i][2],
  2076. info->mm_dna[i][3],
  2077. info->mm_dna[i][4],
  2078. info->mm_dna[i][5],
  2079. info->mm_dna[i][6],
  2080. info->mm_dna[i][7]);
  2081. strcat(statbuf[i], buf);
  2082. }
  2083. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2084. struct timeval now;
  2085. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2086. continue;
  2087. cgtime(&now);
  2088. sprintf(buf, " Elapsed[%.0f]", tdiff(&now, &(info->elapsed[i])));
  2089. strcat(statbuf[i], buf);
  2090. }
  2091. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2092. uint8_t show = 0;
  2093. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2094. continue;
  2095. if (info->mod_type[i] == AVA4_TYPE_MM60)
  2096. show = 1;
  2097. if (info->mod_type[i] == AVA4_TYPE_MM50)
  2098. show = 1;
  2099. if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i))
  2100. show = 1;
  2101. if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) {
  2102. if (!mm_cmp_d17f4a(info, i))
  2103. show = 1;
  2104. }
  2105. strcat(statbuf[i], " MW[");
  2106. for (j = 0; j < info->miner_count[i]; j++) {
  2107. if (show)
  2108. sprintf(buf, "%"PRIu64" ", info->local_works_i[i][j]);
  2109. else
  2110. sprintf(buf, "%d ", info->matching_work[i][j]);
  2111. strcat(statbuf[i], buf);
  2112. }
  2113. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2114. }
  2115. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2116. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2117. continue;
  2118. sprintf(buf, " LW[%"PRIu64"]", info->local_works[i]);
  2119. strcat(statbuf[i], buf);
  2120. }
  2121. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2122. uint8_t show = 0;
  2123. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2124. continue;
  2125. if (info->mod_type[i] == AVA4_TYPE_MM60)
  2126. show = 1;
  2127. if (info->mod_type[i] == AVA4_TYPE_MM50)
  2128. show = 1;
  2129. if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i))
  2130. show = 1;
  2131. if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) {
  2132. if (!mm_cmp_d17f4a(info, i))
  2133. show = 1;
  2134. }
  2135. if (show) {
  2136. strcat(statbuf[i], " MH[");
  2137. for (j = 0; j < info->miner_count[i]; j++) {
  2138. sprintf(buf, "%"PRIu64" ", info->hw_works_i[i][j]);
  2139. strcat(statbuf[i], buf);
  2140. }
  2141. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2142. }
  2143. }
  2144. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2145. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2146. continue;
  2147. sprintf(buf, " HW[%"PRIu64"]", info->hw_works[i]);
  2148. strcat(statbuf[i], buf);
  2149. }
  2150. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2151. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2152. continue;
  2153. a = info->hw_works[i];
  2154. b = info->local_works[i];
  2155. hwp = b ? ((double)a / (double)b) * 100: 0;
  2156. sprintf(buf, " DH[%.3f%%]", hwp);
  2157. strcat(statbuf[i], buf);
  2158. }
  2159. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2160. uint8_t show = 0;
  2161. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2162. continue;
  2163. a = 0;
  2164. b = 0;
  2165. memset(lw5_i, 0, info->miner_count[i] * sizeof(uint32_t));
  2166. memset(hw5_i, 0, info->miner_count[i] * sizeof(uint32_t));
  2167. for (j = 0; j < AVA4_DEFAULT_ADJ_TIMES; j++) {
  2168. a += info->lw5[i][j];
  2169. b += info->hw5[i][j];
  2170. for (k = 0; k < info->miner_count[i]; k++) {
  2171. lw5_i[k] += info->lw5_i[i][k][j];
  2172. hw5_i[k] += info->hw5_i[i][k][j];
  2173. }
  2174. }
  2175. cgtime(&current);
  2176. diff = tdiff(&current, &(info->last_5s)) + 25.0;
  2177. hwp = a ? (double)b / (double)a * 100 : 0;
  2178. if (info->mod_type[i] == AVA4_TYPE_MM50)
  2179. show = 1;
  2180. if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i))
  2181. show = 1;
  2182. if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) {
  2183. if (!mm_cmp_d17f4a(info, i))
  2184. show = 1;
  2185. }
  2186. sprintf(buf, " GHS5m[%.2f] DH5m[%.3f%%]", ((double)a - (double)b) * 4.295 / diff, hwp);
  2187. strcat(statbuf[i], buf);
  2188. if (opt_debug && show) {
  2189. strcat(statbuf[i], " MDH5m[");
  2190. for (k = 0; k < info->miner_count[i]; k++) {
  2191. hwp = lw5_i[k] ? (double)hw5_i[k] / (double)lw5_i[k] * 100 : 0;
  2192. sprintf(buf, "%.3f%% ", hwp);
  2193. strcat(statbuf[i], buf);
  2194. }
  2195. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2196. }
  2197. }
  2198. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2199. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2200. continue;
  2201. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  2202. sprintf(buf, " Temp[%d] Temp0[%d] Temp1[%d]",
  2203. info->temp[i],
  2204. (int)convert_temp(info->adc[i][0]),
  2205. (int)convert_temp(info->adc[i][1]));
  2206. } else
  2207. sprintf(buf, " Temp[%d]", info->temp[i]);
  2208. strcat(statbuf[i], buf);
  2209. }
  2210. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2211. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2212. continue;
  2213. sprintf(buf, " Fan[%d]", info->fan[i]);
  2214. strcat(statbuf[i], buf);
  2215. }
  2216. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2217. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2218. continue;
  2219. if (info->mod_type[i] == AVA4_TYPE_MM60)
  2220. sprintf(buf, " Vol[%.1f]", convert_voltage(info->adc[i][4], 1 / 11.0));
  2221. else
  2222. sprintf(buf, " Vol[%.4f]", (float)info->get_voltage[i] / 10000);
  2223. strcat(statbuf[i], buf);
  2224. }
  2225. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2226. uint8_t show = 0;
  2227. int32_t vref = 0;
  2228. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2229. continue;
  2230. if (info->mod_type[i] == AVA4_TYPE_MM50)
  2231. show = 1;
  2232. if ((info->mod_type[i] == AVA4_TYPE_MM41) && mm_cmp_1501(info, i))
  2233. show = 1;
  2234. if ((info->mod_type[i] == AVA4_TYPE_MM40) && mm_cmp_1501(info, i)) {
  2235. if (!mm_cmp_d17f4a(info, i))
  2236. show = 1;
  2237. }
  2238. if (opt_debug && show) {
  2239. strcat(statbuf[i], " MVol[");
  2240. for (j = 0; j < info->miner_count[i]; j++) {
  2241. sprintf(buf, "%.4f ", (float)info->set_voltage_i[i][j] / 10000);
  2242. vref += ((info->set_voltage_i[i][j] - opt_avalon4_voltage_min) / 125);
  2243. strcat(statbuf[i], buf);
  2244. }
  2245. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2246. strcat(statbuf[i], " VREF[");
  2247. sprintf(buf, "%d ", vref);
  2248. strcat(statbuf[i], buf);
  2249. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2250. }
  2251. }
  2252. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2253. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2254. continue;
  2255. if (info->mod_type[i] == AVA4_TYPE_MM60)
  2256. sprintf(buf, " GHSmm[%.2f] Freq[%.2f]", (float)info->get_frequency[i] / 1000 * info->total_asics[i], (float)info->get_frequency[i] / 1000);
  2257. else
  2258. sprintf(buf, " Freq[%.2f]", (float)info->get_frequency[i] / 1000);
  2259. strcat(statbuf[i], buf);
  2260. }
  2261. if (opt_debug) {
  2262. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2263. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2264. continue;
  2265. if (info->mod_type[i] == AVA4_TYPE_MM50) {
  2266. for (j = 0; j < info->miner_count[i]; j++) {
  2267. sprintf(buf, " MFreq%d[", j);
  2268. strcat(statbuf[i], buf);
  2269. for (k = 0; k < info->asic_count[i]; k++) {
  2270. sprintf(buf, "%d %d %d ",
  2271. info->set_frequency_i[i][j][k][0],
  2272. info->set_frequency_i[i][j][k][1],
  2273. info->set_frequency_i[i][j][k][2]);
  2274. strcat(statbuf[i], buf);
  2275. }
  2276. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2277. }
  2278. }
  2279. }
  2280. }
  2281. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2282. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2283. continue;
  2284. sprintf(buf, " PG[%d]", info->power_good[i]);
  2285. strcat(statbuf[i], buf);
  2286. }
  2287. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2288. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2289. continue;
  2290. sprintf(buf, " Led[%d]", info->led_red[i]);
  2291. strcat(statbuf[i], buf);
  2292. }
  2293. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2294. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2295. continue;
  2296. if (info->mod_type[i] == AVA4_TYPE_MM50 || info->mod_type[i] == AVA4_TYPE_MM60) {
  2297. for (j = 0; j < info->miner_count[i]; j++) {
  2298. sprintf(buf, " MW%d[", j);
  2299. strcat(statbuf[i], buf);
  2300. for (k = 0; k < info->asic_count[i]; k++) {
  2301. sprintf(buf, "%d ", info->chipmatching_work[i][j][k]);
  2302. strcat(statbuf[i], buf);
  2303. }
  2304. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2305. }
  2306. }
  2307. }
  2308. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2309. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2310. continue;
  2311. if (info->mod_type[i] == AVA4_TYPE_MM50) {
  2312. for (j = 0; j < info->miner_count[i]; j++) {
  2313. sprintf(buf, " MA%d[", j);
  2314. strcat(statbuf[i], buf);
  2315. for (k = 0; k < info->asic_count[i]; k++) {
  2316. sprintf(buf, "%d ", info->ma_sum[i][j][k]);
  2317. strcat(statbuf[i], buf);
  2318. }
  2319. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2320. }
  2321. }
  2322. }
  2323. if (opt_debug) {
  2324. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2325. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2326. continue;
  2327. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  2328. sprintf(buf, " PLL[");
  2329. strcat(statbuf[i], buf);
  2330. for (j = 0; j < AVA4_DEFAULT_PLL_MAX; j++) {
  2331. sprintf(buf, "%d ", info->pll_sel[i][j]);
  2332. strcat(statbuf[i], buf);
  2333. }
  2334. statbuf[i][strlen(statbuf[i]) - 1] = ']';
  2335. }
  2336. }
  2337. }
  2338. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2339. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2340. continue;
  2341. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  2342. sprintf(buf, " TA[%d]", info->total_asics[i]);
  2343. strcat(statbuf[i], buf);
  2344. }
  2345. }
  2346. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2347. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2348. continue;
  2349. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  2350. sprintf(buf, " EC[%d]", info->error_code[i]);
  2351. strcat(statbuf[i], buf);
  2352. }
  2353. }
  2354. if (opt_debug) {
  2355. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2356. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2357. continue;
  2358. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  2359. sprintf(buf, " SF[%d %d %d]",
  2360. info->set_smart_frequency[i][0],
  2361. info->set_smart_frequency[i][1],
  2362. info->set_smart_frequency[i][2]);
  2363. strcat(statbuf[i], buf);
  2364. }
  2365. }
  2366. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2367. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2368. continue;
  2369. if (info->mod_type[i] == AVA4_TYPE_MM60) {
  2370. sprintf(buf, " FM[%d]", info->freq_mode[i]);
  2371. strcat(statbuf[i], buf);
  2372. }
  2373. }
  2374. }
  2375. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2376. if (info->mod_type[i] == AVA4_TYPE_NULL)
  2377. continue;
  2378. sprintf(buf, "MM ID%d", i);
  2379. root = api_add_string(root, buf, statbuf[i], true);
  2380. }
  2381. root = api_add_int(root, "MM Count", &(info->mm_count), true);
  2382. if (!has_a6)
  2383. root = api_add_bool(root, "Automatic Voltage", &opt_avalon4_autov, true);
  2384. root = api_add_int(root, "Smart Speed", &opt_avalon4_smart_speed, true);
  2385. root = api_add_bool(root, "Nonce check", &opt_avalon4_noncecheck, true);
  2386. if (info->connecter == AVA4_CONNECTER_IIC)
  2387. root = api_add_string(root, "Connecter", "IIC", true);
  2388. if (info->connecter == AVA4_CONNECTER_AUC) {
  2389. root = api_add_string(root, "Connecter", "AUC", true);
  2390. root = api_add_string(root, "AUC VER", info->auc_version, false);
  2391. root = api_add_int(root, "AUC I2C Speed", &(info->auc_speed), true);
  2392. root = api_add_int(root, "AUC I2C XDelay", &(info->auc_xdelay), true);
  2393. root = api_add_int(root, "AUC ADC", &(info->auc_temp), true);
  2394. }
  2395. return root;
  2396. }
  2397. /* format: freq[-addr[-miner[-chip]]] add4[0, 63], miner[1, miner_count], chip[1, asic_count] */
  2398. char *set_avalon4_device_freq(struct cgpu_info *avalon4, char *arg)
  2399. {
  2400. struct avalon4_info *info = avalon4->device_data;
  2401. char *colon1, *colon2, *param = arg;
  2402. unsigned int val[3], addr = 0, i;
  2403. uint32_t miner_id = 0, chip_id = 0;
  2404. if (!(*arg))
  2405. return NULL;
  2406. colon1 = strchr(arg, ':');
  2407. if (colon1) {
  2408. *(colon1++) = '\0';
  2409. param = colon1;
  2410. }
  2411. if (*arg) {
  2412. val[0] = atoi(arg);
  2413. if (val[0] < AVA4_DEFAULT_FREQUENCY_MIN || val[0] > AVA4_DEFAULT_FREQUENCY_MAX)
  2414. return "Invalid value1 passed to set_avalon4_device_freq";
  2415. }
  2416. if (colon1 && *colon1) {
  2417. colon2 = strchr(colon1, ':');
  2418. if (colon2) {
  2419. *(colon2++) = '\0';
  2420. param = colon2;
  2421. }
  2422. if (*colon1) {
  2423. val[1] = atoi(colon1);
  2424. if (val[1] < AVA4_DEFAULT_FREQUENCY_MIN || val[1] > AVA4_DEFAULT_FREQUENCY_MAX)
  2425. return "Invalid value2 passed to set_avalon4_device_freq";
  2426. }
  2427. if (colon2 && *colon2) {
  2428. val[2] = atoi(colon2);
  2429. if (val[2] < AVA4_DEFAULT_FREQUENCY_MIN || val[2] > AVA4_DEFAULT_FREQUENCY_MAX)
  2430. return "Invalid value3 passed to set_avalon4_device_freq";
  2431. }
  2432. }
  2433. if (!val[0])
  2434. val[2] = val[1] = val[0] = AVA4_DEFAULT_FREQUENCY;
  2435. if (!val[1])
  2436. val[2] = val[1] = val[0];
  2437. if (!val[2])
  2438. val[2] = val[1];
  2439. colon1 = strchr(param, '-');
  2440. if (colon1) {
  2441. sscanf(colon1, "-%d-%d-%d", &addr, &miner_id, &chip_id);
  2442. if (miner_id >= AVA4_DEFAULT_MODULARS) {
  2443. applog(LOG_ERR, "invalid dev index: %d, valid range 0-%d", addr, (AVA4_DEFAULT_MODULARS - 1));
  2444. return "Invalid dev index to set_avalon4_device_freq";
  2445. }
  2446. if (!info->enable[addr]) {
  2447. applog(LOG_ERR, "Disabled dev:%d", addr);
  2448. return "Disabled dev to set_avalon4_device_freq";
  2449. }
  2450. if (miner_id > info->miner_count[addr]) {
  2451. applog(LOG_ERR, "invalid miner index: %d, valid range 0-%d", chip_id, info->miner_count[addr]);
  2452. return "Invalid miner index to set_avalon4_device_freq";
  2453. }
  2454. if (chip_id > info->asic_count[addr]) {
  2455. applog(LOG_ERR, "invalid asic index: %d, valid range 0-%d", chip_id, info->asic_count[addr]);
  2456. return "Invalid asic index to set_avalon4_device_freq";
  2457. }
  2458. }
  2459. if (!miner_id || !chip_id) {
  2460. memcpy(opt_avalon4_freq, val, sizeof(int) * 3);
  2461. if (!addr) {
  2462. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2463. if (!info->enable[i])
  2464. continue;
  2465. avalon4_set_freq(avalon4, i, 0, 0, val);
  2466. }
  2467. } else
  2468. avalon4_set_freq(avalon4, addr, 0, 0, val);
  2469. } else
  2470. avalon4_set_freq(avalon4, addr, miner_id, chip_id, val);
  2471. return NULL;
  2472. }
  2473. static char *avalon4_set_device(struct cgpu_info *avalon4, char *option, char *setting, char *replybuf, size_t siz)
  2474. {
  2475. int val, i, j;
  2476. struct avalon4_info *info = avalon4->device_data;
  2477. if (strcasecmp(option, "help") == 0) {
  2478. snprintf(replybuf, siz, "led|fan|voltage|frequency|pdelay|freezesafe");
  2479. return replybuf;
  2480. }
  2481. if (strcasecmp(option, "freezesafe") == 0) {
  2482. if (!setting || !*setting) {
  2483. snprintf(replybuf, siz, "missing freezesafe mode setting");
  2484. return replybuf;
  2485. }
  2486. val = atoi(setting);
  2487. opt_avalon4_freezesafe = val ? 1 : 0;
  2488. applog(LOG_NOTICE, "%s-%d: update freezesafe mode: %d",
  2489. avalon4->drv->name, avalon4->device_id, opt_avalon4_freezesafe);
  2490. return NULL;
  2491. }
  2492. if (strcasecmp(option, "pdelay") == 0) {
  2493. if (!setting || !*setting) {
  2494. snprintf(replybuf, siz, "missing polling delay setting");
  2495. return replybuf;
  2496. }
  2497. val = atoi(setting);
  2498. if (val < 1 || val > 65535) {
  2499. snprintf(replybuf, siz, "invalid polling delay: %d, valid range 1-65535", val);
  2500. return replybuf;
  2501. }
  2502. opt_avalon4_polling_delay = val;
  2503. applog(LOG_NOTICE, "%s-%d: Update polling delay to: %d",
  2504. avalon4->drv->name, avalon4->device_id, val);
  2505. return NULL;
  2506. }
  2507. if (strcasecmp(option, "fan") == 0) {
  2508. if (!setting || !*setting) {
  2509. snprintf(replybuf, siz, "missing fan value");
  2510. return replybuf;
  2511. }
  2512. if (set_avalon4_fan(setting)) {
  2513. snprintf(replybuf, siz, "invalid fan value, valid range 0-100");
  2514. return replybuf;
  2515. }
  2516. applog(LOG_NOTICE, "%s-%d: Update fan to %d-%d",
  2517. avalon4->drv->name, avalon4->device_id,
  2518. opt_avalon4_fan_min, opt_avalon4_fan_max);
  2519. return NULL;
  2520. }
  2521. if (strcasecmp(option, "frequency") == 0) {
  2522. if (!setting || !*setting) {
  2523. snprintf(replybuf, siz, "missing frequency value");
  2524. return replybuf;
  2525. }
  2526. if (set_avalon4_device_freq(avalon4, setting)) {
  2527. snprintf(replybuf, siz, "invalid frequency value, valid range %d-%d",
  2528. AVA4_DEFAULT_FREQUENCY_MIN, AVA4_DEFAULT_FREQUENCY_MAX);
  2529. return replybuf;
  2530. }
  2531. applog(LOG_NOTICE, "%s-%d: Update frequency to %d",
  2532. avalon4->drv->name, avalon4->device_id,
  2533. (opt_avalon4_freq[0] * 4 + opt_avalon4_freq[1] * 4 + opt_avalon4_freq[2]) / 9);
  2534. return NULL;
  2535. }
  2536. if (strcasecmp(option, "led") == 0) {
  2537. int val_led = -1;
  2538. if (!setting || !*setting) {
  2539. snprintf(replybuf, siz, "missing module_id setting");
  2540. return replybuf;
  2541. }
  2542. sscanf(setting, "%d-%d", &val, &val_led);
  2543. if (val < 1 || val >= AVA4_DEFAULT_MODULARS) {
  2544. snprintf(replybuf, siz, "invalid module_id: %d, valid range 1-%d", val, AVA4_DEFAULT_MODULARS);
  2545. return replybuf;
  2546. }
  2547. if (!info->enable[val]) {
  2548. snprintf(replybuf, siz, "the current module was disabled %d", val);
  2549. return replybuf;
  2550. }
  2551. if (val_led == -1)
  2552. info->led_red[val] = !info->led_red[val];
  2553. else {
  2554. if (val_led < 0 || val_led > 1) {
  2555. snprintf(replybuf, siz, "invalid LED status: %d, valid value 0|1", val_led);
  2556. return replybuf;
  2557. }
  2558. if (val_led != info->led_red[val])
  2559. info->led_red[val] = val_led;
  2560. }
  2561. applog(LOG_NOTICE, "%s-%d: Module:%d, LED: %s",
  2562. avalon4->drv->name, avalon4->device_id,
  2563. val, info->led_red[val] ? "on" : "off");
  2564. return NULL;
  2565. }
  2566. if (strcasecmp(option, "voltage") == 0) {
  2567. int val_mod, val_volt, val_ch = -1, val_offset = -1;
  2568. if (!setting || !*setting) {
  2569. snprintf(replybuf, siz, "missing voltage value");
  2570. return replybuf;
  2571. }
  2572. sscanf(setting, "%d-%d-%d-%d", &val_mod, &val_volt, &val_ch, &val_offset);
  2573. if (val_mod < 0 || val_mod >= AVA4_DEFAULT_MODULARS ||
  2574. val_volt < AVA4_DEFAULT_VOLTAGE_MIN || val_volt > AVA4_DEFAULT_VOLTAGE_MAX) {
  2575. snprintf(replybuf, siz, "invalid module_id or voltage value, valid module_id range %d-%d, valid voltage range %d-%d",
  2576. 0, AVA4_DEFAULT_MODULARS,
  2577. AVA4_DEFAULT_VOLTAGE_MIN, AVA4_DEFAULT_VOLTAGE_MAX);
  2578. return replybuf;
  2579. }
  2580. if ((val_ch != -1) && (val_ch < -1 || val_ch >= AVA4_DEFAULT_MINER_MAX)) {
  2581. snprintf(replybuf, siz, "invalid miner_id, valid miner_id range %d-%d",
  2582. 0, AVA4_DEFAULT_MINER_MAX - 1);
  2583. return replybuf;
  2584. }
  2585. if ((val_offset != -1) && ((val_volt + val_offset) < AVA4_DEFAULT_VOLTAGE_MIN ||
  2586. ((val_volt + val_offset) > AVA4_DEFAULT_VOLTAGE_MAX))) {
  2587. snprintf(replybuf, siz, "invalid val_offset, valid val_offset range %d-%d",
  2588. AVA4_DEFAULT_VOLTAGE_MIN - val_volt,
  2589. AVA4_DEFAULT_VOLTAGE_MAX - val_volt);
  2590. return replybuf;
  2591. }
  2592. if (!info->enable[val_mod]) {
  2593. snprintf(replybuf, siz, "the current module was disabled %d", val_mod);
  2594. return replybuf;
  2595. }
  2596. info->set_voltage[val_mod] = val_volt;
  2597. if (val_ch == -1) {
  2598. for (i = 0; i < info->miner_count[val_mod]; i++) {
  2599. info->set_voltage_i[val_mod][i] = val_volt;
  2600. info->set_voltage_offset[val_mod][i] = 0;
  2601. }
  2602. } else {
  2603. info->set_voltage_i[val_mod][val_ch] = val_volt;
  2604. if (val_offset == -1)
  2605. info->set_voltage_offset[val_mod][val_ch] = 0;
  2606. else
  2607. info->set_voltage_offset[val_mod][val_ch] = val_offset;
  2608. }
  2609. if (val_mod == AVA4_MODULE_BROADCAST) {
  2610. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2611. info->set_voltage[i] = val_volt;
  2612. if (val_ch == -1) {
  2613. for (j = 0; j < info->miner_count[i]; j++) {
  2614. info->set_voltage_i[i][j] = val_volt;
  2615. info->set_voltage_offset[i][j] = 0;
  2616. }
  2617. } else {
  2618. info->set_voltage_i[i][val_ch] = val_volt;
  2619. if (val_offset == -1)
  2620. info->set_voltage_offset[i][val_ch] = 0;
  2621. else
  2622. info->set_voltage_offset[i][val_ch] = val_offset;
  2623. }
  2624. }
  2625. }
  2626. applog(LOG_NOTICE, "%s-%d: Update module[%d] voltage to %d, val_ch:%d, val_offset:%d",
  2627. avalon4->drv->name, avalon4->device_id, val_mod, val_volt, val_ch, val_offset);
  2628. return NULL;
  2629. }
  2630. snprintf(replybuf, siz, "Unknown option: %s", option);
  2631. return replybuf;
  2632. }
  2633. static void avalon4_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon4)
  2634. {
  2635. struct avalon4_info *info = avalon4->device_data;
  2636. int temp = get_current_temp_max(info);
  2637. int voltsmin = AVA4_DEFAULT_VOLTAGE_MAX, voltsmax = AVA4_DEFAULT_VOLTAGE_MIN;
  2638. int fanmin = AVA4_DEFAULT_FAN_MAX, fanmax = AVA4_DEFAULT_FAN_MIN;
  2639. int i, j, tempadcmin = AVA4_ADC_MAX, vcc12adcmin = AVA4_ADC_MAX;
  2640. int has_a6 = 0;
  2641. uint32_t frequency = 0;
  2642. float ghs_sum = 0.0;
  2643. for (i = 1; i < AVA4_DEFAULT_MODULARS; i++) {
  2644. if (!info->enable[i])
  2645. continue;
  2646. if (info->mod_type[i] == AVA4_TYPE_MM60)
  2647. has_a6 = 1;
  2648. if (fanmax <= info->fan_pct[i])
  2649. fanmax = info->fan_pct[i];
  2650. if (fanmin >= info->fan_pct[i])
  2651. fanmin = info->fan_pct[i];
  2652. if (voltsmax <= info->get_voltage[i])
  2653. voltsmax = info->get_voltage[i];
  2654. if (voltsmin >= info->get_voltage[i])
  2655. voltsmin = info->get_voltage[i];
  2656. for (j = 0; j < AVA4_DEFAULT_ADC_MAX - 2; j++) {
  2657. if (info->adc[i][j] < tempadcmin)
  2658. tempadcmin = info->adc[i][j];
  2659. }
  2660. if (info->adc[i][4] < vcc12adcmin)
  2661. vcc12adcmin = info->adc[i][4];
  2662. frequency += info->get_frequency[i];
  2663. ghs_sum += ((float)info->get_frequency[i] / 1000 * info->total_asics[i]);
  2664. }
  2665. if (has_a6) {
  2666. if (info->mm_count)
  2667. frequency /= info->mm_count;
  2668. tailsprintf(buf, bufsiz, "%4dMhz %.2fGHS %2dC-%2dC %3d%% %.1fV", frequency / 96,
  2669. ghs_sum, temp, (int)convert_temp(tempadcmin), fanmin,
  2670. (vcc12adcmin == AVA4_ADC_MAX) ? 0 : convert_voltage(vcc12adcmin, 1 / 11.0));
  2671. } else {
  2672. frequency = (opt_avalon4_freq[0] * 4 + opt_avalon4_freq[1] * 4 + opt_avalon4_freq[2]) / 9;
  2673. tailsprintf(buf, bufsiz, "%4dMhz %2dC %3d%% %.3fV", frequency,
  2674. temp, fanmin, (float)voltsmax / 10000);
  2675. }
  2676. }
  2677. struct device_drv avalon4_drv = {
  2678. .drv_id = DRIVER_avalon4,
  2679. .dname = "avalon4",
  2680. .name = "AV4",
  2681. .set_device = avalon4_set_device,
  2682. .get_api_stats = avalon4_api_stats,
  2683. .get_statline_before = avalon4_statline_before,
  2684. .drv_detect = avalon4_detect,
  2685. .thread_prepare = avalon4_prepare,
  2686. .hash_work = hash_driver_work,
  2687. .flush_work = avalon4_update,
  2688. .update_work = avalon4_update,
  2689. .scanwork = avalon4_scanhash,
  2690. .max_diff = AVA4_DRV_DIFFMAX,
  2691. };