driver-avalon-miner.c 35 KB

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  1. /*
  2. * Copyright 2013-2014 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2014 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2014-2015 Mikeqin <Fengling.Qin@gmail.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 3 of the License, or (at your option)
  9. * any later version. See COPYING for more details.
  10. */
  11. #include <math.h>
  12. #include "config.h"
  13. #include "miner.h"
  14. #include "driver-avalon-miner.h"
  15. #include "crc.h"
  16. #include "sha2.h"
  17. #include "hexdump.c"
  18. #define UNPACK32(x, str) \
  19. { \
  20. *((str) + 3) = (uint8_t) ((x) ); \
  21. *((str) + 2) = (uint8_t) ((x) >> 8); \
  22. *((str) + 1) = (uint8_t) ((x) >> 16); \
  23. *((str) + 0) = (uint8_t) ((x) >> 24); \
  24. }
  25. #define PACK32(str, x) \
  26. { \
  27. *(x) = ((uint32_t) *((str) + 3) ) \
  28. | ((uint32_t) *((str) + 2) << 8) \
  29. | ((uint32_t) *((str) + 1) << 16) \
  30. | ((uint32_t) *((str) + 0) << 24); \
  31. }
  32. #define V_REF 3.3
  33. #define R_REF 10000
  34. #define R0 10000
  35. #define BCOEFFICIENT 3450
  36. #define T0 25
  37. static uint32_t opt_avalonm_freq[3] = {AVAM_DEFAULT_FREQUENCY, AVAM_DEFAULT_FREQUENCY, AVAM_DEFAULT_FREQUENCY};
  38. uint8_t opt_avalonm_ntime_offset = 0;
  39. int opt_avalonm_voltage = AVAM_DEFAULT_VOLTAGE;
  40. uint32_t opt_avalonm_spispeed = AVAM_DEFAULT_SPISPEED;
  41. bool opt_avalonm_autof;
  42. static uint32_t g_freq_array[][2] = {
  43. {100, 0x1e678447},
  44. {113, 0x22688447},
  45. {125, 0x1c470447},
  46. {138, 0x2a6a8447},
  47. {150, 0x22488447},
  48. {163, 0x326c8447},
  49. {175, 0x1a268447},
  50. {188, 0x1c270447},
  51. {200, 0x1e278447},
  52. {213, 0x20280447},
  53. {225, 0x22288447},
  54. {238, 0x24290447},
  55. {250, 0x26298447},
  56. {263, 0x282a0447},
  57. {275, 0x2a2a8447},
  58. {288, 0x2c2b0447},
  59. {300, 0x2e2b8447},
  60. {313, 0x302c0447},
  61. {325, 0x322c8447},
  62. {338, 0x342d0447},
  63. {350, 0x1a068447},
  64. {363, 0x382e0447},
  65. {375, 0x1c070447},
  66. {388, 0x3c2f0447},
  67. {400, 0x1e078447}
  68. };
  69. static uint16_t encode_voltage(uint32_t v)
  70. {
  71. if (v == 0)
  72. return 0xff;
  73. return (((0x59 - (v - 5000) / 125) & 0xff) << 1 | 1);
  74. }
  75. static uint32_t decode_voltage(uint8_t v)
  76. {
  77. if (v == 0xff)
  78. return 0;
  79. return (0x59 - (v >> 1)) * 125 + 5000;
  80. }
  81. static uint32_t decode_cpm(uint32_t cpm)
  82. {
  83. int i;
  84. for (i = 0; i < sizeof(g_freq_array) / sizeof(g_freq_array[0]); i++) {
  85. if (g_freq_array[i][1] == cpm)
  86. return g_freq_array[i][0];
  87. }
  88. return 0;
  89. }
  90. static int avalonm_init_pkg(struct avalonm_pkg *pkg, uint8_t type, uint8_t idx, uint8_t cnt)
  91. {
  92. unsigned short crc;
  93. pkg->head[0] = AVAM_H1;
  94. pkg->head[1] = AVAM_H2;
  95. pkg->type = type;
  96. pkg->opt = 0;
  97. pkg->idx = idx;
  98. pkg->cnt = cnt;
  99. crc = crc16(pkg->data, AVAM_P_DATA_LEN);
  100. pkg->crc[0] = (crc & 0xff00) >> 8;
  101. pkg->crc[1] = crc & 0x00ff;
  102. return 0;
  103. }
  104. static float convert_temp(uint32_t adc)
  105. {
  106. float ret, resistance;
  107. if (adc >= 1023)
  108. return -273.15;
  109. resistance = (1023.0 / adc) - 1;
  110. resistance = R_REF / resistance;
  111. ret = resistance / R0;
  112. ret = log(ret);
  113. ret /= BCOEFFICIENT;
  114. ret += 1.0 / (T0 + 273.15);
  115. ret = 1.0 / ret;
  116. ret -= 273.15;
  117. return ret;
  118. }
  119. static float convert_voltage(uint32_t adc, float percent)
  120. {
  121. float voltage;
  122. voltage = adc * V_REF / 1023 / percent;
  123. return voltage;
  124. }
  125. static void process_nonce(struct cgpu_info *avalonm, uint8_t *report)
  126. {
  127. struct avalonm_info *info = avalonm->device_data;
  128. struct work *work;
  129. uint8_t ntime, chip_id;
  130. uint32_t nonce, id;
  131. PACK32(report, &id);
  132. chip_id = report[6];
  133. if (chip_id >= info->asic_cnts) {
  134. applog(LOG_DEBUG, "%s-%d: chip_id >= info->asic_cnts(%d > %d)",
  135. avalonm->drv->name, avalonm->device_id,
  136. chip_id, info->asic_cnts);
  137. return;
  138. }
  139. ntime = report[7];
  140. PACK32(report + 8, &nonce);
  141. nonce -= 0x4000;
  142. info->usbfifo_cnt = report[13];
  143. info->workfifo_cnt = report[14];
  144. info->noncefifo_cnt = report[15];
  145. applog(LOG_DEBUG, "%s-%d: Found! - ID: %08x CID: %02x N:%08x NR:%d",
  146. avalonm->drv->name, avalonm->device_id,
  147. id, chip_id, nonce, ntime);
  148. work = clone_queued_work_byid(avalonm, id);
  149. if (!work)
  150. return;
  151. if(!submit_noffset_nonce(info->thr, work, nonce, ntime)) {
  152. info->hw_work[chip_id]++;
  153. info->hw_work_i[chip_id][info->time_i]++;
  154. }
  155. info->matching_work[chip_id]++;
  156. free_work(work);
  157. info->nonce_cnts++;
  158. }
  159. static int decode_pkg(struct thr_info *thr, struct avalonm_ret *ar)
  160. {
  161. struct cgpu_info *avalonm = thr->cgpu;
  162. struct avalonm_info *info = avalonm->device_data;
  163. uint32_t ret, tmp, i, freq[3];
  164. unsigned int expected_crc;
  165. unsigned int actual_crc;
  166. if (ar->head[0] != AVAM_H1 && ar->head[1] != AVAM_H2) {
  167. applog(LOG_DEBUG, "%s-%d: H1 %02x, H2 %02x",
  168. avalonm->drv->name, avalonm->device_id,
  169. ar->head[0], ar->head[1]);
  170. info->crcerr_cnt++;
  171. return 0;
  172. }
  173. expected_crc = crc16(ar->data, AVAM_P_DATA_LEN);
  174. actual_crc = (ar->crc[1] & 0xff) | ((ar->crc[0] & 0xff) << 8);
  175. if (expected_crc != actual_crc) {
  176. applog(LOG_DEBUG, "%s-%d: %02x: expected crc(%04x), actual_crc(%04x)",
  177. avalonm->drv->name, avalonm->device_id,
  178. ar->type, expected_crc, actual_crc);
  179. return 0;
  180. }
  181. switch(ar->type) {
  182. case AVAM_P_NONCE_M:
  183. ret = ar->type;
  184. applog(LOG_DEBUG, "%s-%d: AVAM_P_NONCE", avalonm->drv->name, avalonm->device_id);
  185. hexdump(ar->data, 32);
  186. process_nonce(avalonm, ar->data);
  187. if (ar->data[22] != 0xff) {
  188. process_nonce(avalonm, ar->data + 16);
  189. }
  190. break;
  191. case AVAM_P_STATUS_M:
  192. ret = ar->type;
  193. applog(LOG_DEBUG, "%s-%d: AVAM_P_STATUS_M", avalonm->drv->name, avalonm->device_id);
  194. hexdump(ar->data, 32);
  195. memcpy(&tmp, ar->data, 4);
  196. if (!strncmp(info->ver, "3U", 2))
  197. info->get_frequency[0][0] = be32toh(tmp);
  198. else
  199. info->spi_speed = be32toh(tmp);
  200. memcpy(&tmp, ar->data + 4, 4);
  201. info->led_status = be32toh(tmp);
  202. memcpy(&tmp, ar->data + 8, 4);
  203. info->fan_pwm = be32toh(tmp);
  204. memcpy(&tmp, ar->data + 12, 4);
  205. if (!strncmp(info->ver, "3U", 2))
  206. info->get_voltage = convert_voltage(be32toh(tmp), 0.5);
  207. else
  208. info->get_voltage = decode_voltage((uint8_t)be32toh(tmp));
  209. memcpy(&tmp, ar->data + 16, 4);
  210. info->adc[0] = be32toh(tmp);
  211. memcpy(&tmp, ar->data + 20, 4);
  212. info->adc[1] = be32toh(tmp);
  213. memcpy(&tmp, ar->data + 24, 4);
  214. info->adc[2] = be32toh(tmp);
  215. memcpy(&tmp, ar->data + 28 , 4);
  216. info->power_good = be32toh(tmp);
  217. /* power off notice */
  218. if (!info->get_voltage) {
  219. usb_buffer_clear(avalonm);
  220. applog(LOG_NOTICE, "%s-%d: AVAM_P_STATUS_M Power off notice", avalonm->drv->name, avalonm->device_id);
  221. info->power_on = 1;
  222. memset(info->set_frequency, 0, sizeof(uint32_t) * info->asic_cnts * 3);
  223. for (i = 1; i <= info->asic_cnts; i++)
  224. FLAG_SET(info->freq_set, i);
  225. }
  226. break;
  227. case AVAM_P_STATUS_FREQ:
  228. applog(LOG_DEBUG, "%s-%d: AVAM_P_STATUS_FREQ", avalonm->drv->name, avalonm->device_id);
  229. memcpy(&tmp, ar->data, 4);
  230. tmp = be32toh(tmp);
  231. freq[0] = decode_cpm(tmp);
  232. memcpy(&tmp, ar->data + 4, 4);
  233. tmp = be32toh(tmp);
  234. freq[1] = decode_cpm(tmp);
  235. memcpy(&tmp, ar->data + 8, 4);
  236. tmp = be32toh(tmp);
  237. freq[2] = decode_cpm(tmp);
  238. if (!ar->opt) {
  239. for (i = 0; i < info->asic_cnts; i++) {
  240. info->get_frequency[i][0] = freq[0];
  241. info->get_frequency[i][1] = freq[1];
  242. info->get_frequency[i][2] = freq[2];
  243. }
  244. }
  245. if (ar->opt) {
  246. info->get_frequency[ar->opt - 1][0] = freq[0];
  247. info->get_frequency[ar->opt - 1][1] = freq[1];
  248. info->get_frequency[ar->opt - 1][2] = freq[2];
  249. }
  250. break;
  251. default:
  252. applog(LOG_DEBUG, "%s-%d: Unknown response (%x)", avalonm->drv->name, avalonm->device_id,
  253. ar->type);
  254. ret = 0;
  255. break;
  256. }
  257. return ret;
  258. }
  259. static int avalonm_send_pkg(struct cgpu_info *avalonm, const struct avalonm_pkg *pkg)
  260. {
  261. int err = -1;
  262. int writecnt;
  263. if (unlikely(avalonm->usbinfo.nodev))
  264. return -1;
  265. err = usb_write(avalonm, (char *)pkg, AVAM_P_COUNT, &writecnt, C_AVAM_WRITE);
  266. if (err || writecnt != AVAM_P_COUNT) {
  267. applog(LOG_DEBUG, "%s-%d: avalonm_send_pkg %d, w(%d-%d)!", avalonm->drv->name, avalonm->device_id, err, AVAM_P_COUNT, writecnt);
  268. return -1;
  269. }
  270. return writecnt;
  271. }
  272. static int avalonm_receive_pkg(struct cgpu_info *avalonm, struct avalonm_ret *ret)
  273. {
  274. int err = -1;
  275. int readcnt;
  276. if (unlikely(avalonm->usbinfo.nodev))
  277. return -1;
  278. err = usb_read(avalonm, (char*)ret, AVAM_P_COUNT, &readcnt, C_AVAM_READ);
  279. if (err || readcnt != AVAM_P_COUNT) {
  280. applog(LOG_DEBUG, "%s-%d: avalonm_receive_pkg %d, w(%d-%d)!", avalonm->drv->name, avalonm->device_id, err, AVAM_P_COUNT, readcnt);
  281. return -1;
  282. }
  283. return readcnt;
  284. }
  285. static int avalonm_xfer_pkg(struct cgpu_info *avalonm, const struct avalonm_pkg *pkg, struct avalonm_ret *ret)
  286. {
  287. if (sizeof(struct avalonm_pkg) != avalonm_send_pkg(avalonm, pkg))
  288. return AVAM_SEND_ERROR;
  289. if (sizeof(struct avalonm_ret) != avalonm_receive_pkg(avalonm, ret))
  290. return AVAM_SEND_ERROR;
  291. return AVAM_SEND_OK;
  292. }
  293. static int avalonm_get_frequency(struct cgpu_info *avalonm, uint8_t asic_index)
  294. {
  295. struct avalonm_info *info = avalonm->device_data;
  296. struct thr_info *thr = info->thr;
  297. struct avalonm_pkg send_pkg;
  298. struct avalonm_ret ar;
  299. int ret = 0;
  300. memset(send_pkg.data, 0, AVAM_P_DATA_LEN);
  301. avalonm_init_pkg(&send_pkg, AVAM_P_GET_FREQ, 1, 1);
  302. send_pkg.opt = asic_index;
  303. ret = avalonm_xfer_pkg(avalonm, &send_pkg, &ar);
  304. if (ret == AVAM_SEND_OK) {
  305. ret = decode_pkg(thr, &ar);
  306. }
  307. return ret;
  308. }
  309. static void avalonm_set_spispeed(struct cgpu_info *avalonm, uint32_t speed)
  310. {
  311. struct avalonm_pkg send_pkg;
  312. int tmp;
  313. memset(send_pkg.data, 0, AVAM_P_DATA_LEN);
  314. tmp = speed | 0x80000000;
  315. tmp = be32toh(tmp);
  316. memcpy(send_pkg.data, &tmp, 4);
  317. avalonm_init_pkg(&send_pkg, AVAM_P_SETM, 1, 1);
  318. avalonm_send_pkg(avalonm, &send_pkg);
  319. }
  320. static struct cgpu_info *avalonm_detect_one(struct libusb_device *dev, struct usb_find_devices *found)
  321. {
  322. struct cgpu_info *avalonm = usb_alloc_cgpu(&avalonm_drv, 1);
  323. struct avalonm_info *info;
  324. struct avalonm_pkg send_pkg;
  325. struct avalonm_ret ar;
  326. int ret, i;
  327. if (!usb_init(avalonm, dev, found)) {
  328. applog(LOG_ERR, "Avalonm failed usb_init");
  329. avalonm = usb_free_cgpu(avalonm);
  330. return NULL;
  331. }
  332. usb_buffer_clear(avalonm);
  333. update_usb_stats(avalonm);
  334. /* Cleanup the usb fifo */
  335. while (avalonm_receive_pkg(avalonm, &ar) != -1);
  336. /* We have an Avalonm connected */
  337. avalonm->threads = 1;
  338. memset(send_pkg.data, 0, AVAM_P_DATA_LEN);
  339. avalonm_init_pkg(&send_pkg, AVAM_P_DETECT, 1, 1);
  340. ret = avalonm_xfer_pkg(avalonm, &send_pkg, &ar);
  341. if ((ret != AVAM_SEND_OK) || (ar.type != AVAM_P_ACKDETECT)) {
  342. applog(LOG_DEBUG, "%s-%d: Failed to detect Avalon miner", avalonm->drv->name, avalonm->device_id);
  343. return NULL;
  344. }
  345. add_cgpu(avalonm);
  346. applog(LOG_DEBUG, "%s-%d: Found at %s", avalonm->drv->name, avalonm->device_id,
  347. avalonm->device_path);
  348. avalonm->device_data = cgcalloc(sizeof(struct avalonm_info), 1);
  349. info = avalonm->device_data;
  350. info->thr = NULL;
  351. memcpy(info->dna, ar.data, AVAM_MM_DNA_LEN);
  352. memcpy(info->ver, ar.data + AVAM_MM_DNA_LEN, AVAM_MM_VER_LEN);
  353. info->ver[AVAM_MM_VER_LEN] = '\0';
  354. memcpy(&info->asic_cnts, ar.data + AVAM_MM_DNA_LEN + AVAM_MM_VER_LEN, 4);
  355. info->asic_cnts = be32toh(info->asic_cnts);
  356. if (opt_avalonm_ntime_offset >= info->asic_cnts)
  357. quit(1, "%s-%d: invalid opt_avalonm_ntime_offset, should 0-%d", avalonm->drv->name, avalonm->device_id, info->asic_cnts - 1);
  358. memset(info->set_frequency, 0, sizeof(uint32_t) * info->asic_cnts * 3);
  359. memset(info->get_frequency, 0, sizeof(uint32_t) * info->asic_cnts * 3);
  360. for (i = 0; i < info->asic_cnts; i++) {
  361. info->opt_freq[i][0] = opt_avalonm_freq[0];
  362. info->opt_freq[i][1] = opt_avalonm_freq[1];
  363. info->opt_freq[i][2] = opt_avalonm_freq[2];
  364. }
  365. info->set_voltage = 0;
  366. info->opt_voltage = opt_avalonm_voltage;
  367. info->nonce_cnts = 0;
  368. info->usbfifo_cnt = 0;
  369. info->workfifo_cnt = 0;
  370. info->noncefifo_cnt = 0;
  371. info->crcerr_cnt = 0;
  372. info->power_good = 0;
  373. info->spi_speed = 0;
  374. info->led_status = 0;
  375. info->fan_pwm = 0;
  376. info->get_voltage = 0;
  377. info->freq_update = 0;
  378. info->freq_set = 0;
  379. FLAG_SET(info->freq_set, AVAM_ASIC_ALL);
  380. memset(info->hw_work, 0, sizeof(int) * info->asic_cnts);
  381. memset(info->matching_work, 0, sizeof(uint64_t) * info->asic_cnts);
  382. info->adc[0] = info->adc[1] = info->adc[2] = 0;
  383. avalonm_set_spispeed(avalonm, opt_avalonm_spispeed);
  384. cgtime(&info->elapsed);
  385. info->lastadj = info->lasttime = info->elapsed;
  386. info->time_i = 0;
  387. memset(info->hw_work_i, 0, sizeof(int) * info->asic_cnts * AVAM_DEFAULT_MOV_TIMES);
  388. return avalonm;
  389. }
  390. static uint32_t avalonm_get_cpm(uint32_t freq)
  391. {
  392. int i;
  393. for (i = 0; i < (sizeof(g_freq_array) / sizeof(g_freq_array[0]) - 1); i++) {
  394. if (freq >= g_freq_array[i][0] && freq < g_freq_array[i+1][0])
  395. return g_freq_array[i][1];
  396. }
  397. /* check if the final freq match */
  398. if (freq == g_freq_array[i][0])
  399. return g_freq_array[i][1];
  400. /* return the lowest freq if not found */
  401. return g_freq_array[0][1];
  402. }
  403. static void avalonm_set_freq(struct cgpu_info *avalonm, uint8_t asic_index, uint32_t freq[])
  404. {
  405. struct avalonm_info *info = avalonm->device_data;
  406. struct avalonm_pkg send_pkg;
  407. uint32_t tmp, i;
  408. uint8_t index, change = 0;
  409. uint32_t max_freq = 0;
  410. if (asic_index == AVAM_ASIC_ALL) {
  411. index = 0;
  412. for (i = 0; i < info->asic_cnts; i++) {
  413. if ((info->set_frequency[i][0] == freq[0]) &&
  414. (info->set_frequency[i][1] == freq[1]) &&
  415. (info->set_frequency[i][2] == freq[2]))
  416. continue;
  417. change = 1;
  418. info->set_frequency[i][0] = freq[0];
  419. info->set_frequency[i][1] = freq[1];
  420. info->set_frequency[i][2] = freq[2];
  421. FLAG_SET(info->freq_update, AVAM_ASIC_ALL);
  422. }
  423. }
  424. if (asic_index != AVAM_ASIC_ALL) {
  425. index = asic_index - 1;
  426. if (!((info->set_frequency[index][0] == freq[0]) &&
  427. (info->set_frequency[index][1] == freq[1]) &&
  428. (info->set_frequency[index][2] == freq[2]))) {
  429. change = 1;
  430. info->set_frequency[index][0] = freq[0];
  431. info->set_frequency[index][1] = freq[1];
  432. info->set_frequency[index][2] = freq[2];
  433. FLAG_SET(info->freq_update, asic_index);
  434. }
  435. }
  436. if (!change)
  437. return;
  438. for (i = 0; i < info->asic_cnts; i++) {
  439. if (max_freq < info->set_frequency[i][0])
  440. max_freq = info->set_frequency[i][0];
  441. if (max_freq < info->set_frequency[i][1])
  442. max_freq = info->set_frequency[i][1];
  443. if (max_freq < info->set_frequency[i][2])
  444. max_freq = info->set_frequency[i][2];
  445. }
  446. info->delay_ms = CAL_DELAY(max_freq);
  447. memset(send_pkg.data, 0, AVAM_P_DATA_LEN);
  448. tmp = avalonm_get_cpm(freq[0]);
  449. tmp = be32toh(tmp);
  450. memcpy(send_pkg.data, &tmp, 4);
  451. tmp = avalonm_get_cpm(freq[1]);
  452. tmp = be32toh(tmp);
  453. memcpy(send_pkg.data + 4, &tmp, 4);
  454. tmp = avalonm_get_cpm(freq[2]);
  455. tmp = be32toh(tmp);
  456. memcpy(send_pkg.data + 8, &tmp, 4);
  457. avalonm_init_pkg(&send_pkg, AVAM_P_SET_FREQ, 1, 1);
  458. send_pkg.opt = asic_index;
  459. avalonm_send_pkg(avalonm, &send_pkg);
  460. applog(LOG_NOTICE, "%s-%d: Avalonm set asic_index %d freq %d,%d,%d",
  461. avalonm->drv->name, avalonm->device_id,
  462. asic_index,
  463. freq[0],
  464. freq[1],
  465. freq[2]);
  466. }
  467. static void avalonm_set_voltage(struct cgpu_info *avalonm)
  468. {
  469. struct avalonm_info *info = avalonm->device_data;
  470. struct avalonm_pkg send_pkg;
  471. uint16_t tmp;
  472. if (!info->power_on && (info->set_voltage == info->opt_voltage))
  473. return;
  474. info->set_voltage = info->opt_voltage;
  475. memset(send_pkg.data, 0, AVAM_P_DATA_LEN);
  476. /* Use shifter to set voltage */
  477. tmp = info->set_voltage;
  478. tmp = encode_voltage(tmp);
  479. tmp = htobe16(tmp);
  480. memcpy(send_pkg.data, &tmp, 2);
  481. /* Package the data */
  482. avalonm_init_pkg(&send_pkg, AVAM_P_SET_VOLT, 1, 1);
  483. avalonm_send_pkg(avalonm, &send_pkg);
  484. applog(LOG_NOTICE, "%s-%d: Avalonm set volt %d",
  485. avalonm->drv->name, avalonm->device_id,
  486. info->set_voltage);
  487. if (info->power_on)
  488. cgsleep_ms(1000);
  489. info->power_on = 0;
  490. }
  491. static inline void avalonm_detect(bool __maybe_unused hotplug)
  492. {
  493. usb_detect(&avalonm_drv, avalonm_detect_one);
  494. }
  495. static int avalonm_get_reports(void *userdata)
  496. {
  497. struct cgpu_info *avalonm = (struct cgpu_info *)userdata;
  498. struct avalonm_info *info = avalonm->device_data;
  499. struct thr_info *thr = info->thr;
  500. struct avalonm_pkg send_pkg;
  501. struct avalonm_ret ar;
  502. int ret = 0;
  503. memset(send_pkg.data, 0, AVAM_P_DATA_LEN);
  504. avalonm_init_pkg(&send_pkg, AVAM_P_POLLING, 1, 1);
  505. ret = avalonm_xfer_pkg(avalonm, &send_pkg, &ar);
  506. if (ret == AVAM_SEND_OK) {
  507. ret = decode_pkg(thr, &ar);
  508. }
  509. return ret;
  510. }
  511. static void rev(unsigned char *s, size_t l)
  512. {
  513. size_t i, j;
  514. unsigned char t;
  515. for (i = 0, j = l - 1; i < j; i++, j--) {
  516. t = s[i];
  517. s[i] = s[j];
  518. s[j] = t;
  519. }
  520. }
  521. static int64_t avalonm_scanhash(struct thr_info *thr)
  522. {
  523. struct cgpu_info *avalonm = thr->cgpu;
  524. struct avalonm_info *info = avalonm->device_data;
  525. int64_t hash_count, ms_timeout;
  526. struct timeval current;
  527. double device_tdiff;
  528. uint32_t i, j, tmp;
  529. /* Half nonce range */
  530. ms_timeout = 0x80000000ll / 1000;
  531. /* Wait until avalon_send_tasks signals us that it has completed
  532. * sending its work or a full nonce range timeout has occurred. We use
  533. * cgsems to never miss a wakeup. */
  534. cgsem_mswait(&info->qsem, ms_timeout);
  535. hash_count = info->nonce_cnts++;
  536. info->nonce_cnts = 0;
  537. cgtime(&current);
  538. device_tdiff = tdiff(&current, &(info->lastadj));
  539. if (opt_avalonm_autof && (device_tdiff > AVAM_DEFAULT_ADJ_INTERVAL || device_tdiff < 0)) {
  540. copy_time(&info->lastadj, &current);
  541. for (i = 0; i < AVAM_DEFAULT_ASIC_COUNT; i++) {
  542. tmp = 0;
  543. for (j = 0; j < AVAM_DEFAULT_MOV_TIMES; j++)
  544. tmp += info->hw_work_i[i][j];
  545. if (tmp > AVAM_HW_HIGH && (info->opt_freq[i][0] > opt_avalonm_freq[0] - (uint32_t)(12 * 12.5))) {
  546. if ((info->opt_freq[i][0] == AVAM_DEFAULT_FREQUENCY_MIN) &&
  547. (info->opt_freq[i][1] == AVAM_DEFAULT_FREQUENCY_MIN) &&
  548. (info->opt_freq[i][2] == AVAM_DEFAULT_FREQUENCY_MIN))
  549. continue;
  550. if (info->opt_freq[i][0] * 10 % 125)
  551. info->opt_freq[i][0] -= 13;
  552. else
  553. info->opt_freq[i][0] -= 12;
  554. if (info->opt_freq[i][1] * 10 % 125)
  555. info->opt_freq[i][1] -= 13;
  556. else
  557. info->opt_freq[i][1] -= 12;
  558. if (info->opt_freq[i][2] * 10 % 125)
  559. info->opt_freq[i][2] -= 13;
  560. else
  561. info->opt_freq[i][2] -= 12;
  562. if (info->opt_freq[i][0] < AVAM_DEFAULT_FREQUENCY_MIN)
  563. info->opt_freq[i][0] = AVAM_DEFAULT_FREQUENCY_MIN;
  564. if (info->opt_freq[i][1] < AVAM_DEFAULT_FREQUENCY_MIN)
  565. info->opt_freq[i][1] = AVAM_DEFAULT_FREQUENCY_MIN;
  566. if (info->opt_freq[i][2] < AVAM_DEFAULT_FREQUENCY_MIN)
  567. info->opt_freq[i][2] = AVAM_DEFAULT_FREQUENCY_MIN;
  568. FLAG_SET(info->freq_set, i + 1);
  569. applog(LOG_NOTICE, "%s-%d: Automatic decrease [%d] freq to %d,%d,%d",
  570. avalonm->drv->name, avalonm->device_id, i,
  571. info->opt_freq[i][0],
  572. info->opt_freq[i][1],
  573. info->opt_freq[i][2]);
  574. }
  575. if (tmp < AVAM_HW_LOW && (info->opt_freq[i][0] < opt_avalonm_freq[0] + (uint32_t)(8 * 12.5))) {
  576. if ((info->opt_freq[i][0] == AVAM_DEFAULT_FREQUENCY_MAX) &&
  577. (info->opt_freq[i][1] == AVAM_DEFAULT_FREQUENCY_MAX) &&
  578. (info->opt_freq[i][2] == AVAM_DEFAULT_FREQUENCY_MAX))
  579. continue;
  580. if (info->opt_freq[i][0] * 10 % 125)
  581. info->opt_freq[i][0] += 12;
  582. else
  583. info->opt_freq[i][0] += 13;
  584. if (info->opt_freq[i][1] * 10 % 125)
  585. info->opt_freq[i][1] += 12;
  586. else
  587. info->opt_freq[i][1] += 13;
  588. if (info->opt_freq[i][2] * 10 % 125)
  589. info->opt_freq[i][2] += 12;
  590. else
  591. info->opt_freq[i][2] += 13;
  592. if (info->opt_freq[i][0] > AVAM_DEFAULT_FREQUENCY_MAX)
  593. info->opt_freq[i][0] = AVAM_DEFAULT_FREQUENCY_MAX;
  594. if (info->opt_freq[i][1] > AVAM_DEFAULT_FREQUENCY_MAX)
  595. info->opt_freq[i][1] = AVAM_DEFAULT_FREQUENCY_MAX;
  596. if (info->opt_freq[i][2] > AVAM_DEFAULT_FREQUENCY_MAX)
  597. info->opt_freq[i][2] = AVAM_DEFAULT_FREQUENCY_MAX;
  598. FLAG_SET(info->freq_set, i + 1);
  599. applog(LOG_NOTICE, "%s-%d: Automatic increase [%d] freq to %d,%d,%d",
  600. avalonm->drv->name, avalonm->device_id, i,
  601. info->opt_freq[i][0],
  602. info->opt_freq[i][1],
  603. info->opt_freq[i][2]);
  604. }
  605. }
  606. }
  607. return hash_count * 0xffffffffull;
  608. }
  609. static void avalonm_rotate_array(struct cgpu_info *avalonm, struct avalonm_info *info)
  610. {
  611. mutex_lock(&info->qlock);
  612. avalonm->queued = 0;
  613. if (++avalonm->work_array >= AVAM_DEFAULT_ARRAY_SIZE)
  614. avalonm->work_array = 0;
  615. mutex_unlock(&info->qlock);
  616. }
  617. static void *avalonm_process_tasks(void *userdata)
  618. {
  619. char threadname[16];
  620. struct cgpu_info *avalonm = userdata;
  621. struct avalonm_info *info = avalonm->device_data;
  622. struct work *work;
  623. struct avalonm_pkg send_pkg;
  624. int start_count, end_count, i, j, k, ret;
  625. int avalon_get_work_count = info->asic_cnts;
  626. struct timeval current;
  627. double device_tdiff;
  628. snprintf(threadname, sizeof(threadname), "%d/AvmProc", avalonm->device_id);
  629. RenameThread(threadname);
  630. while (likely(!avalonm->shutdown)) {
  631. if (unlikely(avalonm->usbinfo.nodev)) {
  632. applog(LOG_ERR, "%s-%d: Device disappeared, shutting down thread",
  633. avalonm->drv->name, avalonm->device_id);
  634. goto out;
  635. }
  636. cgtime(&current);
  637. device_tdiff = tdiff(&current, &(info->lasttime));
  638. if (device_tdiff >= AVAM_DEFAULT_MOV_TIMES || device_tdiff < 0) {
  639. copy_time(&info->lasttime, &current);
  640. if (info->time_i++ >= AVAM_DEFAULT_MOV_TIMES)
  641. info->time_i = 0;
  642. for(i = 0; i < AVAM_DEFAULT_ASIC_COUNT; i++)
  643. info->hw_work_i[i][info->time_i] = 0;
  644. }
  645. /* Give other threads a chance to acquire qlock. */
  646. i = 0;
  647. do {
  648. cgsleep_ms(40);
  649. } while (!avalonm->shutdown && avalonm->queued < avalon_get_work_count);
  650. mutex_lock(&info->qlock);
  651. start_count = avalonm->work_array * avalon_get_work_count;
  652. end_count = start_count + avalon_get_work_count;
  653. for (i = start_count, j = 0; i < end_count; i++, j++) {
  654. work = avalonm->works[i];
  655. if (likely(j < avalonm->queued && avalonm->works[i] && j < (info->asic_cnts - opt_avalonm_ntime_offset))) {
  656. /* Configuration */
  657. avalonm_set_voltage(avalonm);
  658. if (FLAG_GET(info->freq_set, 0)) {
  659. avalonm_set_freq(avalonm, AVAM_ASIC_ALL, info->opt_freq[0]);
  660. FLAG_CLEAR(info->freq_set, 0);
  661. cgsleep_ms(20);
  662. }
  663. for (k = 1; k <= info->asic_cnts; k++) {
  664. if (FLAG_GET(info->freq_set, k)) {
  665. avalonm_set_freq(avalonm, k, info->opt_freq[k - 1]);
  666. FLAG_CLEAR(info->freq_set, k);
  667. cgsleep_ms(20);
  668. }
  669. }
  670. /* P_WORK part 1: midstate */
  671. memcpy(send_pkg.data, work->midstate, AVAM_P_DATA_LEN);
  672. rev((void *)(send_pkg.data), AVAM_P_DATA_LEN);
  673. avalonm_init_pkg(&send_pkg, AVAM_P_WORK, 1, 2);
  674. hexdump(send_pkg.data, 32);
  675. avalonm_send_pkg(avalonm, &send_pkg);
  676. if (info->freq_update)
  677. cgsleep_ms(300);
  678. /* P_WORK part 2:
  679. * id(6)+reserved(2)+ntime(1)+fan(3)+led(4)+reserved(4)+data(12) */
  680. memset(send_pkg.data, 0, AVAM_P_DATA_LEN);
  681. UNPACK32(work->id, send_pkg.data);
  682. /* always roll work 0 */
  683. if (j == 0)
  684. send_pkg.data[8] = opt_avalonm_ntime_offset;
  685. else
  686. send_pkg.data[8] = 0;
  687. /* TODO led */
  688. UNPACK32(0, send_pkg.data + 12);
  689. memcpy(send_pkg.data + 20, work->data + 64, 12);
  690. rev((void *)(send_pkg.data + 20), 12);
  691. avalonm_init_pkg(&send_pkg, AVAM_P_WORK, 2, 2);
  692. hexdump(send_pkg.data, 32);
  693. avalonm_send_pkg(avalonm, &send_pkg);
  694. if (info->freq_update)
  695. cgsleep_ms(300);
  696. }
  697. }
  698. mutex_unlock(&info->qlock);
  699. avalonm_rotate_array(avalonm, info);
  700. cgsem_post(&info->qsem);
  701. /* little delay, let asics process more job */
  702. if (!strncmp(info->ver, "3U", 2))
  703. cgsleep_ms(400);
  704. /* Get result */
  705. do {
  706. ret = avalonm_get_reports(avalonm);
  707. cgsleep_ms(5);
  708. } while (ret != AVAM_P_STATUS_M);
  709. if (info->freq_update) {
  710. applog(LOG_NOTICE, "%s-%d: avalonm_process_tasks freq change flag %02x",
  711. avalonm->drv->name, avalonm->device_id,
  712. info->freq_update);
  713. if (FLAG_GET(info->freq_update, 0)) {
  714. avalonm_get_frequency(avalonm, 0);
  715. FLAG_CLEAR(info->freq_update, 0);
  716. }
  717. for (i = 1; i <= info->asic_cnts; i++) {
  718. if (FLAG_GET(info->freq_update, i)) {
  719. avalonm_get_frequency(avalonm, i);
  720. FLAG_CLEAR(info->freq_update, i);
  721. }
  722. }
  723. }
  724. cgsleep_ms(info->delay_ms);
  725. }
  726. out:
  727. return NULL;
  728. }
  729. static bool avalonm_prepare(struct thr_info *thr)
  730. {
  731. struct cgpu_info *avalonm = thr->cgpu;
  732. struct avalonm_info *info = avalonm->device_data;
  733. free(avalonm->works);
  734. avalonm->works = calloc(info->asic_cnts * sizeof(struct work *),
  735. AVAM_DEFAULT_ARRAY_SIZE);
  736. if (!avalonm->works)
  737. quit(1, "Failed to calloc avalon miner works in avalonm_prepare");
  738. info->thr = thr;
  739. info->delay_ms = CAL_DELAY(AVAM_DEFAULT_FREQUENCY);
  740. info->power_on = 1;
  741. mutex_init(&info->lock);
  742. mutex_init(&info->qlock);
  743. cgsem_init(&info->qsem);
  744. if (pthread_create(&info->process_thr, NULL, avalonm_process_tasks, (void *)avalonm))
  745. quit(1, "Failed to create avalonm process_thr");
  746. return true;
  747. }
  748. static void avalonm_shutdown(struct thr_info *thr)
  749. {
  750. struct cgpu_info *avalonm = thr->cgpu;
  751. struct avalonm_info *info = avalonm->device_data;
  752. pthread_join(info->process_thr, NULL);
  753. cgsem_destroy(&info->qsem);
  754. mutex_destroy(&info->qlock);
  755. mutex_destroy(&info->lock);
  756. free(avalonm->works);
  757. avalonm->works = NULL;
  758. }
  759. char *set_avalonm_freq(char *arg)
  760. {
  761. char *colon1, *colon2;
  762. int val1 = 0, val2 = 0, val3 = 0;
  763. if (!(*arg))
  764. return NULL;
  765. colon1 = strchr(arg, ':');
  766. if (colon1)
  767. *(colon1++) = '\0';
  768. if (*arg) {
  769. val1 = atoi(arg);
  770. if (val1 < AVAM_DEFAULT_FREQUENCY_MIN || val1 > AVAM_DEFAULT_FREQUENCY_MAX)
  771. return "Invalid value1 passed to set_avalonm_freq";
  772. }
  773. if (colon1 && *colon1) {
  774. colon2 = strchr(colon1, ':');
  775. if (colon2)
  776. *(colon2++) = '\0';
  777. if (*colon1) {
  778. val2 = atoi(colon1);
  779. if (val2 < AVAM_DEFAULT_FREQUENCY_MIN || val2 > AVAM_DEFAULT_FREQUENCY_MAX)
  780. return "Invalid value2 passed to set_avalonm_freq";
  781. }
  782. if (colon2 && *colon2) {
  783. val3 = atoi(colon2);
  784. if (val3 < AVAM_DEFAULT_FREQUENCY_MIN || val3 > AVAM_DEFAULT_FREQUENCY_MAX)
  785. return "Invalid value3 passed to set_avalonm_freq";
  786. }
  787. }
  788. if (!val1)
  789. val3 = val2 = val1 = AVAM_DEFAULT_FREQUENCY;
  790. if (!val2)
  791. val3 = val2 = val1;
  792. if (!val3)
  793. val3 = val2;
  794. opt_avalonm_freq[0] = val1;
  795. opt_avalonm_freq[1] = val2;
  796. opt_avalonm_freq[2] = val3;
  797. applog(LOG_NOTICE, "Update all asic frequency to %d",
  798. (opt_avalonm_freq[0] * 4 + opt_avalonm_freq[1] * 4 + opt_avalonm_freq[2]) / 9);
  799. return NULL;
  800. }
  801. char *set_avalonm_device_freq(struct cgpu_info *avalonm, char *arg)
  802. {
  803. struct avalonm_info *info = avalonm->device_data;
  804. char *colon1, *colon2;
  805. int val1 = 0, val2 = 0, val3 = 0;
  806. int asic_index = AVAM_ASIC_ALL;
  807. uint8_t i;
  808. if (!(*arg))
  809. return NULL;
  810. colon1 = strchr(arg, '-');
  811. if (colon1) {
  812. sscanf(arg, "%d-", &asic_index);
  813. arg = colon1 + 1;
  814. if (asic_index < 0 || asic_index > info->asic_cnts) {
  815. applog(LOG_ERR, "invalid asic index: %d, valid range 0-%d", asic_index, info->asic_cnts);
  816. return "Invalid asic index to set_avalonm_freq";
  817. }
  818. }
  819. colon1 = strchr(arg, ':');
  820. if (colon1)
  821. *(colon1++) = '\0';
  822. if (*arg) {
  823. val1 = atoi(arg);
  824. if (val1 < AVAM_DEFAULT_FREQUENCY_MIN || val1 > AVAM_DEFAULT_FREQUENCY_MAX)
  825. return "Invalid value1 passed to set_avalonm_freq";
  826. }
  827. if (colon1 && *colon1) {
  828. colon2 = strchr(colon1, ':');
  829. if (colon2)
  830. *(colon2++) = '\0';
  831. if (*colon1) {
  832. val2 = atoi(colon1);
  833. if (val2 < AVAM_DEFAULT_FREQUENCY_MIN || val2 > AVAM_DEFAULT_FREQUENCY_MAX)
  834. return "Invalid value2 passed to set_avalonm_freq";
  835. }
  836. if (colon2 && *colon2) {
  837. val3 = atoi(colon2);
  838. if (val3 < AVAM_DEFAULT_FREQUENCY_MIN || val3 > AVAM_DEFAULT_FREQUENCY_MAX)
  839. return "Invalid value3 passed to set_avalonm_freq";
  840. }
  841. }
  842. if (!val1)
  843. val3 = val2 = val1 = AVAM_DEFAULT_FREQUENCY;
  844. if (!val2)
  845. val3 = val2 = val1;
  846. if (!val3)
  847. val3 = val2;
  848. if (!asic_index) {
  849. for (i = 0; i < info->asic_cnts; i++) {
  850. info->opt_freq[i][0] = val1;
  851. info->opt_freq[i][1] = val2;
  852. info->opt_freq[i][2] = val3;
  853. }
  854. FLAG_SET(info->freq_set, AVAM_ASIC_ALL);
  855. applog(LOG_NOTICE, "Update all asic frequency to %d",
  856. (val1 * 4 + val2 * 4 + val3) / 9);
  857. }
  858. if (asic_index) {
  859. info->opt_freq[asic_index - 1][0] = val1;
  860. info->opt_freq[asic_index - 1][1] = val2;
  861. info->opt_freq[asic_index - 1][2] = val3;
  862. FLAG_SET(info->freq_set, asic_index);
  863. applog(LOG_NOTICE, "Update asic %d frequency to %d",
  864. asic_index - 1,
  865. (val1 * 4 + val2 * 4 + val3) / 9);
  866. }
  867. return NULL;
  868. }
  869. char *set_avalonm_voltage(char *arg)
  870. {
  871. int val, ret;
  872. ret = sscanf(arg, "%d", &val);
  873. if (ret < 1)
  874. return "No values passed to avalonm-voltage";
  875. if (val < AVAM_DEFAULT_VOLTAGE_MIN || val > AVAM_DEFAULT_VOLTAGE_MAX)
  876. return "Invalid value passed to avalonm-voltage";
  877. opt_avalonm_voltage = val;
  878. return NULL;
  879. }
  880. char *set_avalonm_device_voltage(struct cgpu_info *avalonm, char *arg)
  881. {
  882. struct avalonm_info *info = avalonm->device_data;
  883. int val, ret;
  884. ret = sscanf(arg, "%d", &val);
  885. if (ret < 1)
  886. return "No values passed to avalonm-voltage";
  887. if (val < AVAM_DEFAULT_VOLTAGE_MIN || val > AVAM_DEFAULT_VOLTAGE_MAX)
  888. return "Invalid value passed to avalonm-voltage";
  889. info->opt_voltage = val;
  890. applog(LOG_NOTICE, "%s-%d: Update voltage to %d",
  891. avalonm->drv->name, avalonm->device_id, info->opt_voltage);
  892. return NULL;
  893. }
  894. static char *avalonm_set_device(struct cgpu_info *avalonm, char *option, char *setting, char *replybuf, size_t siz)
  895. {
  896. if (strcasecmp(option, "help") == 0) {
  897. snprintf(replybuf, siz, "frequency|voltage");
  898. return replybuf;
  899. }
  900. if (strcasecmp(option, "frequency") == 0) {
  901. if (!setting || !*setting) {
  902. snprintf(replybuf, siz, "missing frequency value");
  903. return replybuf;
  904. }
  905. if (set_avalonm_device_freq(avalonm, setting)) {
  906. snprintf(replybuf, siz, "invalid frequency value, valid range %d-%d",
  907. AVAM_DEFAULT_FREQUENCY_MIN, AVAM_DEFAULT_FREQUENCY_MAX);
  908. return replybuf;
  909. }
  910. return NULL;
  911. }
  912. if (strcasecmp(option, "voltage") == 0) {
  913. if (!setting || !*setting) {
  914. snprintf(replybuf, siz, "missing voltage value");
  915. return replybuf;
  916. }
  917. if (set_avalonm_device_voltage(avalonm, setting)) {
  918. snprintf(replybuf, siz, "invalid voltage value, valid range %d-%d",
  919. AVAM_DEFAULT_VOLTAGE_MIN, AVAM_DEFAULT_VOLTAGE_MAX);
  920. return replybuf;
  921. }
  922. return NULL;
  923. }
  924. snprintf(replybuf, siz, "Unknown option: %s", option);
  925. return replybuf;
  926. }
  927. #define STATBUFLEN 512
  928. static struct api_data *avalonm_api_stats(struct cgpu_info *cgpu)
  929. {
  930. struct api_data *root = NULL;
  931. struct avalonm_info *info = cgpu->device_data;
  932. char buf[256];
  933. char statbuf[STATBUFLEN];
  934. uint32_t i, j, tmp;
  935. struct timeval now;
  936. memset(statbuf, 0, STATBUFLEN);
  937. sprintf(buf, "VER[%s]", info->ver);
  938. strcat(statbuf, buf);
  939. sprintf(buf, " DNA[%02x%02x%02x%02x%02x%02x%02x%02x]",
  940. info->dna[0],
  941. info->dna[1],
  942. info->dna[2],
  943. info->dna[3],
  944. info->dna[4],
  945. info->dna[5],
  946. info->dna[6],
  947. info->dna[7]);
  948. strcat(statbuf, buf);
  949. cgtime(&now);
  950. sprintf(buf, " Elapsed[%.0f]", tdiff(&now, &(info->elapsed)));
  951. strcat(statbuf, buf);
  952. sprintf(buf, " Chips[%d]", info->asic_cnts);
  953. strcat(statbuf, buf);
  954. sprintf(buf, " Crc[%d]", info->crcerr_cnt);
  955. strcat(statbuf, buf);
  956. sprintf(buf, " Speed[%d]", info->spi_speed);
  957. strcat(statbuf, buf);
  958. if (!strncmp(info->ver, "3U", 2))
  959. sprintf(buf, " Vol[%.2f]", (float)info->get_voltage);
  960. else
  961. sprintf(buf, " Vol[%.4f]", (float)info->get_voltage / 10000);
  962. strcat(statbuf, buf);
  963. if (!strncmp(info->ver, "3U", 2))
  964. sprintf(buf, " V_CORE[%.2f]", convert_voltage(info->adc[0], 1));
  965. else
  966. sprintf(buf, " V12[%.2f]", convert_voltage(info->adc[0], (10 / 110)));
  967. strcat(statbuf, buf);
  968. if (!strncmp(info->ver, "3U", 2))
  969. sprintf(buf, " T[%d]", info->adc[1]);
  970. else
  971. sprintf(buf, " TC[%.2f]", convert_temp(info->adc[1]));
  972. strcat(statbuf, buf);
  973. if (!strncmp(info->ver, "3U", 2)) {
  974. sprintf(buf, " V0_9[%.2f]", convert_voltage(info->adc[2] & 0xffff, 1));
  975. strcat(statbuf, buf);
  976. sprintf(buf, " V1_8[%.2f]", convert_voltage((info->adc[2] >> 16) & 0xffff, 1));
  977. } else
  978. sprintf(buf, " TF[%.2f]", convert_temp(info->adc[2]));
  979. strcat(statbuf, buf);
  980. if (!strncmp(info->ver, "3U", 2)) {
  981. sprintf(buf, " Freq[%d]", info->get_frequency[0][0]);
  982. strcat(statbuf, buf);
  983. } else {
  984. strcat(statbuf, " Freq[");
  985. for (i = 0; i < info->asic_cnts; i++) {
  986. sprintf(buf, "%d %d %d ",
  987. info->get_frequency[i][0],
  988. info->get_frequency[i][1],
  989. info->get_frequency[i][2]);
  990. strcat(statbuf, buf);
  991. }
  992. statbuf[strlen(statbuf) - 1] = ']';
  993. }
  994. strcat(statbuf, " HW[");
  995. for (i = 0; i < info->asic_cnts; i++) {
  996. sprintf(buf, "%d ", info->hw_work[i]);
  997. strcat(statbuf, buf);
  998. }
  999. statbuf[strlen(statbuf) - 1] = ']';
  1000. /* simple moving the sum of hardware error */
  1001. strcat(statbuf, " SHW[");
  1002. for (i = 0; i < info->asic_cnts; i++) {
  1003. tmp = 0;
  1004. for (j = 0; j < AVAM_DEFAULT_MOV_TIMES; j++)
  1005. tmp += info->hw_work_i[i][j];
  1006. sprintf(buf, "%d ", tmp);
  1007. strcat(statbuf, buf);
  1008. }
  1009. statbuf[strlen(statbuf) - 1] = ']';
  1010. strcat(statbuf, " MW[");
  1011. for (i = 0; i < info->asic_cnts; i++) {
  1012. sprintf(buf, "%ld ", info->matching_work[i]);
  1013. strcat(statbuf, buf);
  1014. }
  1015. statbuf[strlen(statbuf) - 1] = ']';
  1016. sprintf(buf, " Led[%d]", info->led_status);
  1017. strcat(statbuf, buf);
  1018. sprintf(buf, " PG[%d]", info->power_good);
  1019. strcat(statbuf, buf);
  1020. root = api_add_string(root, "AVAM Dev", statbuf, true);
  1021. sprintf(buf, "%d %d %d",
  1022. info->usbfifo_cnt,
  1023. info->workfifo_cnt,
  1024. info->noncefifo_cnt);
  1025. root = api_add_string(root, "AVAM Fifo", buf, true);
  1026. root = api_add_uint8(root, "AVAM ntime", &opt_avalonm_ntime_offset, true);
  1027. root = api_add_bool(root, "Automatic Frequency", &opt_avalonm_autof, true);
  1028. return root;
  1029. }
  1030. static void avalonm_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalonm)
  1031. {
  1032. struct avalonm_info *info = avalonm->device_data;
  1033. int frequency;
  1034. if (!strncmp(info->ver, "3U", 2))
  1035. tailsprintf(buf, bufsiz, "%4dMhz %.2fV", info->get_frequency[0][0], (float)info->get_voltage);
  1036. else {
  1037. frequency = (info->set_frequency[0][0] * 4 + info->set_frequency[0][1] * 4 + info->set_frequency[0][2]) / 9;
  1038. tailsprintf(buf, bufsiz, "%4dMhz %.4fV", frequency, (float)info->get_voltage / 10000);
  1039. }
  1040. }
  1041. /* We use a replacement algorithm to only remove references to work done from
  1042. * the buffer when we need the extra space for new work. */
  1043. static bool avalonm_fill(struct cgpu_info *avalonm)
  1044. {
  1045. struct avalonm_info *info = avalonm->device_data;
  1046. int subid, slot, ac;
  1047. struct work *work;
  1048. bool ret = true;
  1049. ac = info->asic_cnts;
  1050. mutex_lock(&info->qlock);
  1051. if (avalonm->queued >= ac)
  1052. goto out_unlock;
  1053. work = get_queued(avalonm);
  1054. if (unlikely(!work)) {
  1055. ret = false;
  1056. goto out_unlock;
  1057. }
  1058. subid = avalonm->queued++;
  1059. work->subid = subid;
  1060. slot = avalonm->work_array * ac + subid;
  1061. if (likely(avalonm->works[slot]))
  1062. work_completed(avalonm, avalonm->works[slot]);
  1063. avalonm->works[slot] = work;
  1064. if (avalonm->queued < ac)
  1065. ret = false;
  1066. out_unlock:
  1067. mutex_unlock(&info->qlock);
  1068. return ret;
  1069. }
  1070. static void avalonm_flush_work(struct cgpu_info *avalonm)
  1071. {
  1072. struct avalonm_info *info = avalonm->device_data;
  1073. /* Will overwrite any work queued. Do this unlocked since it's just
  1074. * changing a single non-critical value and prevents deadlocks */
  1075. avalonm->queued = 0;
  1076. /* Signal main loop we need more work */
  1077. cgsem_post(&info->qsem);
  1078. }
  1079. struct device_drv avalonm_drv = {
  1080. .drv_id = DRIVER_avalonm,
  1081. .dname = "avalonm",
  1082. .name = "AVM",
  1083. .set_device = avalonm_set_device,
  1084. .get_api_stats = avalonm_api_stats,
  1085. .get_statline_before = avalonm_statline_before,
  1086. .drv_detect = avalonm_detect,
  1087. .thread_prepare = avalonm_prepare,
  1088. .hash_work = hash_queued_work,
  1089. .scanwork = avalonm_scanhash,
  1090. .queue_full = avalonm_fill,
  1091. .flush_work = avalonm_flush_work,
  1092. .thread_shutdown = avalonm_shutdown,
  1093. };