driver-avalon2.c 23 KB

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  1. /*
  2. * Copyright 2013 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2014 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <sys/select.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #ifndef WIN32
  22. #include <termios.h>
  23. #include <sys/stat.h>
  24. #include <fcntl.h>
  25. #ifndef O_CLOEXEC
  26. #define O_CLOEXEC 0
  27. #endif
  28. #else
  29. #include <windows.h>
  30. #include <io.h>
  31. #endif
  32. #include "elist.h"
  33. #include "miner.h"
  34. #include "fpgautils.h"
  35. #include "driver-avalon2.h"
  36. #include "crc.h"
  37. #include "hexdump.c"
  38. #define ASSERT1(condition) __maybe_unused static char sizeof_uint32_t_must_be_4[(condition)?1:-1]
  39. ASSERT1(sizeof(uint32_t) == 4);
  40. int opt_avalon2_freq_min = AVA2_DEFAULT_FREQUENCY;
  41. int opt_avalon2_freq_max = AVA2_DEFAULT_FREQUENCY_MAX;
  42. int opt_avalon2_fan_min = AVA2_DEFAULT_FAN_PWM;
  43. int opt_avalon2_fan_max = AVA2_DEFAULT_FAN_MAX;
  44. int opt_avalon2_voltage_min = AVA2_DEFAULT_VOLTAGE;
  45. int opt_avalon2_voltage_max = AVA2_DEFAULT_VOLTAGE_MAX;
  46. int opt_avalon2_overheat = AVALON2_TEMP_OVERHEAT;
  47. static inline uint8_t rev8(uint8_t d)
  48. {
  49. int i;
  50. uint8_t out = 0;
  51. /* (from left to right) */
  52. for (i = 0; i < 8; i++)
  53. if (d & (1 << i))
  54. out |= (1 << (7 - i));
  55. return out;
  56. }
  57. char *set_avalon2_fan(char *arg)
  58. {
  59. int val1, val2, ret;
  60. ret = sscanf(arg, "%d-%d", &val1, &val2);
  61. if (ret < 1)
  62. return "No values passed to avalon2-fan";
  63. if (ret == 1)
  64. val2 = val1;
  65. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  66. return "Invalid value passed to avalon2-fan";
  67. opt_avalon2_fan_min = AVA2_PWM_MAX - val1 * AVA2_PWM_MAX / 100;
  68. opt_avalon2_fan_max = AVA2_PWM_MAX - val2 * AVA2_PWM_MAX / 100;
  69. return NULL;
  70. }
  71. char *set_avalon2_freq(char *arg)
  72. {
  73. int val1, val2, ret;
  74. ret = sscanf(arg, "%d-%d", &val1, &val2);
  75. if (ret < 1)
  76. return "No values passed to avalon2-freq";
  77. if (ret == 1)
  78. val2 = val1;
  79. if (val1 < AVA2_DEFAULT_FREQUENCY_MIN || val1 > AVA2_DEFAULT_FREQUENCY_MAX ||
  80. val2 < AVA2_DEFAULT_FREQUENCY_MIN || val2 > AVA2_DEFAULT_FREQUENCY_MAX ||
  81. val2 < val1)
  82. return "Invalid value passed to avalon2-freq";
  83. opt_avalon2_freq_min = val1;
  84. opt_avalon2_freq_max = val2;
  85. return NULL;
  86. }
  87. char *set_avalon2_voltage(char *arg)
  88. {
  89. int val1, val2, ret;
  90. ret = sscanf(arg, "%d-%d", &val1, &val2);
  91. if (ret < 1)
  92. return "No values passed to avalon2-voltage";
  93. if (ret == 1)
  94. val2 = val1;
  95. if (val1 < AVA2_DEFAULT_VOLTAGE_MIN || val1 > AVA2_DEFAULT_VOLTAGE_MAX ||
  96. val2 < AVA2_DEFAULT_VOLTAGE_MIN || val2 > AVA2_DEFAULT_VOLTAGE_MAX ||
  97. val2 < val1)
  98. return "Invalid value passed to avalon2-voltage";
  99. opt_avalon2_voltage_min = val1;
  100. opt_avalon2_voltage_max = val2;
  101. return NULL;
  102. }
  103. static int avalon2_init_pkg(struct avalon2_pkg *pkg, uint8_t type, uint8_t idx, uint8_t cnt)
  104. {
  105. unsigned short crc;
  106. pkg->head[0] = AVA2_H1;
  107. pkg->head[1] = AVA2_H2;
  108. pkg->type = type;
  109. pkg->idx = idx;
  110. pkg->cnt = cnt;
  111. crc = crc16(pkg->data, AVA2_P_DATA_LEN);
  112. pkg->crc[0] = (crc & 0xff00) >> 8;
  113. pkg->crc[1] = crc & 0x00ff;
  114. return 0;
  115. }
  116. static int job_idcmp(uint8_t *job_id, char *pool_job_id)
  117. {
  118. int i = 0;
  119. for (i = 0; i < 4; i++) {
  120. if (job_id[i] != *(pool_job_id + strlen(pool_job_id) - 4 + i))
  121. return 1;
  122. }
  123. return 0;
  124. }
  125. static inline int get_temp_max(struct avalon2_info *info)
  126. {
  127. int i;
  128. for (i = 0; i < 2 * AVA2_DEFAULT_MODULARS; i++) {
  129. if (info->temp_max <= info->temp[i])
  130. info->temp_max = info->temp[i];
  131. }
  132. return info->temp_max;
  133. }
  134. static inline int get_currect_temp_max(struct avalon2_info *info)
  135. {
  136. int i;
  137. int t = 0;
  138. for (i = 0; i < 2 * AVA2_DEFAULT_MODULARS; i++) {
  139. if (t <= info->temp[i])
  140. t = info->temp[i];
  141. }
  142. return t;
  143. }
  144. /* http://www.onsemi.com/pub_link/Collateral/ADP3208D.PDF */
  145. static inline uint32_t encode_voltage(uint32_t v)
  146. {
  147. return rev8((0x78 - v / 125) << 1 | 1) << 8;
  148. }
  149. static inline uint32_t decode_voltage(uint32_t v)
  150. {
  151. return (0x78 - (rev8(v >> 8) >> 1)) * 125;
  152. }
  153. extern void submit_nonce2_nonce(struct thr_info *thr, uint32_t pool_no, uint32_t nonce2, uint32_t nonce);
  154. static int decode_pkg(struct thr_info *thr, struct avalon2_ret *ar, uint8_t *pkg)
  155. {
  156. struct cgpu_info *avalon2;
  157. struct avalon2_info *info;
  158. struct pool *pool;
  159. unsigned int expected_crc;
  160. unsigned int actual_crc;
  161. uint32_t nonce, nonce2, miner, modular_id;
  162. int pool_no;
  163. uint8_t job_id[5];
  164. int tmp;
  165. int type = AVA2_GETS_ERROR;
  166. if (thr) {
  167. avalon2 = thr->cgpu;
  168. info = avalon2->device_data;
  169. }
  170. memcpy((uint8_t *)ar, pkg, AVA2_READ_SIZE);
  171. if (ar->head[0] == AVA2_H1 && ar->head[1] == AVA2_H2) {
  172. expected_crc = crc16(ar->data, AVA2_P_DATA_LEN);
  173. actual_crc = (ar->crc[0] & 0xff) |
  174. ((ar->crc[1] & 0xff) << 8);
  175. type = ar->type;
  176. applog(LOG_DEBUG, "Avalon2: %d: expected crc(%04x), actural_crc(%04x)", type, expected_crc, actual_crc);
  177. if (expected_crc != actual_crc)
  178. goto out;
  179. memcpy(&modular_id, ar->data + 28, 4);
  180. modular_id = be32toh(modular_id);
  181. if (modular_id > 3)
  182. modular_id = 0;
  183. switch(type) {
  184. case AVA2_P_NONCE:
  185. memcpy(&miner, ar->data + 0, 4);
  186. memcpy(&pool_no, ar->data + 4, 4);
  187. memcpy(&nonce2, ar->data + 8, 4);
  188. /* Calc time ar->data + 12 */
  189. memcpy(&nonce, ar->data + 16, 4);
  190. memset(job_id, 0, 5);
  191. memcpy(job_id, ar->data + 20, 4);
  192. miner = be32toh(miner);
  193. pool_no = be32toh(pool_no);
  194. if (miner >= AVA2_DEFAULT_MINERS ||
  195. modular_id >= AVA2_DEFAULT_MINERS ||
  196. pool_no >= total_pools ||
  197. pool_no < 0) {
  198. applog(LOG_DEBUG, "Avalon2: Wrong miner/pool/id no %d,%d,%d", miner, pool_no, modular_id);
  199. break;
  200. } else
  201. info->matching_work[modular_id * AVA2_DEFAULT_MINERS + miner]++;
  202. nonce2 = be32toh(nonce2);
  203. nonce = be32toh(nonce);
  204. nonce -= 0x180;
  205. applog(LOG_DEBUG, "Avalon2: Found! [%s] %d:(%08x) (%08x)",
  206. job_id, pool_no, nonce2, nonce);
  207. /* FIXME:
  208. * We need remember the pre_pool. then submit the stale work */
  209. pool = pools[pool_no];
  210. if (job_idcmp(job_id, pool->swork.job_id))
  211. break;
  212. if (thr && !info->new_stratum)
  213. submit_nonce2_nonce(thr, pool_no, nonce2, nonce);
  214. break;
  215. case AVA2_P_STATUS:
  216. memcpy(&tmp, ar->data, 4);
  217. tmp = be32toh(tmp);
  218. info->temp[0 + modular_id * 2] = tmp >> 16;
  219. info->temp[1 + modular_id * 2] = tmp & 0xffff;
  220. memcpy(&tmp, ar->data + 4, 4);
  221. tmp = be32toh(tmp);
  222. info->fan[0 + modular_id * 2] = tmp >> 16;
  223. info->fan[1 + modular_id * 2] = tmp & 0xffff;
  224. memcpy(&(info->get_frequency[modular_id]), ar->data + 8, 4);
  225. memcpy(&(info->get_voltage[modular_id]), ar->data + 12, 4);
  226. memcpy(&(info->local_work[modular_id]), ar->data + 16, 4);
  227. memcpy(&(info->hw_work[modular_id]), ar->data + 20, 4);
  228. memcpy(&(info->power_good[modular_id]), ar->data + 24, 4);
  229. info->get_frequency[modular_id] = be32toh(info->get_frequency[modular_id]);
  230. info->get_voltage[modular_id] = be32toh(info->get_voltage[modular_id]);
  231. info->local_work[modular_id] = be32toh(info->local_work[modular_id]);
  232. info->hw_work[modular_id] = be32toh(info->hw_work[modular_id]);
  233. info->local_works[modular_id] += info->local_work[modular_id];
  234. info->hw_works[modular_id] += info->hw_work[modular_id];
  235. info->get_voltage[modular_id] = decode_voltage(info->get_voltage[modular_id]);
  236. info->power_good[modular_id] = info->power_good[modular_id] >> 24;
  237. avalon2->temp = get_temp_max(info);
  238. break;
  239. case AVA2_P_ACKDETECT:
  240. break;
  241. case AVA2_P_ACK:
  242. break;
  243. case AVA2_P_NAK:
  244. break;
  245. default:
  246. type = AVA2_GETS_ERROR;
  247. break;
  248. }
  249. }
  250. out:
  251. return type;
  252. }
  253. static inline int avalon2_gets(int fd, uint8_t *buf)
  254. {
  255. int i;
  256. int read_amount = AVA2_READ_SIZE;
  257. uint8_t buf_tmp[AVA2_READ_SIZE];
  258. uint8_t buf_copy[2 * AVA2_READ_SIZE];
  259. uint8_t *buf_back = buf;
  260. ssize_t ret = 0;
  261. while (true) {
  262. struct timeval timeout;
  263. fd_set rd;
  264. timeout.tv_sec = 0;
  265. timeout.tv_usec = 100000;
  266. FD_ZERO(&rd);
  267. FD_SET(fd, &rd);
  268. ret = select(fd + 1, &rd, NULL, NULL, &timeout);
  269. if (unlikely(ret < 0)) {
  270. applog(LOG_ERR, "Avalon2: Error %d on select in avalon_gets", errno);
  271. return AVA2_GETS_ERROR;
  272. }
  273. if (ret) {
  274. memset(buf, 0, read_amount);
  275. ret = read(fd, buf, read_amount);
  276. if (unlikely(ret < 0)) {
  277. applog(LOG_ERR, "Avalon2: Error %d on read in avalon_gets", errno);
  278. return AVA2_GETS_ERROR;
  279. }
  280. if (likely(ret >= read_amount)) {
  281. for (i = 1; i < read_amount; i++) {
  282. if (buf_back[i - 1] == AVA2_H1 && buf_back[i] == AVA2_H2)
  283. break;
  284. }
  285. i -= 1;
  286. if (i) {
  287. ret = read(fd, buf_tmp, i);
  288. if (unlikely(ret != i)) {
  289. applog(LOG_ERR, "Avalon2: Error %d on read in avalon_gets", errno);
  290. return AVA2_GETS_ERROR;
  291. }
  292. memcpy(buf_copy, buf_back + i, AVA2_READ_SIZE - i);
  293. memcpy(buf_copy + AVA2_READ_SIZE - i, buf_tmp, i);
  294. memcpy(buf_back, buf_copy, AVA2_READ_SIZE);
  295. }
  296. return AVA2_GETS_OK;
  297. }
  298. buf += ret;
  299. read_amount -= ret;
  300. continue;
  301. }
  302. return AVA2_GETS_TIMEOUT;
  303. }
  304. }
  305. static int avalon2_send_pkg(int fd, const struct avalon2_pkg *pkg,
  306. struct thr_info __maybe_unused *thr)
  307. {
  308. int ret;
  309. uint8_t buf[AVA2_WRITE_SIZE];
  310. int nr_len = AVA2_WRITE_SIZE;
  311. memcpy(buf, pkg, AVA2_WRITE_SIZE);
  312. if (opt_debug) {
  313. applog(LOG_DEBUG, "Avalon2: Sent(%d):", nr_len);
  314. hexdump((uint8_t *)buf, nr_len);
  315. }
  316. ret = write(fd, buf, nr_len);
  317. if (unlikely(ret != nr_len)) {
  318. applog(LOG_DEBUG, "Avalon2: Send(%d)!", ret);
  319. return AVA2_SEND_ERROR;
  320. }
  321. cgsleep_ms(20);
  322. #if 0
  323. ret = avalon2_gets(fd, result);
  324. if (ret != AVA2_GETS_OK) {
  325. applog(LOG_DEBUG, "Avalon2: Get(%d)!", ret);
  326. return AVA2_SEND_ERROR;
  327. }
  328. ret = decode_pkg(thr, &ar, result);
  329. if (ret != AVA2_P_ACK) {
  330. applog(LOG_DEBUG, "Avalon2: PKG(%d)!", ret);
  331. hexdump((uint8_t *)result, AVA2_READ_SIZE);
  332. return AVA2_SEND_ERROR;
  333. }
  334. #endif
  335. return AVA2_SEND_OK;
  336. }
  337. static int avalon2_stratum_pkgs(int fd, struct pool *pool, struct thr_info *thr)
  338. {
  339. const int merkle_offset = 36;
  340. struct avalon2_pkg pkg;
  341. int i, a, b, tmp;
  342. unsigned char target[32];
  343. int job_id_len;
  344. /* Send out the first stratum message STATIC */
  345. applog(LOG_DEBUG, "Avalon2: Pool stratum message STATIC: %d, %d, %d, %d, %d",
  346. pool->coinbase_len,
  347. pool->nonce2_offset,
  348. pool->n2size,
  349. merkle_offset,
  350. pool->merkles);
  351. memset(pkg.data, 0, AVA2_P_DATA_LEN);
  352. tmp = be32toh(pool->coinbase_len);
  353. memcpy(pkg.data, &tmp, 4);
  354. tmp = be32toh(pool->nonce2_offset);
  355. memcpy(pkg.data + 4, &tmp, 4);
  356. tmp = be32toh(pool->n2size);
  357. memcpy(pkg.data + 8, &tmp, 4);
  358. tmp = be32toh(merkle_offset);
  359. memcpy(pkg.data + 12, &tmp, 4);
  360. tmp = be32toh(pool->merkles);
  361. memcpy(pkg.data + 16, &tmp, 4);
  362. tmp = be32toh((int)pool->swork.diff);
  363. memcpy(pkg.data + 20, &tmp, 4);
  364. tmp = be32toh((int)pool->pool_no);
  365. memcpy(pkg.data + 24, &tmp, 4);
  366. avalon2_init_pkg(&pkg, AVA2_P_STATIC, 1, 1);
  367. while (avalon2_send_pkg(fd, &pkg, thr) != AVA2_SEND_OK)
  368. ;
  369. set_target(target, pool->sdiff);
  370. memcpy(pkg.data, target, 32);
  371. if (opt_debug) {
  372. char *target_str;
  373. target_str = bin2hex(target, 32);
  374. applog(LOG_DEBUG, "Avalon2: Pool stratum target: %s", target_str);
  375. free(target_str);
  376. }
  377. avalon2_init_pkg(&pkg, AVA2_P_TARGET, 1, 1);
  378. while (avalon2_send_pkg(fd, &pkg, thr) != AVA2_SEND_OK)
  379. ;
  380. applog(LOG_DEBUG, "Avalon2: Pool stratum message JOBS_ID: %s",
  381. pool->swork.job_id);
  382. memset(pkg.data, 0, AVA2_P_DATA_LEN);
  383. job_id_len = strlen(pool->swork.job_id);
  384. job_id_len = job_id_len >= 4 ? 4 : job_id_len;
  385. for (i = 0; i < job_id_len; i++) {
  386. pkg.data[i] = *(pool->swork.job_id + strlen(pool->swork.job_id) - 4 + i);
  387. }
  388. avalon2_init_pkg(&pkg, AVA2_P_JOB_ID, 1, 1);
  389. while (avalon2_send_pkg(fd, &pkg, thr) != AVA2_SEND_OK)
  390. ;
  391. a = pool->coinbase_len / AVA2_P_DATA_LEN;
  392. b = pool->coinbase_len % AVA2_P_DATA_LEN;
  393. applog(LOG_DEBUG, "Avalon2: Pool stratum message COINBASE: %d %d", a, b);
  394. for (i = 0; i < a; i++) {
  395. memcpy(pkg.data, pool->coinbase + i * 32, 32);
  396. avalon2_init_pkg(&pkg, AVA2_P_COINBASE, i + 1, a + (b ? 1 : 0));
  397. while (avalon2_send_pkg(fd, &pkg, thr) != AVA2_SEND_OK)
  398. ;
  399. }
  400. if (b) {
  401. memset(pkg.data, 0, AVA2_P_DATA_LEN);
  402. memcpy(pkg.data, pool->coinbase + i * 32, b);
  403. avalon2_init_pkg(&pkg, AVA2_P_COINBASE, i + 1, i + 1);
  404. while (avalon2_send_pkg(fd, &pkg, thr) != AVA2_SEND_OK)
  405. ;
  406. }
  407. b = pool->merkles;
  408. applog(LOG_DEBUG, "Avalon2: Pool stratum message MERKLES: %d", b);
  409. for (i = 0; i < b; i++) {
  410. memset(pkg.data, 0, AVA2_P_DATA_LEN);
  411. memcpy(pkg.data, pool->swork.merkle_bin[i], 32);
  412. avalon2_init_pkg(&pkg, AVA2_P_MERKLES, i + 1, b);
  413. while (avalon2_send_pkg(fd, &pkg, thr) != AVA2_SEND_OK)
  414. ;
  415. }
  416. applog(LOG_DEBUG, "Avalon2: Pool stratum message HEADER: 4");
  417. for (i = 0; i < 4; i++) {
  418. memset(pkg.data, 0, AVA2_P_HEADER);
  419. memcpy(pkg.data, pool->header_bin + i * 32, 32);
  420. avalon2_init_pkg(&pkg, AVA2_P_HEADER, i + 1, 4);
  421. while (avalon2_send_pkg(fd, &pkg, thr) != AVA2_SEND_OK)
  422. ;
  423. }
  424. return 0;
  425. }
  426. static int avalon2_get_result(struct thr_info *thr, int fd_detect, struct avalon2_ret *ar)
  427. {
  428. struct cgpu_info *avalon2;
  429. struct avalon2_info *info;
  430. int fd;
  431. fd = fd_detect;
  432. if (thr) {
  433. avalon2 = thr->cgpu;
  434. info = avalon2->device_data;
  435. fd = info->fd;
  436. }
  437. uint8_t result[AVA2_READ_SIZE];
  438. int ret;
  439. memset(result, 0, AVA2_READ_SIZE);
  440. ret = avalon2_gets(fd, result);
  441. if (ret != AVA2_GETS_OK)
  442. return ret;
  443. if (opt_debug) {
  444. applog(LOG_DEBUG, "Avalon2: Get(ret = %d):", ret);
  445. hexdump((uint8_t *)result, AVA2_READ_SIZE);
  446. }
  447. return decode_pkg(thr, ar, result);
  448. }
  449. static bool avalon2_detect_one(const char *devpath)
  450. {
  451. struct avalon2_info *info;
  452. int ackdetect;
  453. int fd;
  454. int tmp, i, modular[AVA2_DEFAULT_MODULARS];
  455. char mm_version[AVA2_DEFAULT_MODULARS][16];
  456. struct cgpu_info *avalon2;
  457. struct avalon2_pkg detect_pkg;
  458. struct avalon2_ret ret_pkg;
  459. applog(LOG_DEBUG, "Avalon2 Detect: Attempting to open %s", devpath);
  460. fd = avalon2_open(devpath, AVA2_IO_SPEED, true);
  461. if (unlikely(fd == -1)) {
  462. applog(LOG_ERR, "Avalon2 Detect: Failed to open %s", devpath);
  463. return false;
  464. }
  465. tcflush(fd, TCIOFLUSH);
  466. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  467. modular[i] = 0;
  468. strcpy(mm_version[i], AVA2_MM_VERNULL);
  469. /* Send out detect pkg */
  470. memset(detect_pkg.data, 0, AVA2_P_DATA_LEN);
  471. tmp = be32toh(i);
  472. memcpy(detect_pkg.data + 28, &tmp, 4);
  473. avalon2_init_pkg(&detect_pkg, AVA2_P_DETECT, 1, 1);
  474. avalon2_send_pkg(fd, &detect_pkg, NULL);
  475. ackdetect = avalon2_get_result(NULL, fd, &ret_pkg);
  476. applog(LOG_DEBUG, "Avalon2 Detect ID[%d]: %d", i, ackdetect);
  477. if (ackdetect != AVA2_P_ACKDETECT)
  478. continue;
  479. modular[i] = 1;
  480. memcpy(mm_version[i], ret_pkg.data, 15);
  481. mm_version[i][15] = '\0';
  482. }
  483. if (!modular[0] && !modular[1] && !modular[2] && !modular[3])
  484. return false;
  485. /* We have a real Avalon! */
  486. avalon2 = calloc(1, sizeof(struct cgpu_info));
  487. avalon2->drv = &avalon2_drv;
  488. avalon2->device_path = strdup(devpath);
  489. avalon2->threads = AVA2_MINER_THREADS;
  490. add_cgpu(avalon2);
  491. applog(LOG_INFO, "Avalon2 Detect: Found at %s, mark as %d",
  492. devpath, avalon2->device_id);
  493. avalon2->device_data = calloc(sizeof(struct avalon2_info), 1);
  494. if (unlikely(!(avalon2->device_data)))
  495. quit(1, "Failed to malloc avalon2_info");
  496. info = avalon2->device_data;
  497. strcpy(info->mm_version[0], mm_version[0]);
  498. strcpy(info->mm_version[1], mm_version[1]);
  499. strcpy(info->mm_version[2], mm_version[2]);
  500. strcpy(info->mm_version[3], mm_version[3]);
  501. info->baud = AVA2_IO_SPEED;
  502. info->fan_pwm = AVA2_DEFAULT_FAN_PWM;
  503. info->set_voltage = AVA2_DEFAULT_VOLTAGE_MIN;
  504. info->set_frequency = AVA2_DEFAULT_FREQUENCY;
  505. info->temp_max = 0;
  506. info->temp_history_index = 0;
  507. info->temp_sum = 0;
  508. info->temp_old = 0;
  509. info->modulars[0] = modular[0];
  510. info->modulars[1] = modular[1];
  511. info->modulars[2] = modular[2]; /* Enable modular */
  512. info->modulars[3] = modular[3]; /* Enable modular */
  513. info->fd = -1;
  514. /* Set asic to idle mode after detect */
  515. avalon2_close(fd);
  516. return true;
  517. }
  518. static inline void avalon2_detect(bool __maybe_unused hotplug)
  519. {
  520. serial_detect(&avalon2_drv, avalon2_detect_one);
  521. }
  522. static void avalon2_init(struct cgpu_info *avalon2)
  523. {
  524. int fd;
  525. struct avalon2_info *info = avalon2->device_data;
  526. fd = avalon2_open(avalon2->device_path, info->baud, true);
  527. if (unlikely(fd == -1)) {
  528. applog(LOG_ERR, "Avalon2: Failed to open on %s", avalon2->device_path);
  529. return;
  530. }
  531. applog(LOG_DEBUG, "Avalon2: Opened on %s", avalon2->device_path);
  532. info->fd = fd;
  533. }
  534. static bool avalon2_prepare(struct thr_info *thr)
  535. {
  536. struct cgpu_info *avalon2 = thr->cgpu;
  537. struct avalon2_info *info = avalon2->device_data;
  538. free(avalon2->works);
  539. avalon2->works = calloc(sizeof(struct work *), 2);
  540. if (!avalon2->works)
  541. quit(1, "Failed to calloc avalon2 works in avalon2_prepare");
  542. if (info->fd == -1)
  543. avalon2_init(avalon2);
  544. info->first = true;
  545. return true;
  546. }
  547. static int polling(struct thr_info *thr)
  548. {
  549. int i, tmp;
  550. struct avalon2_pkg send_pkg;
  551. struct avalon2_ret ar;
  552. struct cgpu_info *avalon2 = thr->cgpu;
  553. struct avalon2_info *info = avalon2->device_data;
  554. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  555. if (info->modulars[i]) {
  556. memset(send_pkg.data, 0, AVA2_P_DATA_LEN);
  557. tmp = be32toh(i);
  558. memcpy(send_pkg.data + 28, &tmp, 4);
  559. avalon2_init_pkg(&send_pkg, AVA2_P_POLLING, 1, 1);
  560. while (avalon2_send_pkg(info->fd, &send_pkg, thr) != AVA2_SEND_OK)
  561. ;
  562. avalon2_get_result(thr, info->fd, &ar);
  563. }
  564. }
  565. return 0;
  566. }
  567. static int64_t avalon2_scanhash(struct thr_info *thr)
  568. {
  569. struct avalon2_pkg send_pkg;
  570. struct pool *pool;
  571. struct cgpu_info *avalon2 = thr->cgpu;
  572. struct avalon2_info *info = avalon2->device_data;
  573. int64_t h;
  574. uint32_t tmp, range, start;
  575. int i;
  576. if (thr->work_restart || thr->work_update ||
  577. info->first) {
  578. info->new_stratum = true;
  579. applog(LOG_DEBUG, "Avalon2: New stratum: restart: %d, update: %d, first: %d",
  580. thr->work_restart, thr->work_update, info->first);
  581. thr->work_update = false;
  582. thr->work_restart = false;
  583. if (unlikely(info->first))
  584. info->first = false;
  585. get_work(thr, thr->id); /* Make sure pool is ready */
  586. pool = current_pool();
  587. if (!pool->has_stratum)
  588. quit(1, "Avalon2: Miner Manager have to use stratum pool");
  589. if (pool->coinbase_len > AVA2_P_COINBASE_SIZE) {
  590. applog(LOG_ERR, "Avalon2: Miner Manager pool coinbase length have to less then %d", AVA2_P_COINBASE_SIZE);
  591. return 0;
  592. }
  593. if (pool->merkles > AVA2_P_MERKLES_COUNT) {
  594. applog(LOG_ERR, "Avalon2: Miner Manager merkles have to less then %d", AVA2_P_MERKLES_COUNT);
  595. return 0;
  596. }
  597. info->diff = (int)pool->swork.diff - 1;
  598. info->pool_no = pool->pool_no;
  599. cg_wlock(&pool->data_lock);
  600. avalon2_stratum_pkgs(info->fd, pool, thr);
  601. cg_wunlock(&pool->data_lock);
  602. /* Configuer the parameter from outside */
  603. info->fan_pwm = opt_avalon2_fan_min;
  604. info->set_voltage = opt_avalon2_voltage_min;
  605. info->set_frequency = opt_avalon2_freq_min;
  606. /* Set the Fan, Voltage and Frequency */
  607. memset(send_pkg.data, 0, AVA2_P_DATA_LEN);
  608. tmp = be32toh(info->fan_pwm);
  609. memcpy(send_pkg.data, &tmp, 4);
  610. applog(LOG_ERR, "Avalon2: Temp max: %d, Cut off temp: %d",
  611. get_currect_temp_max(info), opt_avalon2_overheat);
  612. if (get_currect_temp_max(info) >= opt_avalon2_overheat)
  613. tmp = encode_voltage(0);
  614. else
  615. tmp = encode_voltage(info->set_voltage);
  616. tmp = be32toh(tmp);
  617. memcpy(send_pkg.data + 4, &tmp, 4);
  618. tmp = be32toh(info->set_frequency);
  619. memcpy(send_pkg.data + 8, &tmp, 4);
  620. /* Configure the nonce2 offset and range */
  621. range = 0xffffffff / total_devices;
  622. start = range * avalon2->device_id;
  623. tmp = be32toh(start);
  624. memcpy(send_pkg.data + 12, &tmp, 4);
  625. tmp = be32toh(range);
  626. memcpy(send_pkg.data + 16, &tmp, 4);
  627. /* Package the data */
  628. avalon2_init_pkg(&send_pkg, AVA2_P_SET, 1, 1);
  629. while (avalon2_send_pkg(info->fd, &send_pkg, thr) != AVA2_SEND_OK)
  630. ;
  631. info->new_stratum = false;
  632. }
  633. polling(thr);
  634. h = 0;
  635. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  636. h += info->local_work[i];
  637. }
  638. return h * 0xffffffff;
  639. }
  640. static struct api_data *avalon2_api_stats(struct cgpu_info *cgpu)
  641. {
  642. struct api_data *root = NULL;
  643. struct avalon2_info *info = cgpu->device_data;
  644. int i, j, a, b;
  645. char buf[24];
  646. double hwp;
  647. int devtype[AVA2_DEFAULT_MODULARS];
  648. int minerindex, minercount;
  649. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  650. devtype[i] = AVA2_ID_AVAX;
  651. if (!strncmp((char *)&(info->mm_version[i]), AVA2_MM_VERNULL, 4))
  652. continue;
  653. if (!strncmp((char *)&(info->mm_version[i]), AVA2_FW2_PREFIXSTR, 2))
  654. devtype[i] = AVA2_ID_AVA2;
  655. if (!strncmp((char *)&(info->mm_version[i]), AVA2_FW3_PREFIXSTR, 2))
  656. devtype[i] = AVA2_ID_AVA3;
  657. sprintf(buf, "ID%d MM Version", i + 1);
  658. root = api_add_string(root, buf, &(info->mm_version[i]), false);
  659. }
  660. minerindex = 0;
  661. minercount = 0;
  662. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  663. if (devtype[i] == AVA2_ID_AVAX) {
  664. minerindex += AVA2_DEFAULT_MINERS;
  665. continue;
  666. }
  667. if (devtype[i] == AVA2_ID_AVA2)
  668. minercount = AVA2_DEFAULT_MINERS;
  669. if (devtype[i] == AVA2_ID_AVA3)
  670. minercount = AVA2_AVA3_MINERS;
  671. for (j = minerindex; j < (minerindex + minercount); j++) {
  672. sprintf(buf, "Match work count%02d", j+1);
  673. root = api_add_int(root, buf, &(info->matching_work[j]), false);
  674. }
  675. minerindex += AVA2_DEFAULT_MINERS;
  676. }
  677. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  678. if(devtype[i] == AVA2_ID_AVAX)
  679. continue;
  680. sprintf(buf, "Local works%d", i + 1);
  681. root = api_add_int(root, buf, &(info->local_works[i]), false);
  682. }
  683. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  684. if(devtype[i] == AVA2_ID_AVAX)
  685. continue;
  686. sprintf(buf, "Hardware error works%d", i + 1);
  687. root = api_add_int(root, buf, &(info->hw_works[i]), false);
  688. }
  689. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  690. if(devtype[i] == AVA2_ID_AVAX)
  691. continue;
  692. a = info->hw_works[i];
  693. b = info->local_works[i];
  694. hwp = b ? ((double)a / (double)b) : 0;
  695. sprintf(buf, "Device hardware error%d%%", i + 1);
  696. root = api_add_percent(root, buf, &hwp, true);
  697. }
  698. for (i = 0; i < 2 * AVA2_DEFAULT_MODULARS; i++) {
  699. if(devtype[i/2] == AVA2_ID_AVAX)
  700. continue;
  701. sprintf(buf, "Temperature%d", i + 1);
  702. root = api_add_int(root, buf, &(info->temp[i]), false);
  703. }
  704. for (i = 0; i < 2 * AVA2_DEFAULT_MODULARS; i++) {
  705. if(devtype[i/2] == AVA2_ID_AVAX)
  706. continue;
  707. sprintf(buf, "Fan%d", i + 1);
  708. root = api_add_int(root, buf, &(info->fan[i]), false);
  709. }
  710. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  711. if(devtype[i] == AVA2_ID_AVAX)
  712. continue;
  713. sprintf(buf, "Voltage%d", i + 1);
  714. root = api_add_int(root, buf, &(info->get_voltage[i]), false);
  715. }
  716. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  717. if(devtype[i] == AVA2_ID_AVAX)
  718. continue;
  719. sprintf(buf, "Frequency%d", i + 1);
  720. root = api_add_int(root, buf, &(info->get_frequency[i]), false);
  721. }
  722. for (i = 0; i < AVA2_DEFAULT_MODULARS; i++) {
  723. if(devtype[i] == AVA2_ID_AVAX)
  724. continue;
  725. sprintf(buf, "Power good %02x", i + 1);
  726. root = api_add_int(root, buf, &(info->power_good[i]), false);
  727. }
  728. return root;
  729. }
  730. static void avalon2_shutdown(struct thr_info *thr)
  731. {
  732. struct cgpu_info *avalon = thr->cgpu;
  733. free(avalon->works);
  734. avalon->works = NULL;
  735. }
  736. struct device_drv avalon2_drv = {
  737. .drv_id = DRIVER_avalon2,
  738. .dname = "avalon2",
  739. .name = "AV2",
  740. .get_api_stats = avalon2_api_stats,
  741. .drv_detect = avalon2_detect,
  742. .reinit_device = avalon2_init,
  743. .thread_prepare = avalon2_prepare,
  744. .hash_work = hash_driver_work,
  745. .scanwork = avalon2_scanhash,
  746. .thread_shutdown = avalon2_shutdown,
  747. };