boot.h 33 KB

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  1. /* Modified to use out for SPM access
  2. ** Peter Knight, Optiboot project http://optiboot.googlecode.com
  3. **
  4. ** Todo: Tidy up
  5. **
  6. ** "_short" routines execute 1 cycle faster and use 1 less word of flash
  7. ** by using "out" instruction instead of "sts".
  8. **
  9. ** Additional elpm variants that trust the value of RAMPZ
  10. */
  11. /* Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007 Eric B. Weddington
  12. All rights reserved.
  13. Redistribution and use in source and binary forms, with or without
  14. modification, are permitted provided that the following conditions are met:
  15. * Redistributions of source code must retain the above copyright
  16. notice, this list of conditions and the following disclaimer.
  17. * Redistributions in binary form must reproduce the above copyright
  18. notice, this list of conditions and the following disclaimer in
  19. the documentation and/or other materials provided with the
  20. distribution.
  21. * Neither the name of the copyright holders nor the names of
  22. contributors may be used to endorse or promote products derived
  23. from this software without specific prior written permission.
  24. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25. AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26. IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27. ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28. LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29. CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30. SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31. INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32. CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33. ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34. POSSIBILITY OF SUCH DAMAGE. */
  35. /* $Id: boot.h,v 1.27.2.3 2008/09/30 13:58:48 arcanum Exp $ */
  36. #ifndef _AVR_BOOT_H_
  37. #define _AVR_BOOT_H_ 1
  38. /** \file */
  39. /** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
  40. \code
  41. #include <avr/io.h>
  42. #include <avr/boot.h>
  43. \endcode
  44. The macros in this module provide a C language interface to the
  45. bootloader support functionality of certain AVR processors. These
  46. macros are designed to work with all sizes of flash memory.
  47. Global interrupts are not automatically disabled for these macros. It
  48. is left up to the programmer to do this. See the code example below.
  49. Also see the processor datasheet for caveats on having global interrupts
  50. enabled during writing of the Flash.
  51. \note Not all AVR processors provide bootloader support. See your
  52. processor datasheet to see if it provides bootloader support.
  53. \todo From email with Marek: On smaller devices (all except ATmega64/128),
  54. __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
  55. instructions - since the boot loader has a limited size, this could be an
  56. important optimization.
  57. \par API Usage Example
  58. The following code shows typical usage of the boot API.
  59. \code
  60. #include <inttypes.h>
  61. #include <avr/interrupt.h>
  62. #include <avr/pgmspace.h>
  63. void boot_program_page (uint32_t page, uint8_t *buf)
  64. {
  65. uint16_t i;
  66. uint8_t sreg;
  67. // Disable interrupts.
  68. sreg = SREG;
  69. cli();
  70. eeprom_busy_wait ();
  71. boot_page_erase (page);
  72. boot_spm_busy_wait (); // Wait until the memory is erased.
  73. for (i=0; i<SPM_PAGESIZE; i+=2)
  74. {
  75. // Set up little-endian word.
  76. uint16_t w = *buf++;
  77. w += (*buf++) << 8;
  78. boot_page_fill (page + i, w);
  79. }
  80. boot_page_write (page); // Store buffer in flash page.
  81. boot_spm_busy_wait(); // Wait until the memory is written.
  82. // Reenable RWW-section again. We need this if we want to jump back
  83. // to the application after bootloading.
  84. boot_rww_enable ();
  85. // Re-enable interrupts (if they were ever enabled).
  86. SREG = sreg;
  87. }\endcode */
  88. #include <avr/eeprom.h>
  89. #include <avr/io.h>
  90. #include <inttypes.h>
  91. #include <limits.h>
  92. /* Check for SPM Control Register in processor. */
  93. #if defined (SPMCSR)
  94. # define __SPM_REG SPMCSR
  95. #elif defined (SPMCR)
  96. # define __SPM_REG SPMCR
  97. #else
  98. # error AVR processor does not provide bootloader support!
  99. #endif
  100. /* Check for SPM Enable bit. */
  101. #if defined(SPMEN)
  102. # define __SPM_ENABLE SPMEN
  103. #elif defined(SELFPRGEN)
  104. # define __SPM_ENABLE SELFPRGEN
  105. #else
  106. # error Cannot find SPM Enable bit definition!
  107. #endif
  108. /** \ingroup avr_boot
  109. \def BOOTLOADER_SECTION
  110. Used to declare a function or variable to be placed into a
  111. new section called .bootloader. This section and its contents
  112. can then be relocated to any address (such as the bootloader
  113. NRWW area) at link-time. */
  114. #define BOOTLOADER_SECTION __attribute__ ((section (".bootloader")))
  115. /* Create common bit definitions. */
  116. #ifdef ASB
  117. #define __COMMON_ASB ASB
  118. #else
  119. #define __COMMON_ASB RWWSB
  120. #endif
  121. #ifdef ASRE
  122. #define __COMMON_ASRE ASRE
  123. #else
  124. #define __COMMON_ASRE RWWSRE
  125. #endif
  126. /* Define the bit positions of the Boot Lock Bits. */
  127. #define BLB12 5
  128. #define BLB11 4
  129. #define BLB02 3
  130. #define BLB01 2
  131. /** \ingroup avr_boot
  132. \def boot_spm_interrupt_enable()
  133. Enable the SPM interrupt. */
  134. #define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
  135. /** \ingroup avr_boot
  136. \def boot_spm_interrupt_disable()
  137. Disable the SPM interrupt. */
  138. #define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
  139. /** \ingroup avr_boot
  140. \def boot_is_spm_interrupt()
  141. Check if the SPM interrupt is enabled. */
  142. #define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
  143. /** \ingroup avr_boot
  144. \def boot_rww_busy()
  145. Check if the RWW section is busy. */
  146. #define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
  147. /** \ingroup avr_boot
  148. \def boot_spm_busy()
  149. Check if the SPM instruction is busy. */
  150. #define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
  151. /** \ingroup avr_boot
  152. \def boot_spm_busy_wait()
  153. Wait while the SPM instruction is busy. */
  154. #define boot_spm_busy_wait() do{}while(boot_spm_busy())
  155. #define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
  156. #define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
  157. #define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
  158. #define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
  159. #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
  160. #define __boot_page_fill_short(address, data) \
  161. (__extension__({ \
  162. __asm__ __volatile__ \
  163. ( \
  164. "movw r0, %3\n\t" \
  165. "out %0, %1\n\t" \
  166. "spm\n\t" \
  167. "clr r1\n\t" \
  168. : \
  169. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  170. "r" ((uint8_t)__BOOT_PAGE_FILL), \
  171. "z" ((uint16_t)address), \
  172. "r" ((uint16_t)data) \
  173. : "r0" \
  174. ); \
  175. }))
  176. #define __boot_page_fill_normal(address, data) \
  177. (__extension__({ \
  178. __asm__ __volatile__ \
  179. ( \
  180. "movw r0, %3\n\t" \
  181. "sts %0, %1\n\t" \
  182. "spm\n\t" \
  183. "clr r1\n\t" \
  184. : \
  185. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  186. "r" ((uint8_t)__BOOT_PAGE_FILL), \
  187. "z" ((uint16_t)address), \
  188. "r" ((uint16_t)data) \
  189. : "r0" \
  190. ); \
  191. }))
  192. #define __boot_page_fill_alternate(address, data)\
  193. (__extension__({ \
  194. __asm__ __volatile__ \
  195. ( \
  196. "movw r0, %3\n\t" \
  197. "sts %0, %1\n\t" \
  198. "spm\n\t" \
  199. ".word 0xffff\n\t" \
  200. "nop\n\t" \
  201. "clr r1\n\t" \
  202. : \
  203. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  204. "r" ((uint8_t)__BOOT_PAGE_FILL), \
  205. "z" ((uint16_t)address), \
  206. "r" ((uint16_t)data) \
  207. : "r0" \
  208. ); \
  209. }))
  210. #define __boot_page_fill_extended(address, data) \
  211. (__extension__({ \
  212. __asm__ __volatile__ \
  213. ( \
  214. "movw r0, %4\n\t" \
  215. "movw r30, %A3\n\t" \
  216. "sts %1, %C3\n\t" \
  217. "sts %0, %2\n\t" \
  218. "spm\n\t" \
  219. "clr r1\n\t" \
  220. : \
  221. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  222. "i" (_SFR_MEM_ADDR(RAMPZ)), \
  223. "r" ((uint8_t)__BOOT_PAGE_FILL), \
  224. "r" ((uint32_t)address), \
  225. "r" ((uint16_t)data) \
  226. : "r0", "r30", "r31" \
  227. ); \
  228. }))
  229. #define __boot_page_fill_extended_short(address, data) \
  230. (__extension__({ \
  231. __asm__ __volatile__ \
  232. ( \
  233. "movw r0, %4\n\t" \
  234. "movw r30, %A3\n\t" \
  235. "out %1, %C3\n\t" \
  236. "out %0, %2\n\t" \
  237. "spm\n\t" \
  238. "clr r1\n\t" \
  239. : \
  240. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  241. "i" (_SFR_IO_ADDR(RAMPZ)), \
  242. "r" ((uint8_t)__BOOT_PAGE_FILL), \
  243. "r" ((uint32_t)address), \
  244. "r" ((uint16_t)data) \
  245. : "r0", "r30", "r31" \
  246. ); \
  247. }))
  248. #define __boot_page_erase_short(address) \
  249. (__extension__({ \
  250. __asm__ __volatile__ \
  251. ( \
  252. "out %0, %1\n\t" \
  253. "spm\n\t" \
  254. : \
  255. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  256. "r" ((uint8_t)__BOOT_PAGE_ERASE), \
  257. "z" ((uint16_t)address) \
  258. ); \
  259. }))
  260. #define __boot_page_erase_normal(address) \
  261. (__extension__({ \
  262. __asm__ __volatile__ \
  263. ( \
  264. "sts %0, %1\n\t" \
  265. "spm\n\t" \
  266. : \
  267. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  268. "r" ((uint8_t)__BOOT_PAGE_ERASE), \
  269. "z" ((uint16_t)address) \
  270. ); \
  271. }))
  272. #define __boot_page_erase_alternate(address) \
  273. (__extension__({ \
  274. __asm__ __volatile__ \
  275. ( \
  276. "sts %0, %1\n\t" \
  277. "spm\n\t" \
  278. ".word 0xffff\n\t" \
  279. "nop\n\t" \
  280. : \
  281. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  282. "r" ((uint8_t)__BOOT_PAGE_ERASE), \
  283. "z" ((uint16_t)address) \
  284. ); \
  285. }))
  286. #define __boot_page_erase_extended(address) \
  287. (__extension__({ \
  288. __asm__ __volatile__ \
  289. ( \
  290. "movw r30, %A3\n\t" \
  291. "sts %1, %C3\n\t" \
  292. "sts %0, %2\n\t" \
  293. "spm\n\t" \
  294. : \
  295. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  296. "i" (_SFR_MEM_ADDR(RAMPZ)), \
  297. "r" ((uint8_t)__BOOT_PAGE_ERASE), \
  298. "r" ((uint32_t)address) \
  299. : "r30", "r31" \
  300. ); \
  301. }))
  302. #define __boot_page_erase_extended_short(address) \
  303. (__extension__({ \
  304. __asm__ __volatile__ \
  305. ( \
  306. "movw r30, %A3\n\t" \
  307. "out %1, %C3\n\t" \
  308. "out %0, %2\n\t" \
  309. "spm\n\t" \
  310. : \
  311. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  312. "i" (_SFR_IO_ADDR(RAMPZ)), \
  313. "r" ((uint8_t)__BOOT_PAGE_ERASE), \
  314. "r" ((uint32_t)address) \
  315. : "r30", "r31" \
  316. ); \
  317. }))
  318. #define __boot_page_write_short(address) \
  319. (__extension__({ \
  320. __asm__ __volatile__ \
  321. ( \
  322. "out %0, %1\n\t" \
  323. "spm\n\t" \
  324. : \
  325. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  326. "r" ((uint8_t)__BOOT_PAGE_WRITE), \
  327. "z" ((uint16_t)address) \
  328. ); \
  329. }))
  330. #define __boot_page_write_normal(address) \
  331. (__extension__({ \
  332. __asm__ __volatile__ \
  333. ( \
  334. "sts %0, %1\n\t" \
  335. "spm\n\t" \
  336. : \
  337. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  338. "r" ((uint8_t)__BOOT_PAGE_WRITE), \
  339. "z" ((uint16_t)address) \
  340. ); \
  341. }))
  342. #define __boot_page_write_alternate(address) \
  343. (__extension__({ \
  344. __asm__ __volatile__ \
  345. ( \
  346. "sts %0, %1\n\t" \
  347. "spm\n\t" \
  348. ".word 0xffff\n\t" \
  349. "nop\n\t" \
  350. : \
  351. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  352. "r" ((uint8_t)__BOOT_PAGE_WRITE), \
  353. "z" ((uint16_t)address) \
  354. ); \
  355. }))
  356. #define __boot_page_write_extended(address) \
  357. (__extension__({ \
  358. __asm__ __volatile__ \
  359. ( \
  360. "movw r30, %A3\n\t" \
  361. "sts %1, %C3\n\t" \
  362. "sts %0, %2\n\t" \
  363. "spm\n\t" \
  364. : \
  365. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  366. "i" (_SFR_MEM_ADDR(RAMPZ)), \
  367. "r" ((uint8_t)__BOOT_PAGE_WRITE), \
  368. "r" ((uint32_t)address) \
  369. : "r30", "r31" \
  370. ); \
  371. }))
  372. #define __boot_page_write_extended_short(address) \
  373. (__extension__({ \
  374. __asm__ __volatile__ \
  375. ( \
  376. "movw r30, %A3\n\t" \
  377. "out %1, %C3\n\t" \
  378. "out %0, %2\n\t" \
  379. "spm\n\t" \
  380. : \
  381. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  382. "i" (_SFR_IO_ADDR(RAMPZ)), \
  383. "r" ((uint8_t)__BOOT_PAGE_WRITE), \
  384. "r" ((uint32_t)address) \
  385. : "r30", "r31" \
  386. ); \
  387. }))
  388. #define __boot_rww_enable_short() \
  389. (__extension__({ \
  390. __asm__ __volatile__ \
  391. ( \
  392. "out %0, %1\n\t" \
  393. "spm\n\t" \
  394. : \
  395. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  396. "r" ((uint8_t)__BOOT_RWW_ENABLE) \
  397. ); \
  398. }))
  399. #define __boot_rww_enable() \
  400. (__extension__({ \
  401. __asm__ __volatile__ \
  402. ( \
  403. "sts %0, %1\n\t" \
  404. "spm\n\t" \
  405. : \
  406. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  407. "r" ((uint8_t)__BOOT_RWW_ENABLE) \
  408. ); \
  409. }))
  410. #define __boot_rww_enable_alternate() \
  411. (__extension__({ \
  412. __asm__ __volatile__ \
  413. ( \
  414. "sts %0, %1\n\t" \
  415. "spm\n\t" \
  416. ".word 0xffff\n\t" \
  417. "nop\n\t" \
  418. : \
  419. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  420. "r" ((uint8_t)__BOOT_RWW_ENABLE) \
  421. ); \
  422. }))
  423. /* From the mega16/mega128 data sheets (maybe others):
  424. Bits by SPM To set the Boot Loader Lock bits, write the desired data to
  425. R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
  426. after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
  427. that may prevent the Application and Boot Loader section from any
  428. software update by the MCU.
  429. If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
  430. will be programmed if an SPM instruction is executed within four cycles
  431. after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
  432. don't care during this operation, but for future compatibility it is
  433. recommended to load the Z-pointer with $0001 (same as used for reading the
  434. Lock bits). For future compatibility It is also recommended to set bits 7,
  435. 6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
  436. Lock bits the entire Flash can be read during the operation. */
  437. #define __boot_lock_bits_set_short(lock_bits) \
  438. (__extension__({ \
  439. uint8_t value = (uint8_t)(~(lock_bits)); \
  440. __asm__ __volatile__ \
  441. ( \
  442. "ldi r30, 1\n\t" \
  443. "ldi r31, 0\n\t" \
  444. "mov r0, %2\n\t" \
  445. "out %0, %1\n\t" \
  446. "spm\n\t" \
  447. : \
  448. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  449. "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
  450. "r" (value) \
  451. : "r0", "r30", "r31" \
  452. ); \
  453. }))
  454. #define __boot_lock_bits_set(lock_bits) \
  455. (__extension__({ \
  456. uint8_t value = (uint8_t)(~(lock_bits)); \
  457. __asm__ __volatile__ \
  458. ( \
  459. "ldi r30, 1\n\t" \
  460. "ldi r31, 0\n\t" \
  461. "mov r0, %2\n\t" \
  462. "sts %0, %1\n\t" \
  463. "spm\n\t" \
  464. : \
  465. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  466. "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
  467. "r" (value) \
  468. : "r0", "r30", "r31" \
  469. ); \
  470. }))
  471. #define __boot_lock_bits_set_alternate(lock_bits) \
  472. (__extension__({ \
  473. uint8_t value = (uint8_t)(~(lock_bits)); \
  474. __asm__ __volatile__ \
  475. ( \
  476. "ldi r30, 1\n\t" \
  477. "ldi r31, 0\n\t" \
  478. "mov r0, %2\n\t" \
  479. "sts %0, %1\n\t" \
  480. "spm\n\t" \
  481. ".word 0xffff\n\t" \
  482. "nop\n\t" \
  483. : \
  484. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  485. "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
  486. "r" (value) \
  487. : "r0", "r30", "r31" \
  488. ); \
  489. }))
  490. /*
  491. Reading lock and fuse bits:
  492. Similarly to writing the lock bits above, set BLBSET and SPMEN (or
  493. SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
  494. LPM instruction.
  495. Z address: contents:
  496. 0x0000 low fuse bits
  497. 0x0001 lock bits
  498. 0x0002 extended fuse bits
  499. 0x0003 high fuse bits
  500. Sounds confusing, doesn't it?
  501. Unlike the macros in pgmspace.h, no need to care for non-enhanced
  502. cores here as these old cores do not provide SPM support anyway.
  503. */
  504. /** \ingroup avr_boot
  505. \def GET_LOW_FUSE_BITS
  506. address to read the low fuse bits, using boot_lock_fuse_bits_get
  507. */
  508. #define GET_LOW_FUSE_BITS (0x0000)
  509. /** \ingroup avr_boot
  510. \def GET_LOCK_BITS
  511. address to read the lock bits, using boot_lock_fuse_bits_get
  512. */
  513. #define GET_LOCK_BITS (0x0001)
  514. /** \ingroup avr_boot
  515. \def GET_EXTENDED_FUSE_BITS
  516. address to read the extended fuse bits, using boot_lock_fuse_bits_get
  517. */
  518. #define GET_EXTENDED_FUSE_BITS (0x0002)
  519. /** \ingroup avr_boot
  520. \def GET_HIGH_FUSE_BITS
  521. address to read the high fuse bits, using boot_lock_fuse_bits_get
  522. */
  523. #define GET_HIGH_FUSE_BITS (0x0003)
  524. /** \ingroup avr_boot
  525. \def boot_lock_fuse_bits_get(address)
  526. Read the lock or fuse bits at \c address.
  527. Parameter \c address can be any of GET_LOW_FUSE_BITS,
  528. GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
  529. \note The lock and fuse bits returned are the physical values,
  530. i.e. a bit returned as 0 means the corresponding fuse or lock bit
  531. is programmed.
  532. */
  533. #define boot_lock_fuse_bits_get_short(address) \
  534. (__extension__({ \
  535. uint8_t __result; \
  536. __asm__ __volatile__ \
  537. ( \
  538. "ldi r30, %3\n\t" \
  539. "ldi r31, 0\n\t" \
  540. "out %1, %2\n\t" \
  541. "lpm %0, Z\n\t" \
  542. : "=r" (__result) \
  543. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  544. "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
  545. "M" (address) \
  546. : "r0", "r30", "r31" \
  547. ); \
  548. __result; \
  549. }))
  550. #define boot_lock_fuse_bits_get(address) \
  551. (__extension__({ \
  552. uint8_t __result; \
  553. __asm__ __volatile__ \
  554. ( \
  555. "ldi r30, %3\n\t" \
  556. "ldi r31, 0\n\t" \
  557. "sts %1, %2\n\t" \
  558. "lpm %0, Z\n\t" \
  559. : "=r" (__result) \
  560. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  561. "r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
  562. "M" (address) \
  563. : "r0", "r30", "r31" \
  564. ); \
  565. __result; \
  566. }))
  567. /** \ingroup avr_boot
  568. \def boot_signature_byte_get(address)
  569. Read the Signature Row byte at \c address. For some MCU types,
  570. this function can also retrieve the factory-stored oscillator
  571. calibration bytes.
  572. Parameter \c address can be 0-0x1f as documented by the datasheet.
  573. \note The values are MCU type dependent.
  574. */
  575. #define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
  576. #define boot_signature_byte_get_short(addr) \
  577. (__extension__({ \
  578. uint16_t __addr16 = (uint16_t)(addr); \
  579. uint8_t __result; \
  580. __asm__ __volatile__ \
  581. ( \
  582. "out %1, %2\n\t" \
  583. "lpm %0, Z" "\n\t" \
  584. : "=r" (__result) \
  585. : "i" (_SFR_IO_ADDR(__SPM_REG)), \
  586. "r" ((uint8_t) __BOOT_SIGROW_READ), \
  587. "z" (__addr16) \
  588. ); \
  589. __result; \
  590. }))
  591. #define boot_signature_byte_get(addr) \
  592. (__extension__({ \
  593. uint16_t __addr16 = (uint16_t)(addr); \
  594. uint8_t __result; \
  595. __asm__ __volatile__ \
  596. ( \
  597. "sts %1, %2\n\t" \
  598. "lpm %0, Z" "\n\t" \
  599. : "=r" (__result) \
  600. : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
  601. "r" ((uint8_t) __BOOT_SIGROW_READ), \
  602. "z" (__addr16) \
  603. ); \
  604. __result; \
  605. }))
  606. /** \ingroup avr_boot
  607. \def boot_page_fill(address, data)
  608. Fill the bootloader temporary page buffer for flash
  609. address with data word.
  610. \note The address is a byte address. The data is a word. The AVR
  611. writes data to the buffer a word at a time, but addresses the buffer
  612. per byte! So, increment your address by 2 between calls, and send 2
  613. data bytes in a word format! The LSB of the data is written to the lower
  614. address; the MSB of the data is written to the higher address.*/
  615. /** \ingroup avr_boot
  616. \def boot_page_erase(address)
  617. Erase the flash page that contains address.
  618. \note address is a byte address in flash, not a word address. */
  619. /** \ingroup avr_boot
  620. \def boot_page_write(address)
  621. Write the bootloader temporary page buffer
  622. to flash page that contains address.
  623. \note address is a byte address in flash, not a word address. */
  624. /** \ingroup avr_boot
  625. \def boot_rww_enable()
  626. Enable the Read-While-Write memory section. */
  627. /** \ingroup avr_boot
  628. \def boot_lock_bits_set(lock_bits)
  629. Set the bootloader lock bits.
  630. \param lock_bits A mask of which Boot Loader Lock Bits to set.
  631. \note In this context, a 'set bit' will be written to a zero value.
  632. Note also that only BLBxx bits can be programmed by this command.
  633. For example, to disallow the SPM instruction from writing to the Boot
  634. Loader memory section of flash, you would use this macro as such:
  635. \code
  636. boot_lock_bits_set (_BV (BLB11));
  637. \endcode
  638. \note Like any lock bits, the Boot Loader Lock Bits, once set,
  639. cannot be cleared again except by a chip erase which will in turn
  640. also erase the boot loader itself. */
  641. /* Normal versions of the macros use 16-bit addresses.
  642. Extended versions of the macros use 32-bit addresses.
  643. Alternate versions of the macros use 16-bit addresses and require special
  644. instruction sequences after LPM.
  645. FLASHEND is defined in the ioXXXX.h file.
  646. USHRT_MAX is defined in <limits.h>. */
  647. #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
  648. || defined(__AVR_ATmega323__)
  649. /* Alternate: ATmega161/163/323 and 16 bit address */
  650. #define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
  651. #define boot_page_erase(address) __boot_page_erase_alternate(address)
  652. #define boot_page_write(address) __boot_page_write_alternate(address)
  653. #define boot_rww_enable() __boot_rww_enable_alternate()
  654. #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
  655. #elif (FLASHEND > USHRT_MAX)
  656. /* Extended: >16 bit address */
  657. #define boot_page_fill(address, data) __boot_page_fill_extended_short(address, data)
  658. #define boot_page_erase(address) __boot_page_erase_extended_short(address)
  659. #define boot_page_write(address) __boot_page_write_extended_short(address)
  660. #define boot_rww_enable() __boot_rww_enable_short()
  661. #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_short(lock_bits)
  662. #else
  663. /* Normal: 16 bit address */
  664. #define boot_page_fill(address, data) __boot_page_fill_short(address, data)
  665. #define boot_page_erase(address) __boot_page_erase_short(address)
  666. #define boot_page_write(address) __boot_page_write_short(address)
  667. #define boot_rww_enable() __boot_rww_enable_short()
  668. #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_short(lock_bits)
  669. #endif
  670. /** \ingroup avr_boot
  671. Same as boot_page_fill() except it waits for eeprom and spm operations to
  672. complete before filling the page. */
  673. #define boot_page_fill_safe(address, data) \
  674. do { \
  675. boot_spm_busy_wait(); \
  676. eeprom_busy_wait(); \
  677. boot_page_fill(address, data); \
  678. } while (0)
  679. /** \ingroup avr_boot
  680. Same as boot_page_erase() except it waits for eeprom and spm operations to
  681. complete before erasing the page. */
  682. #define boot_page_erase_safe(address) \
  683. do { \
  684. boot_spm_busy_wait(); \
  685. eeprom_busy_wait(); \
  686. boot_page_erase (address); \
  687. } while (0)
  688. /** \ingroup avr_boot
  689. Same as boot_page_write() except it waits for eeprom and spm operations to
  690. complete before writing the page. */
  691. #define boot_page_write_safe(address) \
  692. do { \
  693. boot_spm_busy_wait(); \
  694. eeprom_busy_wait(); \
  695. boot_page_write (address); \
  696. } while (0)
  697. /** \ingroup avr_boot
  698. Same as boot_rww_enable() except waits for eeprom and spm operations to
  699. complete before enabling the RWW mameory. */
  700. #define boot_rww_enable_safe() \
  701. do { \
  702. boot_spm_busy_wait(); \
  703. eeprom_busy_wait(); \
  704. boot_rww_enable(); \
  705. } while (0)
  706. /** \ingroup avr_boot
  707. Same as boot_lock_bits_set() except waits for eeprom and spm operations to
  708. complete before setting the lock bits. */
  709. #define boot_lock_bits_set_safe(lock_bits) \
  710. do { \
  711. boot_spm_busy_wait(); \
  712. eeprom_busy_wait(); \
  713. boot_lock_bits_set (lock_bits); \
  714. } while (0)
  715. #endif /* _AVR_BOOT_H_ */