driver-avalon.c 45 KB

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  1. /*
  2. * Copyright 2013-2015 Con Kolivas <kernel@kolivas.org>
  3. * Copyright 2012-2013 Xiangfu <xiangfu@openmobilefree.com>
  4. * Copyright 2012 Luke Dashjr
  5. * Copyright 2012 Andrew Smith
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 3 of the License, or (at your option)
  10. * any later version. See COPYING for more details.
  11. */
  12. #include "config.h"
  13. #include <limits.h>
  14. #include <pthread.h>
  15. #include <stdio.h>
  16. #include <sys/time.h>
  17. #include <sys/types.h>
  18. #include <ctype.h>
  19. #include <dirent.h>
  20. #include <unistd.h>
  21. #include <time.h>
  22. #ifndef WIN32
  23. #include <sys/select.h>
  24. #include <termios.h>
  25. #include <sys/stat.h>
  26. #include <fcntl.h>
  27. #ifndef O_CLOEXEC
  28. #define O_CLOEXEC 0
  29. #endif
  30. #else
  31. #include "compat.h"
  32. #include <io.h>
  33. #endif
  34. #include "elist.h"
  35. #include "miner.h"
  36. #include "usbutils.h"
  37. #include "driver-avalon.h"
  38. #include "hexdump.c"
  39. #include "util.h"
  40. int opt_avalon_temp = AVALON_TEMP_TARGET;
  41. int opt_avalon_overheat = AVALON_TEMP_OVERHEAT;
  42. int opt_avalon_fan_min = AVALON_DEFAULT_FAN_MIN_PWM;
  43. int opt_avalon_fan_max = AVALON_DEFAULT_FAN_MAX_PWM;
  44. int opt_avalon_freq_min = AVALON_MIN_FREQUENCY;
  45. int opt_avalon_freq_max = AVALON_MAX_FREQUENCY;
  46. int opt_bitburner_core_voltage = BITBURNER_DEFAULT_CORE_VOLTAGE;
  47. int opt_bitburner_fury_core_voltage = BITBURNER_FURY_DEFAULT_CORE_VOLTAGE;
  48. bool opt_avalon_auto;
  49. static int option_offset = -1;
  50. static int bbf_option_offset = -1;
  51. static int avalon_init_task(struct avalon_task *at,
  52. uint8_t reset, uint8_t ff, uint8_t fan,
  53. uint8_t timeout, uint8_t asic_num,
  54. uint8_t miner_num, uint8_t nonce_elf,
  55. uint8_t gate_miner, int frequency, int asic)
  56. {
  57. uint16_t *lefreq16;
  58. uint8_t *buf;
  59. static bool first = true;
  60. if (unlikely(!at))
  61. return -1;
  62. if (unlikely(timeout <= 0 || asic_num <= 0 || miner_num <= 0))
  63. return -1;
  64. memset(at, 0, sizeof(struct avalon_task));
  65. if (unlikely(reset)) {
  66. at->reset = 1;
  67. at->fan_eft = 1;
  68. at->timer_eft = 1;
  69. first = true;
  70. }
  71. at->flush_fifo = (ff ? 1 : 0);
  72. at->fan_eft = (fan ? 1 : 0);
  73. if (unlikely(first && !at->reset)) {
  74. at->fan_eft = 1;
  75. at->timer_eft = 1;
  76. first = false;
  77. }
  78. at->fan_pwm_data = (fan ? fan : AVALON_DEFAULT_FAN_MAX_PWM);
  79. at->timeout_data = timeout;
  80. at->asic_num = asic_num;
  81. at->miner_num = miner_num;
  82. at->nonce_elf = nonce_elf;
  83. at->gate_miner_elf = 1;
  84. at->asic_pll = 1;
  85. if (unlikely(gate_miner)) {
  86. at-> gate_miner = 1;
  87. at->asic_pll = 0;
  88. }
  89. buf = (uint8_t *)at;
  90. buf[5] = 0x00;
  91. buf[8] = 0x74;
  92. buf[9] = 0x01;
  93. buf[10] = 0x00;
  94. buf[11] = 0x00;
  95. /* With 55nm, this is the real clock in Mhz, 1Mhz means 2Mhs */
  96. lefreq16 = (uint16_t *)&buf[6];
  97. if (asic == AVALON_A3256)
  98. frequency *= 8;
  99. else
  100. frequency = frequency * 32 / 50 + 0x7FE0;
  101. *lefreq16 = htole16(frequency);
  102. return 0;
  103. }
  104. static inline void avalon_create_task(struct avalon_task *at,
  105. struct work *work)
  106. {
  107. memcpy(at->midstate, work->midstate, 32);
  108. memcpy(at->data, work->data + 64, 12);
  109. }
  110. static int avalon_write(struct cgpu_info *avalon, char *buf, ssize_t len, int ep)
  111. {
  112. int err, amount;
  113. err = usb_write(avalon, buf, len, &amount, ep);
  114. applog(LOG_DEBUG, "%s%i: usb_write got err %d", avalon->drv->name,
  115. avalon->device_id, err);
  116. if (unlikely(err != 0)) {
  117. applog(LOG_WARNING, "usb_write error on avalon_write");
  118. return AVA_SEND_ERROR;
  119. }
  120. if (amount != len) {
  121. applog(LOG_WARNING, "usb_write length mismatch on avalon_write");
  122. return AVA_SEND_ERROR;
  123. }
  124. return AVA_SEND_OK;
  125. }
  126. static int avalon_send_task(const struct avalon_task *at, struct cgpu_info *avalon,
  127. struct avalon_info *info)
  128. {
  129. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  130. int delay, ret, i, ep = C_AVALON_TASK;
  131. uint32_t nonce_range;
  132. size_t nr_len;
  133. if (at->nonce_elf)
  134. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  135. else
  136. nr_len = AVALON_WRITE_SIZE;
  137. memcpy(buf, at, AVALON_WRITE_SIZE);
  138. if (at->nonce_elf) {
  139. nonce_range = (uint32_t)0xffffffff / at->asic_num;
  140. for (i = 0; i < at->asic_num; i++) {
  141. buf[AVALON_WRITE_SIZE + (i * 4) + 3] =
  142. (i * nonce_range & 0xff000000) >> 24;
  143. buf[AVALON_WRITE_SIZE + (i * 4) + 2] =
  144. (i * nonce_range & 0x00ff0000) >> 16;
  145. buf[AVALON_WRITE_SIZE + (i * 4) + 1] =
  146. (i * nonce_range & 0x0000ff00) >> 8;
  147. buf[AVALON_WRITE_SIZE + (i * 4) + 0] =
  148. (i * nonce_range & 0x000000ff) >> 0;
  149. }
  150. }
  151. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  152. uint8_t tt = 0;
  153. tt = (buf[0] & 0x0f) << 4;
  154. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  155. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  156. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  157. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  158. buf[0] = tt;
  159. tt = (buf[4] & 0x0f) << 4;
  160. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  161. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  162. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  163. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  164. buf[4] = tt;
  165. #endif
  166. delay = nr_len * 10 * 1000000;
  167. delay = delay / info->baud;
  168. delay += 4000;
  169. if (at->reset) {
  170. ep = C_AVALON_RESET;
  171. nr_len = 1;
  172. }
  173. if (opt_debug) {
  174. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  175. hexdump(buf, nr_len);
  176. }
  177. /* Sleep from the last time we sent data */
  178. cgsleep_us_r(&info->cgsent, info->send_delay);
  179. cgsleep_prepare_r(&info->cgsent);
  180. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  181. applog(LOG_DEBUG, "Avalon: Sent: Buffer delay: %dus", info->send_delay);
  182. info->send_delay = delay;
  183. return ret;
  184. }
  185. static int bitburner_send_task(const struct avalon_task *at, struct cgpu_info *avalon)
  186. {
  187. uint8_t buf[AVALON_WRITE_SIZE + 4 * AVALON_DEFAULT_ASIC_NUM];
  188. int ret, ep = C_AVALON_TASK;
  189. cgtimer_t ts_start;
  190. size_t nr_len;
  191. if (at->nonce_elf)
  192. nr_len = AVALON_WRITE_SIZE + 4 * at->asic_num;
  193. else
  194. nr_len = AVALON_WRITE_SIZE;
  195. memset(buf, 0, nr_len);
  196. memcpy(buf, at, AVALON_WRITE_SIZE);
  197. #if defined(__BIG_ENDIAN__) || defined(MIPSEB)
  198. uint8_t tt = 0;
  199. tt = (buf[0] & 0x0f) << 4;
  200. tt |= ((buf[0] & 0x10) ? (1 << 3) : 0);
  201. tt |= ((buf[0] & 0x20) ? (1 << 2) : 0);
  202. tt |= ((buf[0] & 0x40) ? (1 << 1) : 0);
  203. tt |= ((buf[0] & 0x80) ? (1 << 0) : 0);
  204. buf[0] = tt;
  205. tt = (buf[4] & 0x0f) << 4;
  206. tt |= ((buf[4] & 0x10) ? (1 << 3) : 0);
  207. tt |= ((buf[4] & 0x20) ? (1 << 2) : 0);
  208. tt |= ((buf[4] & 0x40) ? (1 << 1) : 0);
  209. tt |= ((buf[4] & 0x80) ? (1 << 0) : 0);
  210. buf[4] = tt;
  211. #endif
  212. if (at->reset) {
  213. ep = C_AVALON_RESET;
  214. nr_len = 1;
  215. }
  216. if (opt_debug) {
  217. applog(LOG_DEBUG, "Avalon: Sent(%u):", (unsigned int)nr_len);
  218. hexdump(buf, nr_len);
  219. }
  220. cgsleep_prepare_r(&ts_start);
  221. ret = avalon_write(avalon, (char *)buf, nr_len, ep);
  222. cgsleep_us_r(&ts_start, 3000); // 3 ms = 333 tasks per second, or 1.4 TH/s
  223. return ret;
  224. }
  225. static bool avalon_decode_nonce(struct thr_info *thr, struct cgpu_info *avalon,
  226. struct avalon_info *info, struct avalon_result *ar,
  227. struct work *work)
  228. {
  229. uint32_t nonce;
  230. info = avalon->device_data;
  231. info->matching_work[work->subid]++;
  232. nonce = htole32(ar->nonce);
  233. if (info->asic == AVALON_A3255)
  234. nonce -= 0xc0;
  235. applog(LOG_DEBUG, "Avalon: nonce = %0x08x", nonce);
  236. return submit_nonce(thr, work, nonce);
  237. }
  238. /* Wait until the ftdi chip returns a CTS saying we can send more data. */
  239. static void wait_avalon_ready(struct cgpu_info *avalon)
  240. {
  241. while (avalon_buffer_full(avalon)) {
  242. cgsleep_ms(40);
  243. }
  244. }
  245. static int avalon_read(struct cgpu_info *avalon, char *buf, size_t bufsize, int ep)
  246. {
  247. size_t total = 0, readsize = bufsize + 2;
  248. char readbuf[AVALON_READBUF_SIZE];
  249. int err, amount, ofs = 2, cp;
  250. err = usb_read_once(avalon, readbuf, readsize, &amount, ep);
  251. applog(LOG_DEBUG, "%s%i: Get avalon read got err %d",
  252. avalon->drv->name, avalon->device_id, err);
  253. if (err && err != LIBUSB_ERROR_TIMEOUT)
  254. return err;
  255. if (amount < 2)
  256. goto out;
  257. /* The first 2 of every 64 bytes are status on FTDIRL */
  258. while (amount > 2) {
  259. cp = amount - 2;
  260. if (cp > 62)
  261. cp = 62;
  262. memcpy(&buf[total], &readbuf[ofs], cp);
  263. total += cp;
  264. amount -= cp + 2;
  265. ofs += 64;
  266. }
  267. out:
  268. return total;
  269. }
  270. static int avalon_reset(struct cgpu_info *avalon, bool initial)
  271. {
  272. struct avalon_result ar;
  273. int ret, i, spare;
  274. struct avalon_task at;
  275. uint8_t *buf, *tmp;
  276. struct timespec p;
  277. struct avalon_info *info = avalon->device_data;
  278. /* Send reset, then check for result */
  279. avalon_init_task(&at, 1, 0,
  280. AVALON_DEFAULT_FAN_MAX_PWM,
  281. AVALON_DEFAULT_TIMEOUT,
  282. AVALON_DEFAULT_ASIC_NUM,
  283. AVALON_DEFAULT_MINER_NUM,
  284. 0, 0,
  285. AVALON_DEFAULT_FREQUENCY,
  286. AVALON_A3256);
  287. wait_avalon_ready(avalon);
  288. ret = avalon_send_task(&at, avalon, info);
  289. if (unlikely(ret == AVA_SEND_ERROR))
  290. return -1;
  291. if (!initial) {
  292. applog(LOG_ERR, "%s%d reset sequence sent", avalon->drv->name, avalon->device_id);
  293. return 0;
  294. }
  295. ret = avalon_read(avalon, (char *)&ar, AVALON_READ_SIZE, C_GET_AVALON_RESET);
  296. /* What do these sleeps do?? */
  297. p.tv_sec = 0;
  298. p.tv_nsec = AVALON_RESET_PITCH;
  299. nanosleep(&p, NULL);
  300. /* Look for the first occurrence of 0xAA, the reset response should be:
  301. * AA 55 AA 55 00 00 00 00 00 00 */
  302. spare = ret - 10;
  303. buf = tmp = (uint8_t *)&ar;
  304. if (opt_debug) {
  305. applog(LOG_DEBUG, "%s%d reset: get:", avalon->drv->name, avalon->device_id);
  306. hexdump(tmp, AVALON_READ_SIZE);
  307. }
  308. for (i = 0; i <= spare; i++) {
  309. buf = &tmp[i];
  310. if (buf[0] == 0xAA)
  311. break;
  312. }
  313. i = 0;
  314. if (buf[0] == 0xAA && buf[1] == 0x55 &&
  315. buf[2] == 0xAA && buf[3] == 0x55) {
  316. for (i = 4; i < 11; i++)
  317. if (buf[i] != 0)
  318. break;
  319. }
  320. if (i != 11) {
  321. applog(LOG_ERR, "%s%d: Reset failed! not an Avalon?"
  322. " (%d: %02x %02x %02x %02x)", avalon->drv->name, avalon->device_id,
  323. i, buf[0], buf[1], buf[2], buf[3]);
  324. /* FIXME: return 1; */
  325. } else {
  326. /* buf[44]: minor
  327. * buf[45]: day
  328. * buf[46]: year,month, d6: 201306
  329. */
  330. info->ctlr_ver = ((buf[46] >> 4) + 2000) * 1000000 +
  331. (buf[46] & 0x0f) * 10000 +
  332. buf[45] * 100 + buf[44];
  333. applog(LOG_WARNING, "%s%d: Reset succeeded (Controller version: %d)",
  334. avalon->drv->name, avalon->device_id, info->ctlr_ver);
  335. }
  336. return 0;
  337. }
  338. static int avalon_calc_timeout(int frequency)
  339. {
  340. return AVALON_TIMEOUT_FACTOR / frequency;
  341. }
  342. static bool get_options(int this_option_offset, int *baud, int *miner_count,
  343. int *asic_count, int *timeout, int *frequency, int *asic,
  344. char *options)
  345. {
  346. char buf[BUFSIZ+1];
  347. char *ptr, *comma, *colon, *colon2, *colon3, *colon4, *colon5;
  348. bool timeout_default;
  349. size_t max;
  350. int i, tmp;
  351. if (options == NULL)
  352. buf[0] = '\0';
  353. else {
  354. ptr = options;
  355. for (i = 0; i < this_option_offset; i++) {
  356. comma = strchr(ptr, ',');
  357. if (comma == NULL)
  358. break;
  359. ptr = comma + 1;
  360. }
  361. comma = strchr(ptr, ',');
  362. if (comma == NULL)
  363. max = strlen(ptr);
  364. else
  365. max = comma - ptr;
  366. if (max > BUFSIZ)
  367. max = BUFSIZ;
  368. strncpy(buf, ptr, max);
  369. buf[max] = '\0';
  370. }
  371. if (!(*buf))
  372. return false;
  373. colon = strchr(buf, ':');
  374. if (colon)
  375. *(colon++) = '\0';
  376. tmp = atoi(buf);
  377. switch (tmp) {
  378. case 115200:
  379. *baud = 115200;
  380. break;
  381. case 57600:
  382. *baud = 57600;
  383. break;
  384. case 38400:
  385. *baud = 38400;
  386. break;
  387. case 19200:
  388. *baud = 19200;
  389. break;
  390. default:
  391. quit(1, "Invalid avalon-options for baud (%s) "
  392. "must be 115200, 57600, 38400 or 19200", buf);
  393. }
  394. if (colon && *colon) {
  395. colon2 = strchr(colon, ':');
  396. if (colon2)
  397. *(colon2++) = '\0';
  398. if (*colon) {
  399. tmp = atoi(colon);
  400. if (tmp > 0 && tmp <= AVALON_MAX_MINER_NUM) {
  401. *miner_count = tmp;
  402. } else {
  403. quit(1, "Invalid avalon-options for "
  404. "miner_count (%s) must be 1 ~ %d",
  405. colon, AVALON_MAX_MINER_NUM);
  406. }
  407. }
  408. if (colon2 && *colon2) {
  409. colon3 = strchr(colon2, ':');
  410. if (colon3)
  411. *(colon3++) = '\0';
  412. tmp = atoi(colon2);
  413. if (tmp > 0 && tmp <= AVALON_DEFAULT_ASIC_NUM)
  414. *asic_count = tmp;
  415. else {
  416. quit(1, "Invalid avalon-options for "
  417. "asic_count (%s) must be 1 ~ %d",
  418. colon2, AVALON_DEFAULT_ASIC_NUM);
  419. }
  420. timeout_default = false;
  421. if (colon3 && *colon3) {
  422. colon4 = strchr(colon3, ':');
  423. if (colon4)
  424. *(colon4++) = '\0';
  425. if (tolower(*colon3) == 'd')
  426. timeout_default = true;
  427. else {
  428. tmp = atoi(colon3);
  429. if (tmp > 0 && tmp <= 0xff)
  430. *timeout = tmp;
  431. else {
  432. quit(1, "Invalid avalon-options for "
  433. "timeout (%s) must be 1 ~ %d",
  434. colon3, 0xff);
  435. }
  436. }
  437. if (colon4 && *colon4) {
  438. colon5 = strchr(colon4, ':');
  439. if (colon5)
  440. *(colon5++) = '\0';
  441. tmp = atoi(colon4);
  442. if (tmp < AVALON_MIN_FREQUENCY || tmp > AVALON_MAX_FREQUENCY) {
  443. quit(1, "Invalid avalon-options for frequency, must be %d <= frequency <= %d",
  444. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  445. }
  446. *frequency = tmp;
  447. if (timeout_default)
  448. *timeout = avalon_calc_timeout(*frequency);
  449. if (colon5 && *colon5) {
  450. tmp = atoi(colon5);
  451. if (tmp != AVALON_A3256 && tmp != AVALON_A3255)
  452. quit(1, "Invalid avalon-options for asic, must be 110 or 55");
  453. *asic = tmp;
  454. }
  455. }
  456. }
  457. }
  458. }
  459. return true;
  460. }
  461. char *set_avalon_fan(char *arg)
  462. {
  463. int val1, val2, ret;
  464. ret = sscanf(arg, "%d-%d", &val1, &val2);
  465. if (ret < 1)
  466. return "No values passed to avalon-fan";
  467. if (ret == 1)
  468. val2 = val1;
  469. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  470. return "Invalid value passed to avalon-fan";
  471. opt_avalon_fan_min = val1 * AVALON_PWM_MAX / 100;
  472. opt_avalon_fan_max = val2 * AVALON_PWM_MAX / 100;
  473. return NULL;
  474. }
  475. char *set_avalon_freq(char *arg)
  476. {
  477. int val1, val2, ret;
  478. ret = sscanf(arg, "%d-%d", &val1, &val2);
  479. if (ret < 1)
  480. return "No values passed to avalon-freq";
  481. if (ret == 1)
  482. val2 = val1;
  483. if (val1 < AVALON_MIN_FREQUENCY || val1 > AVALON_MAX_FREQUENCY ||
  484. val2 < AVALON_MIN_FREQUENCY || val2 > AVALON_MAX_FREQUENCY ||
  485. val2 < val1)
  486. return "Invalid value passed to avalon-freq";
  487. opt_avalon_freq_min = val1;
  488. opt_avalon_freq_max = val2;
  489. return NULL;
  490. }
  491. static void avalon_idle(struct cgpu_info *avalon, struct avalon_info *info)
  492. {
  493. int i;
  494. wait_avalon_ready(avalon);
  495. /* Send idle to all miners */
  496. for (i = 0; i < info->miner_count; i++) {
  497. struct avalon_task at;
  498. if (unlikely(avalon_buffer_full(avalon)))
  499. break;
  500. info->idle++;
  501. avalon_init_task(&at, 0, 0, info->fan_pwm, info->timeout,
  502. info->asic_count, info->miner_count, 1, 1,
  503. info->frequency, info->asic);
  504. if (avalon_send_task(&at, avalon, info) == AVA_SEND_ERROR)
  505. break;
  506. }
  507. applog(LOG_WARNING, "%s%i: Idling %d miners", avalon->drv->name, avalon->device_id, i);
  508. wait_avalon_ready(avalon);
  509. }
  510. static void avalon_initialise(struct cgpu_info *avalon)
  511. {
  512. int err, interface;
  513. if (avalon->usbinfo.nodev)
  514. return;
  515. interface = usb_interface(avalon);
  516. // Reset
  517. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_RESET,
  518. FTDI_VALUE_RESET, interface, C_RESET);
  519. applog(LOG_DEBUG, "%s%i: reset got err %d",
  520. avalon->drv->name, avalon->device_id, err);
  521. if (avalon->usbinfo.nodev)
  522. return;
  523. // Set latency
  524. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_LATENCY,
  525. AVALON_LATENCY, interface, C_LATENCY);
  526. applog(LOG_DEBUG, "%s%i: latency got err %d",
  527. avalon->drv->name, avalon->device_id, err);
  528. if (avalon->usbinfo.nodev)
  529. return;
  530. // Set data
  531. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_DATA,
  532. FTDI_VALUE_DATA_AVA, interface, C_SETDATA);
  533. applog(LOG_DEBUG, "%s%i: data got err %d",
  534. avalon->drv->name, avalon->device_id, err);
  535. if (avalon->usbinfo.nodev)
  536. return;
  537. // Set the baud
  538. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_BAUD, FTDI_VALUE_BAUD_AVA,
  539. (FTDI_INDEX_BAUD_AVA & 0xff00) | interface,
  540. C_SETBAUD);
  541. applog(LOG_DEBUG, "%s%i: setbaud got err %d",
  542. avalon->drv->name, avalon->device_id, err);
  543. if (avalon->usbinfo.nodev)
  544. return;
  545. // Set Modem Control
  546. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  547. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  548. applog(LOG_DEBUG, "%s%i: setmodemctrl got err %d",
  549. avalon->drv->name, avalon->device_id, err);
  550. if (avalon->usbinfo.nodev)
  551. return;
  552. // Set Flow Control
  553. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  554. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  555. applog(LOG_DEBUG, "%s%i: setflowctrl got err %d",
  556. avalon->drv->name, avalon->device_id, err);
  557. if (avalon->usbinfo.nodev)
  558. return;
  559. /* Avalon repeats the following */
  560. // Set Modem Control
  561. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_MODEM,
  562. FTDI_VALUE_MODEM, interface, C_SETMODEM);
  563. applog(LOG_DEBUG, "%s%i: setmodemctrl 2 got err %d",
  564. avalon->drv->name, avalon->device_id, err);
  565. if (avalon->usbinfo.nodev)
  566. return;
  567. // Set Flow Control
  568. err = usb_transfer(avalon, FTDI_TYPE_OUT, FTDI_REQUEST_FLOW,
  569. FTDI_VALUE_FLOW, interface, C_SETFLOW);
  570. applog(LOG_DEBUG, "%s%i: setflowctrl 2 got err %d",
  571. avalon->drv->name, avalon->device_id, err);
  572. }
  573. static bool is_bitburner(struct cgpu_info *avalon)
  574. {
  575. enum sub_ident ident;
  576. ident = usb_ident(avalon);
  577. return ident == IDENT_BTB || ident == IDENT_BBF;
  578. }
  579. static bool bitburner_set_core_voltage(struct cgpu_info *avalon, int core_voltage)
  580. {
  581. uint8_t buf[2];
  582. int err;
  583. if (is_bitburner(avalon)) {
  584. buf[0] = (uint8_t)core_voltage;
  585. buf[1] = (uint8_t)(core_voltage >> 8);
  586. err = usb_transfer_data(avalon, FTDI_TYPE_OUT, BITBURNER_REQUEST,
  587. BITBURNER_VALUE, BITBURNER_INDEX_SET_VOLTAGE,
  588. (uint32_t *)buf, sizeof(buf), C_BB_SET_VOLTAGE);
  589. if (unlikely(err < 0)) {
  590. applog(LOG_ERR, "%s%i: SetCoreVoltage failed: err = %d",
  591. avalon->drv->name, avalon->device_id, err);
  592. return false;
  593. } else {
  594. applog(LOG_WARNING, "%s%i: Core voltage set to %d millivolts",
  595. avalon->drv->name, avalon->device_id,
  596. core_voltage);
  597. }
  598. return true;
  599. }
  600. return false;
  601. }
  602. static int bitburner_get_core_voltage(struct cgpu_info *avalon)
  603. {
  604. uint8_t buf[2];
  605. int err;
  606. int amount;
  607. if (is_bitburner(avalon)) {
  608. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  609. BITBURNER_VALUE, BITBURNER_INDEX_GET_VOLTAGE,
  610. (char *)buf, sizeof(buf), &amount,
  611. C_BB_GET_VOLTAGE);
  612. if (unlikely(err != 0 || amount != 2)) {
  613. applog(LOG_ERR, "%s%i: GetCoreVoltage failed: err = %d, amount = %d",
  614. avalon->drv->name, avalon->device_id, err, amount);
  615. return 0;
  616. } else {
  617. return (int)(buf[0] + ((unsigned int)buf[1] << 8));
  618. }
  619. } else {
  620. return 0;
  621. }
  622. }
  623. static void bitburner_get_version(struct cgpu_info *avalon)
  624. {
  625. struct avalon_info *info = avalon->device_data;
  626. uint8_t buf[3];
  627. int err;
  628. int amount;
  629. err = usb_transfer_read(avalon, FTDI_TYPE_IN, BITBURNER_REQUEST,
  630. BITBURNER_VALUE, BITBURNER_INDEX_GET_VERSION,
  631. (char *)buf, sizeof(buf), &amount,
  632. C_GETVERSION);
  633. if (unlikely(err != 0 || amount != sizeof(buf))) {
  634. applog(LOG_DEBUG, "%s%i: GetVersion failed: err=%d, amt=%d assuming %d.%d.%d",
  635. avalon->drv->name, avalon->device_id, err, amount,
  636. BITBURNER_VERSION1, BITBURNER_VERSION2, BITBURNER_VERSION3);
  637. info->version1 = BITBURNER_VERSION1;
  638. info->version2 = BITBURNER_VERSION2;
  639. info->version3 = BITBURNER_VERSION3;
  640. } else {
  641. info->version1 = buf[0];
  642. info->version2 = buf[1];
  643. info->version3 = buf[2];
  644. }
  645. }
  646. static struct cgpu_info *avalon_detect_one(libusb_device *dev, struct usb_find_devices *found)
  647. {
  648. int baud, miner_count, asic_count, timeout, frequency, asic;
  649. int this_option_offset;
  650. struct avalon_info *info;
  651. struct cgpu_info *avalon;
  652. bool configured;
  653. int ret;
  654. avalon = usb_alloc_cgpu(&avalon_drv, AVALON_MINER_THREADS);
  655. baud = AVALON_IO_SPEED;
  656. miner_count = AVALON_DEFAULT_MINER_NUM;
  657. asic_count = AVALON_DEFAULT_ASIC_NUM;
  658. timeout = AVALON_DEFAULT_TIMEOUT;
  659. frequency = AVALON_DEFAULT_FREQUENCY;
  660. asic = AVALON_A3256;
  661. if (!usb_init(avalon, dev, found))
  662. goto shin;
  663. this_option_offset = usb_ident(avalon) == IDENT_BBF ? ++bbf_option_offset : ++option_offset;
  664. configured = get_options(this_option_offset, &baud, &miner_count,
  665. &asic_count, &timeout, &frequency, &asic,
  666. (usb_ident(avalon) == IDENT_BBF && opt_bitburner_fury_options != NULL) ? opt_bitburner_fury_options : opt_avalon_options);
  667. /* Even though this is an FTDI type chip, we want to do the parsing
  668. * all ourselves so set it to std usb type */
  669. avalon->usbdev->usb_type = USB_TYPE_STD;
  670. /* We have a real Avalon! */
  671. avalon_initialise(avalon);
  672. avalon->device_data = calloc(sizeof(struct avalon_info), 1);
  673. if (unlikely(!(avalon->device_data)))
  674. quit(1, "Failed to calloc avalon_info data");
  675. info = avalon->device_data;
  676. if (configured) {
  677. info->asic = asic;
  678. info->baud = baud;
  679. info->miner_count = miner_count;
  680. info->asic_count = asic_count;
  681. info->timeout = timeout;
  682. info->frequency = frequency;
  683. } else {
  684. info->asic = AVALON_A3256;
  685. info->baud = AVALON_IO_SPEED;
  686. info->asic_count = AVALON_DEFAULT_ASIC_NUM;
  687. switch (usb_ident(avalon)) {
  688. case IDENT_BBF:
  689. info->miner_count = BITBURNER_FURY_DEFAULT_MINER_NUM;
  690. info->timeout = BITBURNER_FURY_DEFAULT_TIMEOUT;
  691. info->frequency = BITBURNER_FURY_DEFAULT_FREQUENCY;
  692. break;
  693. default:
  694. info->miner_count = AVALON_DEFAULT_MINER_NUM;
  695. info->timeout = AVALON_DEFAULT_TIMEOUT;
  696. info->frequency = AVALON_DEFAULT_FREQUENCY;
  697. }
  698. }
  699. if (info->asic == AVALON_A3255)
  700. info->increment = info->decrement = 50;
  701. else {
  702. info->increment = 2;
  703. info->decrement = 1;
  704. }
  705. info->fan_pwm = AVALON_DEFAULT_FAN_MIN_PWM;
  706. /* This is for check the temp/fan every 3~4s */
  707. info->temp_history_count =
  708. (4 / (float)((float)info->timeout * (AVALON_A3256 / info->asic) * ((float)1.67/0x32))) + 1;
  709. if (info->temp_history_count <= 0)
  710. info->temp_history_count = 1;
  711. info->temp_history_index = 0;
  712. info->temp_sum = 0;
  713. info->temp_old = 0;
  714. if (!add_cgpu(avalon))
  715. goto unshin;
  716. ret = avalon_reset(avalon, true);
  717. if (ret && !configured)
  718. goto unshin;
  719. update_usb_stats(avalon);
  720. avalon_idle(avalon, info);
  721. applog(LOG_DEBUG, "Avalon Detected: %s "
  722. "(miner_count=%d asic_count=%d timeout=%d frequency=%d chip=%d)",
  723. avalon->device_path, info->miner_count, info->asic_count, info->timeout,
  724. info->frequency, info->asic);
  725. if (usb_ident(avalon) == IDENT_BTB) {
  726. if (opt_bitburner_core_voltage < BITBURNER_MIN_COREMV ||
  727. opt_bitburner_core_voltage > BITBURNER_MAX_COREMV) {
  728. quit(1, "Invalid bitburner-voltage %d must be %dmv - %dmv",
  729. opt_bitburner_core_voltage,
  730. BITBURNER_MIN_COREMV,
  731. BITBURNER_MAX_COREMV);
  732. } else
  733. bitburner_set_core_voltage(avalon, opt_bitburner_core_voltage);
  734. } else if (usb_ident(avalon) == IDENT_BBF) {
  735. if (opt_bitburner_fury_core_voltage < BITBURNER_FURY_MIN_COREMV ||
  736. opt_bitburner_fury_core_voltage > BITBURNER_FURY_MAX_COREMV) {
  737. quit(1, "Invalid bitburner-fury-voltage %d must be %dmv - %dmv",
  738. opt_bitburner_fury_core_voltage,
  739. BITBURNER_FURY_MIN_COREMV,
  740. BITBURNER_FURY_MAX_COREMV);
  741. } else
  742. bitburner_set_core_voltage(avalon, opt_bitburner_fury_core_voltage);
  743. }
  744. if (is_bitburner(avalon)) {
  745. bitburner_get_version(avalon);
  746. }
  747. return avalon;
  748. unshin:
  749. usb_uninit(avalon);
  750. shin:
  751. free(avalon->device_data);
  752. avalon->device_data = NULL;
  753. avalon = usb_free_cgpu(avalon);
  754. return NULL;
  755. }
  756. static void avalon_detect(bool __maybe_unused hotplug)
  757. {
  758. usb_detect(&avalon_drv, avalon_detect_one);
  759. }
  760. static void avalon_init(struct cgpu_info *avalon)
  761. {
  762. applog(LOG_INFO, "Avalon: Opened on %s", avalon->device_path);
  763. }
  764. static struct work *avalon_valid_result(struct cgpu_info *avalon, struct avalon_result *ar)
  765. {
  766. return clone_queued_work_bymidstate(avalon, (char *)ar->midstate, 32,
  767. (char *)ar->data, 64, 12);
  768. }
  769. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  770. struct avalon_result *ar);
  771. static void avalon_inc_nvw(struct avalon_info *info, struct thr_info *thr)
  772. {
  773. applog(LOG_INFO, "%s%d: No matching work - HW error",
  774. thr->cgpu->drv->name, thr->cgpu->device_id);
  775. inc_hw_errors(thr);
  776. info->no_matching_work++;
  777. }
  778. static void avalon_parse_results(struct cgpu_info *avalon, struct avalon_info *info,
  779. struct thr_info *thr, char *buf, int *offset)
  780. {
  781. int i, spare = *offset - AVALON_READ_SIZE;
  782. bool found = false;
  783. for (i = 0; i <= spare; i++) {
  784. struct avalon_result *ar;
  785. struct work *work;
  786. ar = (struct avalon_result *)&buf[i];
  787. work = avalon_valid_result(avalon, ar);
  788. if (work) {
  789. bool gettemp = false;
  790. found = true;
  791. if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
  792. mutex_lock(&info->lock);
  793. if (!info->nonces++)
  794. gettemp = true;
  795. info->auto_nonces++;
  796. mutex_unlock(&info->lock);
  797. } else if (opt_avalon_auto) {
  798. mutex_lock(&info->lock);
  799. info->auto_hw++;
  800. mutex_unlock(&info->lock);
  801. }
  802. free_work(work);
  803. if (gettemp)
  804. avalon_update_temps(avalon, info, ar);
  805. break;
  806. }
  807. }
  808. if (!found) {
  809. spare = *offset - AVALON_READ_SIZE;
  810. /* We are buffering and haven't accumulated one more corrupt
  811. * work result. */
  812. if (spare < (int)AVALON_READ_SIZE)
  813. return;
  814. avalon_inc_nvw(info, thr);
  815. } else {
  816. spare = AVALON_READ_SIZE + i;
  817. if (i) {
  818. if (i >= (int)AVALON_READ_SIZE)
  819. avalon_inc_nvw(info, thr);
  820. else
  821. applog(LOG_WARNING, "Avalon: Discarding %d bytes from buffer", i);
  822. }
  823. }
  824. *offset -= spare;
  825. memmove(buf, buf + spare, *offset);
  826. }
  827. static void avalon_running_reset(struct cgpu_info *avalon,
  828. struct avalon_info *info)
  829. {
  830. avalon_reset(avalon, false);
  831. avalon_idle(avalon, info);
  832. avalon->results = 0;
  833. info->reset = false;
  834. }
  835. static void *avalon_get_results(void *userdata)
  836. {
  837. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  838. struct avalon_info *info = avalon->device_data;
  839. const int rsize = AVALON_FTDI_READSIZE;
  840. char readbuf[AVALON_READBUF_SIZE];
  841. struct thr_info *thr = info->thr;
  842. int offset = 0, ret = 0;
  843. char threadname[16];
  844. snprintf(threadname, sizeof(threadname), "%d/AvaRecv", avalon->device_id);
  845. RenameThread(threadname);
  846. while (likely(!avalon->shutdown)) {
  847. char buf[rsize];
  848. if (offset >= (int)AVALON_READ_SIZE)
  849. avalon_parse_results(avalon, info, thr, readbuf, &offset);
  850. if (unlikely(offset + rsize >= AVALON_READBUF_SIZE)) {
  851. /* This should never happen */
  852. applog(LOG_ERR, "Avalon readbuf overflow, resetting buffer");
  853. offset = 0;
  854. }
  855. if (unlikely(info->reset)) {
  856. avalon_running_reset(avalon, info);
  857. /* Discard anything in the buffer */
  858. offset = 0;
  859. }
  860. ret = avalon_read(avalon, buf, rsize, C_AVALON_READ);
  861. if (unlikely(ret < 0))
  862. break;
  863. if (ret < 1)
  864. continue;
  865. if (opt_debug) {
  866. applog(LOG_DEBUG, "Avalon: get:");
  867. hexdump((uint8_t *)buf, ret);
  868. }
  869. memcpy(&readbuf[offset], &buf, ret);
  870. offset += ret;
  871. }
  872. return NULL;
  873. }
  874. static void avalon_rotate_array(struct cgpu_info *avalon, struct avalon_info *info)
  875. {
  876. mutex_lock(&info->qlock);
  877. avalon->queued = 0;
  878. if (++avalon->work_array >= AVALON_ARRAY_SIZE)
  879. avalon->work_array = 0;
  880. mutex_unlock(&info->qlock);
  881. }
  882. static void bitburner_rotate_array(struct cgpu_info *avalon)
  883. {
  884. avalon->queued = 0;
  885. if (++avalon->work_array >= BITBURNER_ARRAY_SIZE)
  886. avalon->work_array = 0;
  887. }
  888. static void avalon_set_timeout(struct avalon_info *info)
  889. {
  890. info->timeout = avalon_calc_timeout(info->frequency);
  891. }
  892. static void avalon_set_freq(struct cgpu_info *avalon, int frequency)
  893. {
  894. struct avalon_info *info = avalon->device_data;
  895. info->frequency = frequency;
  896. if (info->frequency > opt_avalon_freq_max)
  897. info->frequency = opt_avalon_freq_max;
  898. if (info->frequency < opt_avalon_freq_min)
  899. info->frequency = opt_avalon_freq_min;
  900. avalon_set_timeout(info);
  901. applog(LOG_WARNING, "%s%i: Set frequency to %d, timeout %d",
  902. avalon->drv->name, avalon->device_id,
  903. info->frequency, info->timeout);
  904. }
  905. static void avalon_inc_freq(struct avalon_info *info)
  906. {
  907. info->frequency += info->increment;
  908. if (info->frequency > opt_avalon_freq_max)
  909. info->frequency = opt_avalon_freq_max;
  910. avalon_set_timeout(info);
  911. applog(LOG_NOTICE, "Avalon increasing frequency to %d, timeout %d",
  912. info->frequency, info->timeout);
  913. }
  914. static void avalon_dec_freq(struct avalon_info *info)
  915. {
  916. info->frequency -= info->decrement;
  917. if (info->frequency < opt_avalon_freq_min)
  918. info->frequency = opt_avalon_freq_min;
  919. avalon_set_timeout(info);
  920. applog(LOG_NOTICE, "Avalon decreasing frequency to %d, timeout %d",
  921. info->frequency, info->timeout);
  922. }
  923. static void avalon_reset_auto(struct avalon_info *info)
  924. {
  925. info->auto_queued =
  926. info->auto_nonces =
  927. info->auto_hw = 0;
  928. }
  929. static void avalon_adjust_freq(struct avalon_info *info, struct cgpu_info *avalon)
  930. {
  931. if (opt_avalon_auto && info->auto_queued >= AVALON_AUTO_CYCLE) {
  932. mutex_lock(&info->lock);
  933. if (!info->optimal) {
  934. if (info->fan_pwm >= opt_avalon_fan_max) {
  935. applog(LOG_WARNING,
  936. "%s%i: Above optimal temperature, throttling",
  937. avalon->drv->name, avalon->device_id);
  938. avalon_dec_freq(info);
  939. }
  940. } else if (info->auto_nonces >= AVALON_AUTO_CYCLE / 2) {
  941. int total = info->auto_nonces + info->auto_hw;
  942. /* Try to keep hw errors < 2% */
  943. if (info->auto_hw * 100 < total)
  944. avalon_inc_freq(info);
  945. else if (info->auto_hw * 66 > total)
  946. avalon_dec_freq(info);
  947. }
  948. avalon_reset_auto(info);
  949. mutex_unlock(&info->lock);
  950. }
  951. }
  952. static void *avalon_send_tasks(void *userdata)
  953. {
  954. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  955. struct avalon_info *info = avalon->device_data;
  956. const int avalon_get_work_count = info->miner_count;
  957. char threadname[16];
  958. snprintf(threadname, sizeof(threadname), "%d/AvaSend", avalon->device_id);
  959. RenameThread(threadname);
  960. while (likely(!avalon->shutdown)) {
  961. int start_count, end_count, i, j, ret;
  962. cgtimer_t ts_start;
  963. struct avalon_task at;
  964. bool idled = false;
  965. int64_t us_timeout;
  966. while (avalon_buffer_full(avalon))
  967. cgsleep_ms(40);
  968. avalon_adjust_freq(info, avalon);
  969. /* A full nonce range */
  970. us_timeout = 0x100000000ll / info->asic_count / info->frequency;
  971. cgsleep_prepare_r(&ts_start);
  972. start_count = avalon->work_array * avalon_get_work_count;
  973. end_count = start_count + avalon_get_work_count;
  974. for (i = start_count, j = 0; i < end_count; i++, j++) {
  975. if (avalon_buffer_full(avalon)) {
  976. applog(LOG_INFO,
  977. "%s%i: Buffer full after only %d of %d work queued",
  978. avalon->drv->name, avalon->device_id, j, avalon_get_work_count);
  979. break;
  980. }
  981. mutex_lock(&info->qlock);
  982. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  983. avalon_init_task(&at, 0, 0, info->fan_pwm,
  984. info->timeout, info->asic_count,
  985. info->miner_count, 1, 0, info->frequency, info->asic);
  986. avalon_create_task(&at, avalon->works[i]);
  987. info->auto_queued++;
  988. } else {
  989. int idle_freq = info->frequency;
  990. if (!info->idle++)
  991. idled = true;
  992. if (unlikely(info->overheat && opt_avalon_auto))
  993. idle_freq = AVALON_MIN_FREQUENCY;
  994. avalon_init_task(&at, 0, 0, info->fan_pwm,
  995. info->timeout, info->asic_count,
  996. info->miner_count, 1, 1, idle_freq, info->asic);
  997. /* Reset the auto_queued count if we end up
  998. * idling any miners. */
  999. avalon_reset_auto(info);
  1000. }
  1001. mutex_unlock(&info->qlock);
  1002. ret = avalon_send_task(&at, avalon, info);
  1003. if (unlikely(ret == AVA_SEND_ERROR)) {
  1004. /* Send errors are fatal */
  1005. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  1006. avalon->drv->name, avalon->device_id);
  1007. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  1008. goto out;
  1009. }
  1010. }
  1011. avalon_rotate_array(avalon, info);
  1012. cgsem_post(&info->qsem);
  1013. if (unlikely(idled)) {
  1014. applog(LOG_WARNING, "%s%i: Idled %d miners",
  1015. avalon->drv->name, avalon->device_id, idled);
  1016. }
  1017. /* Sleep how long it would take to complete a full nonce range
  1018. * at the current frequency using the clock_nanosleep function
  1019. * timed from before we started loading new work so it will
  1020. * fall short of the full duration. */
  1021. cgsleep_us_r(&ts_start, us_timeout);
  1022. }
  1023. out:
  1024. return NULL;
  1025. }
  1026. static void *bitburner_send_tasks(void *userdata)
  1027. {
  1028. struct cgpu_info *avalon = (struct cgpu_info *)userdata;
  1029. struct avalon_info *info = avalon->device_data;
  1030. const int avalon_get_work_count = info->miner_count;
  1031. char threadname[16];
  1032. snprintf(threadname, sizeof(threadname), "%d/AvaSend", avalon->device_id);
  1033. RenameThread(threadname);
  1034. while (likely(!avalon->shutdown)) {
  1035. int start_count, end_count, i, j, ret;
  1036. struct avalon_task at;
  1037. bool idled = false;
  1038. while (avalon_buffer_full(avalon))
  1039. cgsleep_ms(40);
  1040. avalon_adjust_freq(info, avalon);
  1041. /* Give other threads a chance to acquire qlock. */
  1042. i = 0;
  1043. do {
  1044. cgsleep_ms(40);
  1045. } while (!avalon->shutdown && i++ < 15
  1046. && avalon->queued < avalon_get_work_count);
  1047. mutex_lock(&info->qlock);
  1048. start_count = avalon->work_array * avalon_get_work_count;
  1049. end_count = start_count + avalon_get_work_count;
  1050. for (i = start_count, j = 0; i < end_count; i++, j++) {
  1051. while (avalon_buffer_full(avalon))
  1052. cgsleep_ms(40);
  1053. if (likely(j < avalon->queued && !info->overheat && avalon->works[i])) {
  1054. avalon_init_task(&at, 0, 0, info->fan_pwm,
  1055. info->timeout, info->asic_count,
  1056. info->miner_count, 1, 0, info->frequency, info->asic);
  1057. avalon_create_task(&at, avalon->works[i]);
  1058. info->auto_queued++;
  1059. } else {
  1060. int idle_freq = info->frequency;
  1061. if (!info->idle++)
  1062. idled = true;
  1063. if (unlikely(info->overheat && opt_avalon_auto))
  1064. idle_freq = AVALON_MIN_FREQUENCY;
  1065. avalon_init_task(&at, 0, 0, info->fan_pwm,
  1066. info->timeout, info->asic_count,
  1067. info->miner_count, 1, 1, idle_freq, info->asic);
  1068. /* Reset the auto_queued count if we end up
  1069. * idling any miners. */
  1070. avalon_reset_auto(info);
  1071. }
  1072. ret = bitburner_send_task(&at, avalon);
  1073. if (unlikely(ret == AVA_SEND_ERROR)) {
  1074. applog(LOG_ERR, "%s%i: Comms error(buffer)",
  1075. avalon->drv->name, avalon->device_id);
  1076. dev_error(avalon, REASON_DEV_COMMS_ERROR);
  1077. info->reset = true;
  1078. break;
  1079. }
  1080. }
  1081. bitburner_rotate_array(avalon);
  1082. mutex_unlock(&info->qlock);
  1083. cgsem_post(&info->qsem);
  1084. if (unlikely(idled)) {
  1085. applog(LOG_WARNING, "%s%i: Idled %d miners",
  1086. avalon->drv->name, avalon->device_id, idled);
  1087. }
  1088. }
  1089. return NULL;
  1090. }
  1091. static bool avalon_prepare(struct thr_info *thr)
  1092. {
  1093. struct cgpu_info *avalon = thr->cgpu;
  1094. struct avalon_info *info = avalon->device_data;
  1095. int array_size = AVALON_ARRAY_SIZE;
  1096. void *(*write_thread_fn)(void *) = avalon_send_tasks;
  1097. if (is_bitburner(avalon)) {
  1098. array_size = BITBURNER_ARRAY_SIZE;
  1099. write_thread_fn = bitburner_send_tasks;
  1100. }
  1101. free(avalon->works);
  1102. avalon->works = calloc(info->miner_count * sizeof(struct work *),
  1103. array_size);
  1104. if (!avalon->works)
  1105. quit(1, "Failed to calloc avalon works in avalon_prepare");
  1106. info->thr = thr;
  1107. mutex_init(&info->lock);
  1108. mutex_init(&info->qlock);
  1109. cgsem_init(&info->qsem);
  1110. if (pthread_create(&info->read_thr, NULL, avalon_get_results, (void *)avalon))
  1111. quit(1, "Failed to create avalon read_thr");
  1112. if (pthread_create(&info->write_thr, NULL, write_thread_fn, (void *)avalon))
  1113. quit(1, "Failed to create avalon write_thr");
  1114. avalon_init(avalon);
  1115. return true;
  1116. }
  1117. static inline void record_temp_fan(struct cgpu_info *avalon, struct avalon_info *info,
  1118. struct avalon_result *ar)
  1119. {
  1120. double temp_max;
  1121. info->fan0 = ar->fan0 * AVALON_FAN_FACTOR;
  1122. info->fan1 = ar->fan1 * AVALON_FAN_FACTOR;
  1123. info->fan2 = ar->fan2 * AVALON_FAN_FACTOR;
  1124. info->temp0 = ar->temp0;
  1125. info->temp1 = ar->temp1;
  1126. info->temp2 = ar->temp2;
  1127. if (ar->temp0 & 0x80) {
  1128. ar->temp0 &= 0x7f;
  1129. info->temp0 = 0 - ((~ar->temp0 & 0x7f) + 1);
  1130. }
  1131. if (ar->temp1 & 0x80) {
  1132. ar->temp1 &= 0x7f;
  1133. info->temp1 = 0 - ((~ar->temp1 & 0x7f) + 1);
  1134. }
  1135. if (ar->temp2 & 0x80) {
  1136. ar->temp2 &= 0x7f;
  1137. info->temp2 = 0 - ((~ar->temp2 & 0x7f) + 1);
  1138. }
  1139. temp_max = info->temp0;
  1140. if (info->temp1 > temp_max)
  1141. temp_max = info->temp1;
  1142. if (info->temp2 > temp_max)
  1143. temp_max = info->temp2;
  1144. avalon->temp = avalon->temp * 0.63 + temp_max * 0.37;
  1145. }
  1146. static void temp_rise(struct avalon_info *info, int temp)
  1147. {
  1148. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 3) {
  1149. info->fan_pwm = AVALON_PWM_MAX;
  1150. return;
  1151. }
  1152. if (temp >= opt_avalon_temp + AVALON_TEMP_HYSTERESIS * 2)
  1153. info->fan_pwm += 10;
  1154. else if (temp > opt_avalon_temp)
  1155. info->fan_pwm += 5;
  1156. else if (temp >= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1157. info->fan_pwm += 1;
  1158. else
  1159. return;
  1160. if (info->fan_pwm > opt_avalon_fan_max)
  1161. info->fan_pwm = opt_avalon_fan_max;
  1162. }
  1163. static void temp_drop(struct avalon_info *info, int temp)
  1164. {
  1165. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 3) {
  1166. info->fan_pwm = opt_avalon_fan_min;
  1167. return;
  1168. }
  1169. if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS * 2)
  1170. info->fan_pwm -= 10;
  1171. else if (temp <= opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1172. info->fan_pwm -= 5;
  1173. else if (temp < opt_avalon_temp)
  1174. info->fan_pwm -= 1;
  1175. if (info->fan_pwm < opt_avalon_fan_min)
  1176. info->fan_pwm = opt_avalon_fan_min;
  1177. }
  1178. static inline void adjust_fan(struct avalon_info *info)
  1179. {
  1180. int temp_new;
  1181. temp_new = info->temp_sum / info->temp_history_count;
  1182. if (temp_new > info->temp_old)
  1183. temp_rise(info, temp_new);
  1184. else if (temp_new < info->temp_old)
  1185. temp_drop(info, temp_new);
  1186. else {
  1187. /* temp_new == info->temp_old */
  1188. if (temp_new > opt_avalon_temp)
  1189. temp_rise(info, temp_new);
  1190. else if (temp_new < opt_avalon_temp - AVALON_TEMP_HYSTERESIS)
  1191. temp_drop(info, temp_new);
  1192. }
  1193. info->temp_old = temp_new;
  1194. if (info->temp_old <= opt_avalon_temp)
  1195. info->optimal = true;
  1196. else
  1197. info->optimal = false;
  1198. }
  1199. static void avalon_update_temps(struct cgpu_info *avalon, struct avalon_info *info,
  1200. struct avalon_result *ar)
  1201. {
  1202. record_temp_fan(avalon, info, ar);
  1203. applog(LOG_INFO,
  1204. "Avalon: Fan1: %d/m, Fan2: %d/m, Fan3: %d/m\t"
  1205. "Temp1: %dC, Temp2: %dC, Temp3: %dC, TempMAX: %.0fC",
  1206. info->fan0, info->fan1, info->fan2,
  1207. info->temp0, info->temp1, info->temp2, avalon->temp);
  1208. info->temp_history_index++;
  1209. info->temp_sum += avalon->temp;
  1210. applog(LOG_DEBUG, "Avalon: temp_index: %d, temp_count: %d, temp_old: %d",
  1211. info->temp_history_index, info->temp_history_count, info->temp_old);
  1212. if (is_bitburner(avalon)) {
  1213. info->core_voltage = bitburner_get_core_voltage(avalon);
  1214. }
  1215. if (info->temp_history_index == info->temp_history_count) {
  1216. adjust_fan(info);
  1217. info->temp_history_index = 0;
  1218. info->temp_sum = 0;
  1219. }
  1220. if (unlikely(info->temp_old >= opt_avalon_overheat)) {
  1221. applog(LOG_WARNING, "%s%d overheat! Idling", avalon->drv->name, avalon->device_id);
  1222. info->overheat = true;
  1223. } else if (info->overheat && info->temp_old <= opt_avalon_temp) {
  1224. applog(LOG_WARNING, "%s%d cooled, restarting", avalon->drv->name, avalon->device_id);
  1225. info->overheat = false;
  1226. }
  1227. }
  1228. static void get_avalon_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon)
  1229. {
  1230. struct avalon_info *info = avalon->device_data;
  1231. int lowfan = 10000;
  1232. if (is_bitburner(avalon)) {
  1233. int temp = info->temp0;
  1234. if (info->temp2 > temp)
  1235. temp = info->temp2;
  1236. if (temp > 99)
  1237. temp = 99;
  1238. if (temp < 0)
  1239. temp = 0;
  1240. tailsprintf(buf, bufsiz, "%2dC %3dMHz %4dmV", temp, info->frequency, info->core_voltage);
  1241. } else {
  1242. /* Find the lowest fan speed of the ASIC cooling fans. */
  1243. if (info->fan1 >= 0 && info->fan1 < lowfan)
  1244. lowfan = info->fan1;
  1245. if (info->fan2 >= 0 && info->fan2 < lowfan)
  1246. lowfan = info->fan2;
  1247. tailsprintf(buf, bufsiz, "%2dC/%3dC %04dR", info->temp0, info->temp2, lowfan);
  1248. }
  1249. }
  1250. /* We use a replacement algorithm to only remove references to work done from
  1251. * the buffer when we need the extra space for new work. */
  1252. static bool avalon_fill(struct cgpu_info *avalon)
  1253. {
  1254. struct avalon_info *info = avalon->device_data;
  1255. int subid, slot, mc;
  1256. struct work *work;
  1257. bool ret = true;
  1258. mc = info->miner_count;
  1259. mutex_lock(&info->qlock);
  1260. if (avalon->queued >= mc)
  1261. goto out_unlock;
  1262. work = get_queued(avalon);
  1263. if (unlikely(!work)) {
  1264. ret = false;
  1265. goto out_unlock;
  1266. }
  1267. subid = avalon->queued++;
  1268. work->subid = subid;
  1269. slot = avalon->work_array * mc + subid;
  1270. if (likely(avalon->works[slot]))
  1271. work_completed(avalon, avalon->works[slot]);
  1272. avalon->works[slot] = work;
  1273. if (avalon->queued < mc)
  1274. ret = false;
  1275. out_unlock:
  1276. mutex_unlock(&info->qlock);
  1277. return ret;
  1278. }
  1279. static int64_t avalon_scanhash(struct thr_info *thr)
  1280. {
  1281. struct cgpu_info *avalon = thr->cgpu;
  1282. struct avalon_info *info = avalon->device_data;
  1283. const int miner_count = info->miner_count;
  1284. int64_t hash_count, ms_timeout;
  1285. /* Half nonce range */
  1286. ms_timeout = 0x80000000ll / info->asic_count / info->frequency / 1000;
  1287. /* Wait until avalon_send_tasks signals us that it has completed
  1288. * sending its work or a full nonce range timeout has occurred. We use
  1289. * cgsems to never miss a wakeup. */
  1290. cgsem_mswait(&info->qsem, ms_timeout);
  1291. mutex_lock(&info->lock);
  1292. hash_count = 0xffffffffull * (uint64_t)info->nonces;
  1293. avalon->results += info->nonces;
  1294. if (avalon->results > miner_count || info->idle)
  1295. avalon->results = miner_count;
  1296. if (!info->reset)
  1297. avalon->results--;
  1298. info->nonces = info->idle = 0;
  1299. mutex_unlock(&info->lock);
  1300. /* Check for nothing but consecutive bad results or consistently less
  1301. * results than we should be getting and reset the FPGA if necessary */
  1302. if (!is_bitburner(avalon)) {
  1303. if (avalon->results < -miner_count && !info->reset) {
  1304. applog(LOG_ERR, "%s%d: Result return rate low, resetting!",
  1305. avalon->drv->name, avalon->device_id);
  1306. avalon->results = miner_count;
  1307. info->reset = true;
  1308. }
  1309. }
  1310. if (unlikely(avalon->usbinfo.nodev)) {
  1311. applog(LOG_ERR, "%s%d: Device disappeared, shutting down thread",
  1312. avalon->drv->name, avalon->device_id);
  1313. hash_count = -1;
  1314. }
  1315. /* This hashmeter is just a utility counter based on returned shares */
  1316. return hash_count;
  1317. }
  1318. static void avalon_flush_work(struct cgpu_info *avalon)
  1319. {
  1320. struct avalon_info *info = avalon->device_data;
  1321. /* Will overwrite any work queued. Do this unlocked since it's just
  1322. * changing a single non-critical value and prevents deadlocks */
  1323. avalon->queued = 0;
  1324. /* Signal main loop we need more work */
  1325. cgsem_post(&info->qsem);
  1326. }
  1327. static struct api_data *avalon_api_stats(struct cgpu_info *cgpu)
  1328. {
  1329. struct api_data *root = NULL;
  1330. struct avalon_info *info = cgpu->device_data;
  1331. char buf[64];
  1332. int i;
  1333. double hwp = (cgpu->hw_errors + cgpu->diff1) ?
  1334. (double)(cgpu->hw_errors) / (double)(cgpu->hw_errors + cgpu->diff1) : 0;
  1335. root = api_add_int(root, "baud", &(info->baud), false);
  1336. root = api_add_int(root, "miner_count", &(info->miner_count),false);
  1337. root = api_add_int(root, "asic_count", &(info->asic_count), false);
  1338. root = api_add_int(root, "timeout", &(info->timeout), false);
  1339. root = api_add_int(root, "frequency", &(info->frequency), false);
  1340. root = api_add_int(root, "fan1", &(info->fan0), false);
  1341. root = api_add_int(root, "fan2", &(info->fan1), false);
  1342. root = api_add_int(root, "fan3", &(info->fan2), false);
  1343. root = api_add_int(root, "temp1", &(info->temp0), false);
  1344. root = api_add_int(root, "temp2", &(info->temp1), false);
  1345. root = api_add_int(root, "temp3", &(info->temp2), false);
  1346. root = api_add_double(root, "temp_max", &cgpu->temp, false);
  1347. root = api_add_percent(root, "Device Hardware%", &hwp, true);
  1348. root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);
  1349. for (i = 0; i < info->miner_count; i++) {
  1350. char mcw[24];
  1351. sprintf(mcw, "match_work_count%d", i + 1);
  1352. root = api_add_int(root, mcw, &(info->matching_work[i]), false);
  1353. }
  1354. if (is_bitburner(cgpu)) {
  1355. root = api_add_int(root, "core_voltage", &(info->core_voltage), false);
  1356. snprintf(buf, sizeof(buf), "%"PRIu8".%"PRIu8".%"PRIu8,
  1357. info->version1, info->version2, info->version3);
  1358. root = api_add_string(root, "version", buf, true);
  1359. }
  1360. root = api_add_uint32(root, "Controller Version", &(info->ctlr_ver), false);
  1361. root = api_add_uint32(root, "Avalon Chip", &(info->asic), false);
  1362. return root;
  1363. }
  1364. static void avalon_shutdown(struct thr_info *thr)
  1365. {
  1366. struct cgpu_info *avalon = thr->cgpu;
  1367. struct avalon_info *info = avalon->device_data;
  1368. pthread_join(info->read_thr, NULL);
  1369. pthread_join(info->write_thr, NULL);
  1370. avalon_running_reset(avalon, info);
  1371. cgsem_destroy(&info->qsem);
  1372. mutex_destroy(&info->qlock);
  1373. mutex_destroy(&info->lock);
  1374. free(avalon->works);
  1375. avalon->works = NULL;
  1376. }
  1377. static char *avalon_set_device(struct cgpu_info *avalon, char *option, char *setting, char *replybuf)
  1378. {
  1379. int val;
  1380. if (strcasecmp(option, "help") == 0) {
  1381. sprintf(replybuf, "freq: range %d-%d millivolts: range %d-%d",
  1382. AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY,
  1383. BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1384. return replybuf;
  1385. }
  1386. if (strcasecmp(option, "millivolts") == 0 || strcasecmp(option, "mv") == 0) {
  1387. if (!is_bitburner(avalon)) {
  1388. sprintf(replybuf, "%s cannot set millivolts", avalon->drv->name);
  1389. return replybuf;
  1390. }
  1391. if (!setting || !*setting) {
  1392. sprintf(replybuf, "missing millivolts setting");
  1393. return replybuf;
  1394. }
  1395. val = atoi(setting);
  1396. if (val < BITBURNER_MIN_COREMV || val > BITBURNER_MAX_COREMV) {
  1397. sprintf(replybuf, "invalid millivolts: '%s' valid range %d-%d",
  1398. setting, BITBURNER_MIN_COREMV, BITBURNER_MAX_COREMV);
  1399. return replybuf;
  1400. }
  1401. if (bitburner_set_core_voltage(avalon, val))
  1402. return NULL;
  1403. else {
  1404. sprintf(replybuf, "Set millivolts failed");
  1405. return replybuf;
  1406. }
  1407. }
  1408. if (strcasecmp(option, "freq") == 0) {
  1409. if (!setting || !*setting) {
  1410. sprintf(replybuf, "missing freq setting");
  1411. return replybuf;
  1412. }
  1413. val = atoi(setting);
  1414. if (val < AVALON_MIN_FREQUENCY || val > AVALON_MAX_FREQUENCY) {
  1415. sprintf(replybuf, "invalid freq: '%s' valid range %d-%d",
  1416. setting, AVALON_MIN_FREQUENCY, AVALON_MAX_FREQUENCY);
  1417. return replybuf;
  1418. }
  1419. avalon_set_freq(avalon, val);
  1420. return NULL;
  1421. }
  1422. sprintf(replybuf, "Unknown option: %s", option);
  1423. return replybuf;
  1424. }
  1425. struct device_drv avalon_drv = {
  1426. .drv_id = DRIVER_avalon,
  1427. .dname = "avalon",
  1428. .name = "AVA",
  1429. .drv_detect = avalon_detect,
  1430. .thread_prepare = avalon_prepare,
  1431. .hash_work = hash_queued_work,
  1432. .queue_full = avalon_fill,
  1433. .scanwork = avalon_scanhash,
  1434. .flush_work = avalon_flush_work,
  1435. .get_api_stats = avalon_api_stats,
  1436. .get_statline_before = get_avalon_statline_before,
  1437. .set_device = avalon_set_device,
  1438. .reinit_device = avalon_init,
  1439. .thread_shutdown = avalon_shutdown,
  1440. };