605-MIPS-ath79-db120-fixes.patch 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204
  1. --- a/arch/mips/ath79/mach-db120.c
  2. +++ b/arch/mips/ath79/mach-db120.c
  3. @@ -2,7 +2,7 @@
  4. * Atheros DB120 reference board support
  5. *
  6. * Copyright (c) 2011 Qualcomm Atheros
  7. - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
  8. + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
  9. *
  10. * Permission to use, copy, modify, and/or distribute this software for any
  11. * purpose with or without fee is hereby granted, provided that the above
  12. @@ -19,16 +19,26 @@
  13. */
  14. #include <linux/pci.h>
  15. +#include <linux/phy.h>
  16. +#include <linux/platform_device.h>
  17. #include <linux/ath9k_platform.h>
  18. +#include <linux/ar8216_platform.h>
  19. -#include "machtypes.h"
  20. +#include <asm/mach-ath79/ar71xx_regs.h>
  21. +
  22. +#include "common.h"
  23. +#include "dev-ap9x-pci.h"
  24. +#include "dev-eth.h"
  25. #include "dev-gpio-buttons.h"
  26. #include "dev-leds-gpio.h"
  27. +#include "dev-m25p80.h"
  28. +#include "dev-nfc.h"
  29. #include "dev-spi.h"
  30. #include "dev-usb.h"
  31. #include "dev-wmac.h"
  32. -#include "pci.h"
  33. +#include "machtypes.h"
  34. +#define DB120_GPIO_LED_USB 11
  35. #define DB120_GPIO_LED_WLAN_5G 12
  36. #define DB120_GPIO_LED_WLAN_2G 13
  37. #define DB120_GPIO_LED_STATUS 14
  38. @@ -39,8 +49,10 @@
  39. #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
  40. #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
  41. -#define DB120_WMAC_CALDATA_OFFSET 0x1000
  42. -#define DB120_PCIE_CALDATA_OFFSET 0x5000
  43. +#define DB120_MAC0_OFFSET 0
  44. +#define DB120_MAC1_OFFSET 6
  45. +#define DB120_WMAC_CALDATA_OFFSET 0x1000
  46. +#define DB120_PCIE_CALDATA_OFFSET 0x5000
  47. static struct gpio_led db120_leds_gpio[] __initdata = {
  48. {
  49. @@ -63,6 +75,11 @@ static struct gpio_led db120_leds_gpio[]
  50. .gpio = DB120_GPIO_LED_WLAN_2G,
  51. .active_low = 1,
  52. },
  53. + {
  54. + .name = "db120:green:usb",
  55. + .gpio = DB120_GPIO_LED_USB,
  56. + .active_low = 1,
  57. + }
  58. };
  59. static struct gpio_keys_button db120_gpio_keys[] __initdata = {
  60. @@ -76,60 +93,85 @@ static struct gpio_keys_button db120_gpi
  61. },
  62. };
  63. -static struct spi_board_info db120_spi_info[] = {
  64. - {
  65. - .bus_num = 0,
  66. - .chip_select = 0,
  67. - .max_speed_hz = 25000000,
  68. - .modalias = "s25sl064a",
  69. - }
  70. +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
  71. + .mode = AR8327_PAD_MAC_RGMII,
  72. + .txclk_delay_en = true,
  73. + .rxclk_delay_en = true,
  74. + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  75. + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  76. };
  77. -static struct ath79_spi_platform_data db120_spi_data = {
  78. - .bus_num = 0,
  79. - .num_chipselect = 1,
  80. +static struct ar8327_led_cfg db120_ar8327_led_cfg = {
  81. + .led_ctrl0 = 0x00000000,
  82. + .led_ctrl1 = 0xc737c737,
  83. + .led_ctrl2 = 0x00000000,
  84. + .led_ctrl3 = 0x00c30c00,
  85. + .open_drain = true,
  86. };
  87. -#ifdef CONFIG_PCI
  88. -static struct ath9k_platform_data db120_ath9k_data;
  89. -
  90. -static int db120_pci_plat_dev_init(struct pci_dev *dev)
  91. -{
  92. - switch (PCI_SLOT(dev->devfn)) {
  93. - case 0:
  94. - dev->dev.platform_data = &db120_ath9k_data;
  95. - break;
  96. - }
  97. -
  98. - return 0;
  99. -}
  100. -
  101. -static void __init db120_pci_init(u8 *eeprom)
  102. -{
  103. - memcpy(db120_ath9k_data.eeprom_data, eeprom,
  104. - sizeof(db120_ath9k_data.eeprom_data));
  105. +static struct ar8327_platform_data db120_ar8327_data = {
  106. + .pad0_cfg = &db120_ar8327_pad0_cfg,
  107. + .port0_cfg = {
  108. + .force_link = 1,
  109. + .speed = AR8327_PORT_SPEED_1000,
  110. + .duplex = 1,
  111. + .txpause = 1,
  112. + .rxpause = 1,
  113. + },
  114. + .led_cfg = &db120_ar8327_led_cfg,
  115. +};
  116. - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
  117. - ath79_register_pci();
  118. -}
  119. -#else
  120. -static inline void db120_pci_init(u8 *eeprom) {}
  121. -#endif /* CONFIG_PCI */
  122. +static struct mdio_board_info db120_mdio0_info[] = {
  123. + {
  124. + .bus_id = "ag71xx-mdio.0",
  125. + .phy_addr = 0,
  126. + .platform_data = &db120_ar8327_data,
  127. + },
  128. +};
  129. static void __init db120_setup(void)
  130. {
  131. u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  132. + ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
  133. + ath79_register_m25p80(NULL);
  134. +
  135. ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
  136. db120_leds_gpio);
  137. ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
  138. ARRAY_SIZE(db120_gpio_keys),
  139. db120_gpio_keys);
  140. - ath79_register_spi(&db120_spi_data, db120_spi_info,
  141. - ARRAY_SIZE(db120_spi_info));
  142. ath79_register_usb();
  143. ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
  144. - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
  145. + ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
  146. +
  147. + ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
  148. + AR934X_ETH_CFG_SW_ONLY_MODE);
  149. +
  150. + ath79_register_mdio(1, 0x0);
  151. + ath79_register_mdio(0, 0x0);
  152. +
  153. + ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
  154. +
  155. + mdiobus_register_board_info(db120_mdio0_info,
  156. + ARRAY_SIZE(db120_mdio0_info));
  157. +
  158. + /* GMAC0 is connected to an AR8327 switch */
  159. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  160. + ath79_eth0_data.phy_mask = BIT(0);
  161. + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
  162. + ath79_eth0_pll_data.pll_1000 = 0x06000000;
  163. + ath79_register_eth(0);
  164. +
  165. + /* GMAC1 is connected to the internal switch */
  166. + ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
  167. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
  168. + ath79_eth1_data.speed = SPEED_1000;
  169. + ath79_eth1_data.duplex = DUPLEX_FULL;
  170. +
  171. + ath79_register_eth(1);
  172. +
  173. + ath79_register_nfc();
  174. }
  175. MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
  176. --- a/arch/mips/ath79/Kconfig
  177. +++ b/arch/mips/ath79/Kconfig
  178. @@ -43,9 +43,12 @@ config ATH79_MACH_AP81
  179. config ATH79_MACH_DB120
  180. bool "Atheros DB120 reference board"
  181. select SOC_AR934X
  182. + select ATH79_DEV_AP9X_PCI if PCI
  183. + select ATH79_DEV_ETH
  184. select ATH79_DEV_GPIO_BUTTONS
  185. select ATH79_DEV_LEDS_GPIO
  186. - select ATH79_DEV_SPI
  187. + select ATH79_DEV_M25P80
  188. + select ATH79_DEV_NFC
  189. select ATH79_DEV_USB
  190. select ATH79_DEV_WMAC
  191. help