0117-drm-vc4-A-few-more-non-functional-changes-to-sync-to.patch 10 KB

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  1. From 95ef989ba2f3a5e10c742a3f6ed88e16a9f11e56 Mon Sep 17 00:00:00 2001
  2. From: Eric Anholt <eric@anholt.net>
  3. Date: Tue, 8 Dec 2015 14:00:43 -0800
  4. Subject: [PATCH 117/381] drm/vc4: A few more non-functional changes to sync to
  5. upstream.
  6. At this point all that's left is the force-enable of HDMI connector,
  7. and using direct firmware calls to turn on V3D instead of the generic
  8. power domain support.
  9. Signed-off-by: Eric Anholt <eric@anholt.net>
  10. ---
  11. drivers/gpu/drm/vc4/vc4_v3d.c | 2 +-
  12. include/uapi/drm/vc4_drm.h | 182 +++++++++++++++++++++---------------------
  13. 2 files changed, 92 insertions(+), 92 deletions(-)
  14. --- a/drivers/gpu/drm/vc4/vc4_v3d.c
  15. +++ b/drivers/gpu/drm/vc4/vc4_v3d.c
  16. @@ -109,7 +109,7 @@ static const struct {
  17. int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused)
  18. {
  19. - struct drm_info_node *node = (struct drm_info_node *) m->private;
  20. + struct drm_info_node *node = (struct drm_info_node *)m->private;
  21. struct drm_device *dev = node->minor->dev;
  22. struct vc4_dev *vc4 = to_vc4_dev(dev);
  23. int i;
  24. --- a/include/uapi/drm/vc4_drm.h
  25. +++ b/include/uapi/drm/vc4_drm.h
  26. @@ -24,7 +24,7 @@
  27. #ifndef _UAPI_VC4_DRM_H_
  28. #define _UAPI_VC4_DRM_H_
  29. -#include <drm/drm.h>
  30. +#include "drm.h"
  31. #define DRM_VC4_SUBMIT_CL 0x00
  32. #define DRM_VC4_WAIT_SEQNO 0x01
  33. @@ -34,25 +34,25 @@
  34. #define DRM_VC4_CREATE_SHADER_BO 0x05
  35. #define DRM_VC4_GET_HANG_STATE 0x06
  36. -#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
  37. -#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
  38. -#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
  39. -#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
  40. -#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
  41. -#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
  42. -#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
  43. +#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
  44. +#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
  45. +#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
  46. +#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
  47. +#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
  48. +#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
  49. +#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
  50. struct drm_vc4_submit_rcl_surface {
  51. - uint32_t hindex; /* Handle index, or ~0 if not present. */
  52. - uint32_t offset; /* Offset to start of buffer. */
  53. + __u32 hindex; /* Handle index, or ~0 if not present. */
  54. + __u32 offset; /* Offset to start of buffer. */
  55. /*
  56. - * Bits for either render config (color_write) or load/store packet.
  57. - * Bits should all be 0 for MSAA load/stores.
  58. + * Bits for either render config (color_write) or load/store packet.
  59. + * Bits should all be 0 for MSAA load/stores.
  60. */
  61. - uint16_t bits;
  62. + __u16 bits;
  63. #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
  64. - uint16_t flags;
  65. + __u16 flags;
  66. };
  67. /**
  68. @@ -76,7 +76,7 @@ struct drm_vc4_submit_cl {
  69. * then writes out the state updates and draw calls necessary per tile
  70. * to the tile allocation BO.
  71. */
  72. - uint64_t bin_cl;
  73. + __u64 bin_cl;
  74. /* Pointer to the shader records.
  75. *
  76. @@ -85,16 +85,16 @@ struct drm_vc4_submit_cl {
  77. * reference to the shader record has enough information to determine
  78. * how many pointers are necessary (fixed number for shaders/uniforms,
  79. * and an attribute count), so those BO indices into bo_handles are
  80. - * just stored as uint32_ts before each shader record passed in.
  81. + * just stored as __u32s before each shader record passed in.
  82. */
  83. - uint64_t shader_rec;
  84. + __u64 shader_rec;
  85. /* Pointer to uniform data and texture handles for the textures
  86. * referenced by the shader.
  87. *
  88. * For each shader state record, there is a set of uniform data in the
  89. * order referenced by the record (FS, VS, then CS). Each set of
  90. - * uniform data has a uint32_t index into bo_handles per texture
  91. + * uniform data has a __u32 index into bo_handles per texture
  92. * sample operation, in the order the QPU_W_TMUn_S writes appear in
  93. * the program. Following the texture BO handle indices is the actual
  94. * uniform data.
  95. @@ -103,52 +103,52 @@ struct drm_vc4_submit_cl {
  96. * because the kernel has to determine the sizes anyway during shader
  97. * code validation.
  98. */
  99. - uint64_t uniforms;
  100. - uint64_t bo_handles;
  101. + __u64 uniforms;
  102. + __u64 bo_handles;
  103. /* Size in bytes of the binner command list. */
  104. - uint32_t bin_cl_size;
  105. + __u32 bin_cl_size;
  106. /* Size in bytes of the set of shader records. */
  107. - uint32_t shader_rec_size;
  108. + __u32 shader_rec_size;
  109. /* Number of shader records.
  110. *
  111. * This could just be computed from the contents of shader_records and
  112. * the address bits of references to them from the bin CL, but it
  113. * keeps the kernel from having to resize some allocations it makes.
  114. */
  115. - uint32_t shader_rec_count;
  116. + __u32 shader_rec_count;
  117. /* Size in bytes of the uniform state. */
  118. - uint32_t uniforms_size;
  119. + __u32 uniforms_size;
  120. /* Number of BO handles passed in (size is that times 4). */
  121. - uint32_t bo_handle_count;
  122. + __u32 bo_handle_count;
  123. /* RCL setup: */
  124. - uint16_t width;
  125. - uint16_t height;
  126. - uint8_t min_x_tile;
  127. - uint8_t min_y_tile;
  128. - uint8_t max_x_tile;
  129. - uint8_t max_y_tile;
  130. + __u16 width;
  131. + __u16 height;
  132. + __u8 min_x_tile;
  133. + __u8 min_y_tile;
  134. + __u8 max_x_tile;
  135. + __u8 max_y_tile;
  136. struct drm_vc4_submit_rcl_surface color_read;
  137. struct drm_vc4_submit_rcl_surface color_write;
  138. struct drm_vc4_submit_rcl_surface zs_read;
  139. struct drm_vc4_submit_rcl_surface zs_write;
  140. struct drm_vc4_submit_rcl_surface msaa_color_write;
  141. struct drm_vc4_submit_rcl_surface msaa_zs_write;
  142. - uint32_t clear_color[2];
  143. - uint32_t clear_z;
  144. - uint8_t clear_s;
  145. + __u32 clear_color[2];
  146. + __u32 clear_z;
  147. + __u8 clear_s;
  148. - uint32_t pad:24;
  149. + __u32 pad:24;
  150. #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
  151. - uint32_t flags;
  152. + __u32 flags;
  153. /* Returned value of the seqno of this render job (for the
  154. * wait ioctl).
  155. */
  156. - uint64_t seqno;
  157. + __u64 seqno;
  158. };
  159. /**
  160. @@ -159,8 +159,8 @@ struct drm_vc4_submit_cl {
  161. * block, just return the status."
  162. */
  163. struct drm_vc4_wait_seqno {
  164. - uint64_t seqno;
  165. - uint64_t timeout_ns;
  166. + __u64 seqno;
  167. + __u64 timeout_ns;
  168. };
  169. /**
  170. @@ -172,9 +172,9 @@ struct drm_vc4_wait_seqno {
  171. * completed.
  172. */
  173. struct drm_vc4_wait_bo {
  174. - uint32_t handle;
  175. - uint32_t pad;
  176. - uint64_t timeout_ns;
  177. + __u32 handle;
  178. + __u32 pad;
  179. + __u64 timeout_ns;
  180. };
  181. /**
  182. @@ -184,11 +184,30 @@ struct drm_vc4_wait_bo {
  183. * used in a future extension.
  184. */
  185. struct drm_vc4_create_bo {
  186. - uint32_t size;
  187. - uint32_t flags;
  188. + __u32 size;
  189. + __u32 flags;
  190. /** Returned GEM handle for the BO. */
  191. - uint32_t handle;
  192. - uint32_t pad;
  193. + __u32 handle;
  194. + __u32 pad;
  195. +};
  196. +
  197. +/**
  198. + * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
  199. + *
  200. + * This doesn't actually perform an mmap. Instead, it returns the
  201. + * offset you need to use in an mmap on the DRM device node. This
  202. + * means that tools like valgrind end up knowing about the mapped
  203. + * memory.
  204. + *
  205. + * There are currently no values for the flags argument, but it may be
  206. + * used in a future extension.
  207. + */
  208. +struct drm_vc4_mmap_bo {
  209. + /** Handle for the object being mapped. */
  210. + __u32 handle;
  211. + __u32 flags;
  212. + /** offset into the drm node to use for subsequent mmap call. */
  213. + __u64 offset;
  214. };
  215. /**
  216. @@ -201,43 +220,24 @@ struct drm_vc4_create_bo {
  217. */
  218. struct drm_vc4_create_shader_bo {
  219. /* Size of the data argument. */
  220. - uint32_t size;
  221. + __u32 size;
  222. /* Flags, currently must be 0. */
  223. - uint32_t flags;
  224. + __u32 flags;
  225. /* Pointer to the data. */
  226. - uint64_t data;
  227. + __u64 data;
  228. /** Returned GEM handle for the BO. */
  229. - uint32_t handle;
  230. + __u32 handle;
  231. /* Pad, must be 0. */
  232. - uint32_t pad;
  233. -};
  234. -
  235. -/**
  236. - * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
  237. - *
  238. - * This doesn't actually perform an mmap. Instead, it returns the
  239. - * offset you need to use in an mmap on the DRM device node. This
  240. - * means that tools like valgrind end up knowing about the mapped
  241. - * memory.
  242. - *
  243. - * There are currently no values for the flags argument, but it may be
  244. - * used in a future extension.
  245. - */
  246. -struct drm_vc4_mmap_bo {
  247. - /** Handle for the object being mapped. */
  248. - uint32_t handle;
  249. - uint32_t flags;
  250. - /** offset into the drm node to use for subsequent mmap call. */
  251. - uint64_t offset;
  252. + __u32 pad;
  253. };
  254. struct drm_vc4_get_hang_state_bo {
  255. - uint32_t handle;
  256. - uint32_t paddr;
  257. - uint32_t size;
  258. - uint32_t pad;
  259. + __u32 handle;
  260. + __u32 paddr;
  261. + __u32 size;
  262. + __u32 pad;
  263. };
  264. /**
  265. @@ -246,34 +246,34 @@ struct drm_vc4_get_hang_state_bo {
  266. */
  267. struct drm_vc4_get_hang_state {
  268. /** Pointer to array of struct drm_vc4_get_hang_state_bo. */
  269. - uint64_t bo;
  270. + __u64 bo;
  271. /**
  272. * On input, the size of the bo array. Output is the number
  273. * of bos to be returned.
  274. */
  275. - uint32_t bo_count;
  276. + __u32 bo_count;
  277. - uint32_t start_bin, start_render;
  278. + __u32 start_bin, start_render;
  279. - uint32_t ct0ca, ct0ea;
  280. - uint32_t ct1ca, ct1ea;
  281. - uint32_t ct0cs, ct1cs;
  282. - uint32_t ct0ra0, ct1ra0;
  283. -
  284. - uint32_t bpca, bpcs;
  285. - uint32_t bpoa, bpos;
  286. -
  287. - uint32_t vpmbase;
  288. -
  289. - uint32_t dbge;
  290. - uint32_t fdbgo;
  291. - uint32_t fdbgb;
  292. - uint32_t fdbgr;
  293. - uint32_t fdbgs;
  294. - uint32_t errstat;
  295. + __u32 ct0ca, ct0ea;
  296. + __u32 ct1ca, ct1ea;
  297. + __u32 ct0cs, ct1cs;
  298. + __u32 ct0ra0, ct1ra0;
  299. +
  300. + __u32 bpca, bpcs;
  301. + __u32 bpoa, bpos;
  302. +
  303. + __u32 vpmbase;
  304. +
  305. + __u32 dbge;
  306. + __u32 fdbgo;
  307. + __u32 fdbgb;
  308. + __u32 fdbgr;
  309. + __u32 fdbgs;
  310. + __u32 errstat;
  311. /* Pad that we may save more registers into in the future. */
  312. - uint32_t pad[16];
  313. + __u32 pad[16];
  314. };
  315. #endif /* _UAPI_VC4_DRM_H_ */