0281-drm-vc4-Make-the-CRTCs-cooperate-on-allocating-displ.patch 7.7 KB

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  1. From 645f9aea7c4c7880059f87a715a8bdd004ef9604 Mon Sep 17 00:00:00 2001
  2. From: Eric Anholt <eric@anholt.net>
  3. Date: Mon, 28 Dec 2015 13:25:41 -0800
  4. Subject: [PATCH 281/381] drm/vc4: Make the CRTCs cooperate on allocating
  5. display lists.
  6. So far, we've only ever lit up one CRTC, so this has been fine. To
  7. extend to more displays or more planes, we need to make sure we don't
  8. run our display lists into each other.
  9. Signed-off-by: Eric Anholt <eric@anholt.net>
  10. (cherry picked from commit d8dbf44f13b91185c618219d912b246817a8d132)
  11. ---
  12. drivers/gpu/drm/vc4/vc4_crtc.c | 115 +++++++++++++++++++++++------------------
  13. drivers/gpu/drm/vc4/vc4_drv.h | 8 ++-
  14. drivers/gpu/drm/vc4/vc4_hvs.c | 13 +++++
  15. 3 files changed, 84 insertions(+), 52 deletions(-)
  16. --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  17. +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  18. @@ -49,22 +49,27 @@ struct vc4_crtc {
  19. /* Which HVS channel we're using for our CRTC. */
  20. int channel;
  21. - /* Pointer to the actual hardware display list memory for the
  22. - * crtc.
  23. - */
  24. - u32 __iomem *dlist;
  25. -
  26. - u32 dlist_size; /* in dwords */
  27. -
  28. struct drm_pending_vblank_event *event;
  29. };
  30. +struct vc4_crtc_state {
  31. + struct drm_crtc_state base;
  32. + /* Dlist area for this CRTC configuration. */
  33. + struct drm_mm_node mm;
  34. +};
  35. +
  36. static inline struct vc4_crtc *
  37. to_vc4_crtc(struct drm_crtc *crtc)
  38. {
  39. return (struct vc4_crtc *)crtc;
  40. }
  41. +static inline struct vc4_crtc_state *
  42. +to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  43. +{
  44. + return (struct vc4_crtc_state *)crtc_state;
  45. +}
  46. +
  47. struct vc4_crtc_data {
  48. /* Which channel of the HVS this pixelvalve sources from. */
  49. int hvs_channel;
  50. @@ -319,11 +324,13 @@ static void vc4_crtc_enable(struct drm_c
  51. static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
  52. struct drm_crtc_state *state)
  53. {
  54. + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
  55. struct drm_device *dev = crtc->dev;
  56. struct vc4_dev *vc4 = to_vc4_dev(dev);
  57. struct drm_plane *plane;
  58. - struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  59. + unsigned long flags;
  60. u32 dlist_count = 0;
  61. + int ret;
  62. /* The pixelvalve can only feed one encoder (and encoders are
  63. * 1:1 with connectors.)
  64. @@ -346,18 +353,12 @@ static int vc4_crtc_atomic_check(struct
  65. dlist_count++; /* Account for SCALER_CTL0_END. */
  66. - if (!vc4_crtc->dlist || dlist_count > vc4_crtc->dlist_size) {
  67. - vc4_crtc->dlist = ((u32 __iomem *)vc4->hvs->dlist +
  68. - HVS_BOOTLOADER_DLIST_END);
  69. - vc4_crtc->dlist_size = ((SCALER_DLIST_SIZE >> 2) -
  70. - HVS_BOOTLOADER_DLIST_END);
  71. -
  72. - if (dlist_count > vc4_crtc->dlist_size) {
  73. - DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n",
  74. - dlist_count, vc4_crtc->dlist_size);
  75. - return -EINVAL;
  76. - }
  77. - }
  78. + spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
  79. + ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
  80. + dlist_count, 1, 0);
  81. + spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
  82. + if (ret)
  83. + return ret;
  84. return 0;
  85. }
  86. @@ -368,47 +369,29 @@ static void vc4_crtc_atomic_flush(struct
  87. struct drm_device *dev = crtc->dev;
  88. struct vc4_dev *vc4 = to_vc4_dev(dev);
  89. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  90. + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
  91. struct drm_plane *plane;
  92. bool debug_dump_regs = false;
  93. - u32 __iomem *dlist_next = vc4_crtc->dlist;
  94. + u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
  95. + u32 __iomem *dlist_next = dlist_start;
  96. if (debug_dump_regs) {
  97. DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
  98. vc4_hvs_dump_state(dev);
  99. }
  100. - /* Copy all the active planes' dlist contents to the hardware dlist.
  101. - *
  102. - * XXX: If the new display list was large enough that it
  103. - * overlapped a currently-read display list, we need to do
  104. - * something like disable scanout before putting in the new
  105. - * list. For now, we're safe because we only have the two
  106. - * planes.
  107. - */
  108. + /* Copy all the active planes' dlist contents to the hardware dlist. */
  109. drm_atomic_crtc_for_each_plane(plane, crtc) {
  110. dlist_next += vc4_plane_write_dlist(plane, dlist_next);
  111. }
  112. - if (dlist_next == vc4_crtc->dlist) {
  113. - /* If no planes were enabled, use the SCALER_CTL0_END
  114. - * at the start of the display list memory (in the
  115. - * bootloader section). We'll rewrite that
  116. - * SCALER_CTL0_END, just in case, though.
  117. - */
  118. - writel(SCALER_CTL0_END, vc4->hvs->dlist);
  119. - HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 0);
  120. - } else {
  121. - writel(SCALER_CTL0_END, dlist_next);
  122. - dlist_next++;
  123. -
  124. - HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
  125. - (u32 __iomem *)vc4_crtc->dlist -
  126. - (u32 __iomem *)vc4->hvs->dlist);
  127. -
  128. - /* Make the next display list start after ours. */
  129. - vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist);
  130. - vc4_crtc->dlist = dlist_next;
  131. - }
  132. + writel(SCALER_CTL0_END, dlist_next);
  133. + dlist_next++;
  134. +
  135. + WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
  136. +
  137. + HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
  138. + vc4_state->mm.start);
  139. if (debug_dump_regs) {
  140. DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
  141. @@ -573,6 +556,36 @@ static int vc4_page_flip(struct drm_crtc
  142. return drm_atomic_helper_page_flip(crtc, fb, event, flags);
  143. }
  144. +static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
  145. +{
  146. + struct vc4_crtc_state *vc4_state;
  147. +
  148. + vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
  149. + if (!vc4_state)
  150. + return NULL;
  151. +
  152. + __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
  153. + return &vc4_state->base;
  154. +}
  155. +
  156. +static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
  157. + struct drm_crtc_state *state)
  158. +{
  159. + struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
  160. + struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
  161. +
  162. + if (vc4_state->mm.allocated) {
  163. + unsigned long flags;
  164. +
  165. + spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
  166. + drm_mm_remove_node(&vc4_state->mm);
  167. + spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
  168. +
  169. + }
  170. +
  171. + __drm_atomic_helper_crtc_destroy_state(crtc, state);
  172. +}
  173. +
  174. static const struct drm_crtc_funcs vc4_crtc_funcs = {
  175. .set_config = drm_atomic_helper_set_config,
  176. .destroy = vc4_crtc_destroy,
  177. @@ -581,8 +594,8 @@ static const struct drm_crtc_funcs vc4_c
  178. .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
  179. .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
  180. .reset = drm_atomic_helper_crtc_reset,
  181. - .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  182. - .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  183. + .atomic_duplicate_state = vc4_crtc_duplicate_state,
  184. + .atomic_destroy_state = vc4_crtc_destroy_state,
  185. };
  186. static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
  187. --- a/drivers/gpu/drm/vc4/vc4_drv.h
  188. +++ b/drivers/gpu/drm/vc4/vc4_drv.h
  189. @@ -150,7 +150,13 @@ struct vc4_v3d {
  190. struct vc4_hvs {
  191. struct platform_device *pdev;
  192. void __iomem *regs;
  193. - void __iomem *dlist;
  194. + u32 __iomem *dlist;
  195. +
  196. + /* Memory manager for CRTCs to allocate space in the display
  197. + * list. Units are dwords.
  198. + */
  199. + struct drm_mm dlist_mm;
  200. + spinlock_t mm_lock;
  201. };
  202. struct vc4_plane {
  203. --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  204. +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  205. @@ -119,6 +119,17 @@ static int vc4_hvs_bind(struct device *d
  206. hvs->dlist = hvs->regs + SCALER_DLIST_START;
  207. + spin_lock_init(&hvs->mm_lock);
  208. +
  209. + /* Set up the HVS display list memory manager. We never
  210. + * overwrite the setup from the bootloader (just 128b out of
  211. + * our 16K), since we don't want to scramble the screen when
  212. + * transitioning from the firmware's boot setup to runtime.
  213. + */
  214. + drm_mm_init(&hvs->dlist_mm,
  215. + HVS_BOOTLOADER_DLIST_END,
  216. + (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END);
  217. +
  218. vc4->hvs = hvs;
  219. return 0;
  220. }
  221. @@ -129,6 +140,8 @@ static void vc4_hvs_unbind(struct device
  222. struct drm_device *drm = dev_get_drvdata(master);
  223. struct vc4_dev *vc4 = drm->dev_private;
  224. + drm_mm_takedown(&vc4->hvs->dlist_mm);
  225. +
  226. vc4->hvs = NULL;
  227. }