0288-drm-vc4-Bring-HDMI-up-from-power-off-if-necessary.patch 2.3 KB

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  1. From b90794bb85c90b4276fea302cf75251021134e7a Mon Sep 17 00:00:00 2001
  2. From: Eric Anholt <eric@anholt.net>
  3. Date: Fri, 12 Feb 2016 14:15:14 -0800
  4. Subject: [PATCH 288/381] drm/vc4: Bring HDMI up from power off if necessary.
  5. If the firmware hadn't brought up HDMI for us, we need to do its
  6. power-on reset sequence (reset HD and and clear its STANDBY bits,
  7. reset HDMI, and leave the PHY disabled).
  8. Signed-off-by: Eric Anholt <eric@anholt.net>
  9. (cherry picked from commit 851479ad5927b7b1aa141ca9dedb897a7bce2b1d)
  10. ---
  11. drivers/gpu/drm/vc4/vc4_hdmi.c | 29 ++++++++++++++++++++++++++++-
  12. drivers/gpu/drm/vc4/vc4_regs.h | 2 ++
  13. 2 files changed, 30 insertions(+), 1 deletion(-)
  14. --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  15. +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  16. @@ -497,6 +497,16 @@ static int vc4_hdmi_bind(struct device *
  17. goto err_put_i2c;
  18. }
  19. + /* This is the rate that is set by the firmware. The number
  20. + * needs to be a bit higher than the pixel clock rate
  21. + * (generally 148.5Mhz).
  22. + */
  23. + ret = clk_set_rate(hdmi->hsm_clock, 163682864);
  24. + if (ret) {
  25. + DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
  26. + goto err_unprepare_pix;
  27. + }
  28. +
  29. ret = clk_prepare_enable(hdmi->hsm_clock);
  30. if (ret) {
  31. DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
  32. @@ -518,7 +528,24 @@ static int vc4_hdmi_bind(struct device *
  33. vc4->hdmi = hdmi;
  34. /* HDMI core must be enabled. */
  35. - WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0);
  36. + if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
  37. + HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
  38. + udelay(1);
  39. + HD_WRITE(VC4_HD_M_CTL, 0);
  40. +
  41. + HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
  42. +
  43. + HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
  44. + VC4_HDMI_SW_RESET_HDMI |
  45. + VC4_HDMI_SW_RESET_FORMAT_DETECT);
  46. +
  47. + HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
  48. +
  49. + /* PHY should be in reset, like
  50. + * vc4_hdmi_encoder_disable() does.
  51. + */
  52. + HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
  53. + }
  54. drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
  55. DRM_MODE_ENCODER_TMDS);
  56. --- a/drivers/gpu/drm/vc4/vc4_regs.h
  57. +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  58. @@ -456,6 +456,8 @@
  59. #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
  60. #define VC4_HD_M_CTL 0x00c
  61. +# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
  62. +# define VC4_HD_M_RAM_STANDBY (3 << 4)
  63. # define VC4_HD_M_SW_RST BIT(2)
  64. # define VC4_HD_M_ENABLE BIT(0)