0290-drm-vc4-Fix-the-name-of-the-VSYNCD_EVEN-register.patch 1.1 KB

123456789101112131415161718192021222324252627282930313233343536
  1. From 659c32d3344952ef9c49a18d512318e5dca9eff3 Mon Sep 17 00:00:00 2001
  2. From: Eric Anholt <eric@anholt.net>
  3. Date: Mon, 15 Feb 2016 17:06:02 -0800
  4. Subject: [PATCH 290/381] drm/vc4: Fix the name of the VSYNCD_EVEN register.
  5. It's used for delaying vsync in interlaced mode.
  6. Signed-off-by: Eric Anholt <eric@anholt.net>
  7. (cherry picked from commit c31806fbdda910d337b60896040afa708bdfa2bd)
  8. ---
  9. drivers/gpu/drm/vc4/vc4_crtc.c | 2 +-
  10. drivers/gpu/drm/vc4/vc4_regs.h | 2 +-
  11. 2 files changed, 2 insertions(+), 2 deletions(-)
  12. --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  13. +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  14. @@ -88,7 +88,7 @@ static const struct {
  15. } crtc_regs[] = {
  16. CRTC_REG(PV_CONTROL),
  17. CRTC_REG(PV_V_CONTROL),
  18. - CRTC_REG(PV_VSYNCD),
  19. + CRTC_REG(PV_VSYNCD_EVEN),
  20. CRTC_REG(PV_HORZA),
  21. CRTC_REG(PV_HORZB),
  22. CRTC_REG(PV_VERTA),
  23. --- a/drivers/gpu/drm/vc4/vc4_regs.h
  24. +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  25. @@ -187,7 +187,7 @@
  26. # define PV_VCONTROL_CONTINUOUS BIT(1)
  27. # define PV_VCONTROL_VIDEN BIT(0)
  28. -#define PV_VSYNCD 0x08
  29. +#define PV_VSYNCD_EVEN 0x08
  30. #define PV_HORZA 0x0c
  31. # define PV_HORZA_HBP_MASK VC4_MASK(31, 16)