164-arm-qcom-dts-Add-NAND-controller-node-for-ipq806x.patch 1.4 KB

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  4. Subject: [v3,4/5] arm: qcom: dts: Add NAND controller node for ipq806x
  5. From: Archit Taneja <architt@codeaurora.org>
  6. X-Patchwork-Id: 6927121
  7. Message-Id: <1438578498-32254-5-git-send-email-architt@codeaurora.org>
  8. To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
  9. cernekee@gmail.com, computersforpeace@gmail.com
  10. Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
  11. sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
  12. Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
  13. Date: Mon, 3 Aug 2015 10:38:17 +0530
  14. The nand controller in IPQ806x is of the 'EBI2 type'. Use the corresponding
  15. compatible string.
  16. Cc: devicetree@vger.kernel.org
  17. Reviewed-by: Andy Gross <agross@codeaurora.org>
  18. Signed-off-by: Archit Taneja <architt@codeaurora.org>
  19. ---
  20. arch/arm/boot/dts/qcom-ipq8064.dtsi | 15 +++++++++++++++
  21. 1 file changed, 15 insertions(+)
  22. --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  23. +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  24. @@ -725,6 +725,22 @@
  25. status = "disabled";
  26. };
  27. + nand@1ac00000 {
  28. + compatible = "qcom,ebi2-nandc";
  29. + reg = <0x1ac00000 0x800>;
  30. +
  31. + clocks = <&gcc EBI2_CLK>,
  32. + <&gcc EBI2_AON_CLK>;
  33. + clock-names = "core", "aon";
  34. +
  35. + dmas = <&adm_dma 3>;
  36. + dma-names = "rxtx";
  37. + qcom,cmd-crci = <15>;
  38. + qcom,data-crci = <3>;
  39. +
  40. + status = "disabled";
  41. + };
  42. +
  43. };
  44. sfpb_mutex: sfpb-mutex {