801-ARM-qcom-add-Netgear-Nighthawk-X4-D7800-device-tree.patch 7.1 KB

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  1. --- a/arch/arm/boot/dts/Makefile
  2. +++ b/arch/arm/boot/dts/Makefile
  3. @@ -362,6 +362,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
  4. qcom-ipq8064-ap148.dtb \
  5. qcom-ipq8064-db149.dtb \
  6. qcom-ipq8064-r7500.dtb \
  7. + qcom-ipq8064-d7800.dtb \
  8. qcom-msm8660-surf.dtb \
  9. qcom-msm8960-cdp.dtb \
  10. qcom-msm8974-sony-xperia-honami.dtb
  11. --- /dev/null
  12. +++ b/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
  13. @@ -0,0 +1,368 @@
  14. +#include "qcom-ipq8064-v1.0.dtsi"
  15. +
  16. +#include <dt-bindings/input/input.h>
  17. +
  18. +/ {
  19. + model = "Netgear Nighthawk X4 D7800";
  20. + compatible = "netgear,d7800", "qcom,ipq8064";
  21. +
  22. + memory@0 {
  23. + reg = <0x42000000 0xe000000>;
  24. + device_type = "memory";
  25. + };
  26. +
  27. + reserved-memory {
  28. + #address-cells = <1>;
  29. + #size-cells = <1>;
  30. + ranges;
  31. + rsvd@41200000 {
  32. + reg = <0x41200000 0x300000>;
  33. + no-map;
  34. + };
  35. + };
  36. +
  37. + aliases {
  38. + serial0 = &uart4;
  39. + mdio-gpio0 = &mdio0;
  40. + };
  41. +
  42. + chosen {
  43. + bootargs = "rootfstype=squashfs noinitrd";
  44. + linux,stdout-path = "serial0:115200n8";
  45. + };
  46. +
  47. + soc {
  48. + pinmux@800000 {
  49. + i2c4_pins: i2c4_pinmux {
  50. + pins = "gpio12", "gpio13";
  51. + function = "gsbi4";
  52. + bias-disable;
  53. + };
  54. +
  55. + pcie0_pins: pcie0_pinmux {
  56. + mux {
  57. + pins = "gpio3";
  58. + function = "pcie1_rst";
  59. + drive-strength = <12>;
  60. + bias-disable;
  61. + };
  62. + };
  63. +
  64. + pcie1_pins: pcie1_pinmux {
  65. + mux {
  66. + pins = "gpio48";
  67. + function = "pcie2_rst";
  68. + drive-strength = <12>;
  69. + bias-disable;
  70. + };
  71. + };
  72. +
  73. + nand_pins: nand_pins {
  74. + mux {
  75. + pins = "gpio34", "gpio35", "gpio36",
  76. + "gpio37", "gpio38", "gpio39",
  77. + "gpio40", "gpio41", "gpio42",
  78. + "gpio43", "gpio44", "gpio45",
  79. + "gpio46", "gpio47";
  80. + function = "nand";
  81. + drive-strength = <10>;
  82. + bias-disable;
  83. + };
  84. + pullups {
  85. + pins = "gpio39";
  86. + bias-pull-up;
  87. + };
  88. + hold {
  89. + pins = "gpio40", "gpio41", "gpio42",
  90. + "gpio43", "gpio44", "gpio45",
  91. + "gpio46", "gpio47";
  92. + bias-bus-hold;
  93. + };
  94. + };
  95. +
  96. + mdio0_pins: mdio0_pins {
  97. + mux {
  98. + pins = "gpio0", "gpio1";
  99. + function = "gpio";
  100. + drive-strength = <8>;
  101. + bias-disable;
  102. + };
  103. + };
  104. +
  105. + rgmii2_pins: rgmii2_pins {
  106. + mux {
  107. + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
  108. + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
  109. + function = "rgmii2";
  110. + drive-strength = <8>;
  111. + bias-disable;
  112. + };
  113. + };
  114. + };
  115. +
  116. + gsbi@16300000 {
  117. + qcom,mode = <GSBI_PROT_I2C_UART>;
  118. + status = "ok";
  119. + serial@16340000 {
  120. + status = "ok";
  121. + };
  122. + /*
  123. + * The i2c device on gsbi4 should not be enabled.
  124. + * On ipq806x designs gsbi4 i2c is meant for exclusive
  125. + * RPM usage. Turning this on in kernel manifests as
  126. + * i2c failure for the RPM.
  127. + */
  128. + };
  129. +
  130. + sata-phy@1b400000 {
  131. + status = "ok";
  132. + };
  133. +
  134. + sata@29000000 {
  135. + status = "ok";
  136. + };
  137. +
  138. + phy@100f8800 { /* USB3 port 1 HS phy */
  139. + status = "ok";
  140. + };
  141. +
  142. + phy@100f8830 { /* USB3 port 1 SS phy */
  143. + status = "ok";
  144. + };
  145. +
  146. + phy@110f8800 { /* USB3 port 0 HS phy */
  147. + status = "ok";
  148. + };
  149. +
  150. + phy@110f8830 { /* USB3 port 0 SS phy */
  151. + status = "ok";
  152. + };
  153. +
  154. + usb30@0 {
  155. + status = "ok";
  156. + };
  157. +
  158. + usb30@1 {
  159. + status = "ok";
  160. + };
  161. +
  162. + pcie0: pci@1b500000 {
  163. + status = "ok";
  164. + reset-gpio = <&qcom_pinmux 3 0>;
  165. + pinctrl-0 = <&pcie0_pins>;
  166. + pinctrl-names = "default";
  167. + };
  168. +
  169. + pcie1: pci@1b700000 {
  170. + status = "ok";
  171. + reset-gpio = <&qcom_pinmux 48 0>;
  172. + pinctrl-0 = <&pcie1_pins>;
  173. + pinctrl-names = "default";
  174. + };
  175. +
  176. + nand@1ac00000 {
  177. + status = "ok";
  178. +
  179. + pinctrl-0 = <&nand_pins>;
  180. + pinctrl-names = "default";
  181. +
  182. + nand-ecc-strength = <4>;
  183. + nand-bus-width = <8>;
  184. +
  185. + #address-cells = <1>;
  186. + #size-cells = <1>;
  187. +
  188. + qcadata@0 {
  189. + label = "qcadata";
  190. + reg = <0x0000000 0x0c80000>;
  191. + read-only;
  192. + };
  193. +
  194. + APPSBL@c80000 {
  195. + label = "APPSBL";
  196. + reg = <0x0c80000 0x0500000>;
  197. + read-only;
  198. + };
  199. +
  200. + APPSBLENV@1180000 {
  201. + label = "APPSBLENV";
  202. + reg = <0x1180000 0x0080000>;
  203. + read-only;
  204. + };
  205. +
  206. + art: art@1200000 {
  207. + label = "art";
  208. + reg = <0x1200000 0x0140000>;
  209. + read-only;
  210. + };
  211. +
  212. + artbak: art@1340000 {
  213. + label = "artbak";
  214. + reg = <0x1340000 0x0140000>;
  215. + read-only;
  216. + };
  217. +
  218. + kernel@1480000 {
  219. + label = "kernel";
  220. + reg = <0x1480000 0x0200000>;
  221. + };
  222. +
  223. + ubi@1680000 {
  224. + label = "ubi";
  225. + reg = <0x1680000 0x1E00000>;
  226. + };
  227. +
  228. + netgear@3480000 {
  229. + label = "netgear";
  230. + reg = <0x3480000 0x4480000>;
  231. + read-only;
  232. + };
  233. +
  234. + reserve@7900000 {
  235. + label = "reserve";
  236. + reg = <0x7900000 0x0700000>;
  237. + read-only;
  238. + };
  239. +
  240. + firmware@1480000 {
  241. + label = "firmware";
  242. + reg = <0x1480000 0x2000000>;
  243. + };
  244. +
  245. + };
  246. +
  247. + mdio0: mdio {
  248. + compatible = "virtual,mdio-gpio";
  249. + #address-cells = <1>;
  250. + #size-cells = <0>;
  251. + gpios = <&qcom_pinmux 1 0 &qcom_pinmux 0 0>;
  252. + pinctrl-0 = <&mdio0_pins>;
  253. + pinctrl-names = "default";
  254. +
  255. + phy0: ethernet-phy@0 {
  256. + device_type = "ethernet-phy";
  257. + reg = <0>;
  258. + qca,ar8327-initvals = <
  259. + 0x00004 0x7600000 /* PAD0_MODE */
  260. + 0x00008 0x1000000 /* PAD5_MODE */
  261. + 0x0000c 0x80 /* PAD6_MODE */
  262. + 0x000e4 0xaa545 /* MAC_POWER_SEL */
  263. + 0x000e0 0xc74164de /* SGMII_CTRL */
  264. + 0x0007c 0x4e /* PORT0_STATUS */
  265. + 0x00094 0x4e /* PORT6_STATUS */
  266. + >;
  267. + };
  268. +
  269. + phy4: ethernet-phy@4 {
  270. + device_type = "ethernet-phy";
  271. + reg = <4>;
  272. + };
  273. + };
  274. +
  275. + gmac1: ethernet@37200000 {
  276. + status = "ok";
  277. + phy-mode = "rgmii";
  278. + phy-handle = <&phy4>;
  279. + qcom,id = <1>;
  280. +
  281. + pinctrl-0 = <&rgmii2_pins>;
  282. + pinctrl-names = "default";
  283. +
  284. + mtd-mac-address = <&art 6>;
  285. + };
  286. +
  287. + gmac2: ethernet@37400000 {
  288. + status = "ok";
  289. + phy-mode = "sgmii";
  290. + qcom,id = <2>;
  291. +
  292. + mtd-mac-address = <&art 0>;
  293. +
  294. + fixed-link {
  295. + speed = <1000>;
  296. + full-duplex;
  297. + };
  298. + };
  299. + };
  300. +
  301. + gpio-keys {
  302. + compatible = "gpio-keys";
  303. +
  304. + wifi {
  305. + label = "wifi";
  306. + gpios = <&qcom_pinmux 6 1>;
  307. + linux,code = <KEY_WLAN>;
  308. + };
  309. +
  310. + reset {
  311. + label = "reset";
  312. + gpios = <&qcom_pinmux 54 1>;
  313. + linux,code = <KEY_RESTART>;
  314. + };
  315. +
  316. + wps {
  317. + label = "wps";
  318. + gpios = <&qcom_pinmux 65 1>;
  319. + linux,code = <KEY_WPS_BUTTON>;
  320. + };
  321. + };
  322. +
  323. + gpio-leds {
  324. + compatible = "gpio-leds";
  325. +
  326. + usb1 {
  327. + label = "d7800:amber:usb1";
  328. + gpios = <&qcom_pinmux 7 0>;
  329. + };
  330. +
  331. + usb3 {
  332. + label = "d7800:amber:usb3";
  333. + gpios = <&qcom_pinmux 8 0>;
  334. + };
  335. +
  336. + status {
  337. + label = "d7800:amber:status";
  338. + gpios = <&qcom_pinmux 9 0>;
  339. + };
  340. +
  341. + internet {
  342. + label = "d7800:white:internet";
  343. + gpios = <&qcom_pinmux 22 0>;
  344. + };
  345. +
  346. + wan {
  347. + label = "d7800:white:wan";
  348. + gpios = <&qcom_pinmux 23 0>;
  349. + };
  350. +
  351. + wps {
  352. + label = "d7800:white:wps";
  353. + gpios = <&qcom_pinmux 24 0>;
  354. + };
  355. +
  356. + esata {
  357. + label = "d7800:white:esata";
  358. + gpios = <&qcom_pinmux 26 0>;
  359. + };
  360. +
  361. + power {
  362. + label = "d7800:white:power";
  363. + gpios = <&qcom_pinmux 53 0>;
  364. + default-state = "on";
  365. + };
  366. +
  367. + rfkill {
  368. + label = "d7800:white:rfkill";
  369. + gpios = <&qcom_pinmux 64 0>;
  370. + };
  371. +
  372. + wifi5g {
  373. + label = "d7800:white:wifi5g";
  374. + gpios = <&qcom_pinmux 67 0>;
  375. + };
  376. + };
  377. +};
  378. +
  379. +&adm_dma {
  380. + status = "ok";
  381. +};