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- From f26cc3733bdd697bd81ae505fc133fa7c9b6ea19 Mon Sep 17 00:00:00 2001
- From: Mathieu Olivari <mathieu@codeaurora.org>
- Date: Tue, 7 Apr 2015 19:58:58 -0700
- Subject: [PATCH] ARM: dts: qcom: add initial DB149 device-tree
- Add basic DB149 (IPQ806x based platform) device-tree. It supports UART,
- SATA, USB2, USB3 and NOR flash.
- Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
- ---
- arch/arm/boot/dts/Makefile | 1 +
- arch/arm/boot/dts/qcom-ipq8064-db149.dts | 132 +++++++++++++++++++++++++++++++
- 2 files changed, 133 insertions(+)
- create mode 100644 arch/arm/boot/dts/qcom-ipq8064-db149.dts
- --- a/arch/arm/boot/dts/Makefile
- +++ b/arch/arm/boot/dts/Makefile
- @@ -506,6 +506,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
- qcom-apq8084-ifc6540.dtb \
- qcom-apq8084-mtp.dtb \
- qcom-ipq8064-ap148.dtb \
- + qcom-ipq8064-db149.dtb \
- qcom-msm8660-surf.dtb \
- qcom-msm8960-cdp.dtb \
- qcom-msm8974-sony-xperia-honami.dtb
- --- /dev/null
- +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
- @@ -0,0 +1,132 @@
- +#include "qcom-ipq8064-v1.0.dtsi"
- +
- +/ {
- + model = "Qualcomm IPQ8064/DB149";
- + compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
- +
- + reserved-memory {
- + #address-cells = <1>;
- + #size-cells = <1>;
- + ranges;
- + rsvd@41200000 {
- + reg = <0x41200000 0x300000>;
- + no-map;
- + };
- + };
- +
- + alias {
- + serial0 = &uart2;
- + };
- +
- + chosen {
- + linux,stdout-path = "serial0:115200n8";
- + };
- +
- + soc {
- + pinmux@800000 {
- + i2c4_pins: i2c4_pinmux {
- + pins = "gpio12", "gpio13";
- + function = "gsbi4";
- + bias-disable;
- + };
- +
- + spi_pins: spi_pins {
- + mux {
- + pins = "gpio18", "gpio19", "gpio21";
- + function = "gsbi5";
- + drive-strength = <10>;
- + bias-none;
- + };
- + };
- + };
- +
- + gsbi2: gsbi@12480000 {
- + qcom,mode = <GSBI_PROT_I2C_UART>;
- + status = "ok";
- + uart2: serial@12490000 {
- + status = "ok";
- + };
- + };
- +
- + gsbi5: gsbi@1a200000 {
- + qcom,mode = <GSBI_PROT_SPI>;
- + status = "ok";
- +
- + spi4: spi@1a280000 {
- + status = "ok";
- + spi-max-frequency = <50000000>;
- +
- + pinctrl-0 = <&spi_pins>;
- + pinctrl-names = "default";
- +
- + cs-gpios = <&qcom_pinmux 20 0>;
- +
- + flash: m25p80@0 {
- + compatible = "s25fl256s1";
- + #address-cells = <1>;
- + #size-cells = <1>;
- + spi-max-frequency = <50000000>;
- + reg = <0>;
- + m25p,fast-read;
- +
- + partition@0 {
- + label = "lowlevel_init";
- + reg = <0x0 0x1b0000>;
- + };
- +
- + partition@1 {
- + label = "u-boot";
- + reg = <0x1b0000 0x80000>;
- + };
- +
- + partition@2 {
- + label = "u-boot-env";
- + reg = <0x230000 0x40000>;
- + };
- +
- + partition@3 {
- + label = "caldata";
- + reg = <0x270000 0x40000>;
- + };
- +
- + partition@4 {
- + label = "firmware";
- + reg = <0x2b0000 0x1d50000>;
- + };
- + };
- + };
- + };
- +
- + sata-phy@1b400000 {
- + status = "ok";
- + };
- +
- + sata@29000000 {
- + status = "ok";
- + };
- +
- + phy@100f8800 { /* USB3 port 1 HS phy */
- + status = "ok";
- + };
- +
- + phy@100f8830 { /* USB3 port 1 SS phy */
- + status = "ok";
- + };
- +
- + phy@110f8800 { /* USB3 port 0 HS phy */
- + status = "ok";
- + };
- +
- + phy@110f8830 { /* USB3 port 0 SS phy */
- + status = "ok";
- + };
- +
- + usb30@0 {
- + status = "ok";
- + };
- +
- + usb30@1 {
- + status = "ok";
- + };
- + };
- +};
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