EASY80920.dtsi 6.8 KB

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  1. /include/ "vr9.dtsi"
  2. / {
  3. chosen {
  4. bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
  5. leds {
  6. boot = &power;
  7. failsafe = &power;
  8. running = &power;
  9. usb = &usb1;
  10. usb2 = &usb2;
  11. };
  12. };
  13. memory@0 {
  14. reg = <0x0 0x4000000>;
  15. };
  16. fpi@10000000 {
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. compatible = "lantiq,fpi", "simple-bus";
  20. ranges = <0x0 0x10000000 0xEEFFFFF>;
  21. reg = <0x10000000 0xEF00000>;
  22. localbus@0 {
  23. #address-cells = <2>;
  24. #size-cells = <1>;
  25. compatible = "lantiq,localbus", "simple-bus";
  26. };
  27. gpio: pinmux@E100B10 {
  28. compatible = "lantiq,pinctrl-xr9";
  29. pinctrl-names = "default";
  30. pinctrl-0 = <&state_default>;
  31. interrupt-parent = <&icu0>;
  32. interrupts = <166 135 66 40 41 42 38>;
  33. #gpio-cells = <2>;
  34. gpio-controller;
  35. reg = <0xE100B10 0xA0>;
  36. state_default: pinmux {
  37. exin3 {
  38. lantiq,groups = "exin3";
  39. lantiq,function = "exin";
  40. };
  41. stp {
  42. lantiq,groups = "stp";
  43. lantiq,function = "stp";
  44. };
  45. nand {
  46. lantiq,groups = "nand cle", "nand ale",
  47. "nand rd", "nand rdy";
  48. lantiq,function = "ebu";
  49. };
  50. mdio {
  51. lantiq,groups = "mdio";
  52. lantiq,function = "mdio";
  53. };
  54. pci {
  55. lantiq,groups = "gnt1", "req1";
  56. lantiq,function = "pci";
  57. };
  58. conf_out {
  59. lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
  60. "io4", "io5", "io6", /* stp */
  61. "io21",
  62. "io33";
  63. lantiq,open-drain;
  64. lantiq,pull = <0>;
  65. lantiq,output = <1>;
  66. };
  67. pcie-rst {
  68. lantiq,pins = "io38";
  69. lantiq,pull = <0>;
  70. lantiq,output = <1>;
  71. };
  72. conf_in {
  73. lantiq,pins = "io39", /* exin3 */
  74. "io48"; /* nand rdy */
  75. lantiq,pull = <2>;
  76. };
  77. };
  78. pins_spi_default: pins_spi_default {
  79. spi_in {
  80. lantiq,groups = "spi_di";
  81. lantiq,function = "spi";
  82. };
  83. spi_out {
  84. lantiq,groups = "spi_do", "spi_clk",
  85. "spi_cs4";
  86. lantiq,function = "spi";
  87. lantiq,output = <1>;
  88. };
  89. };
  90. };
  91. stp: stp@E100BB0 {
  92. compatible = "lantiq,gpio-stp-xway";
  93. reg = <0xE100BB0 0x40>;
  94. #gpio-cells = <2>;
  95. gpio-controller;
  96. lantiq,shadow = <0xffff>;
  97. lantiq,groups = <0x7>;
  98. lantiq,dsl = <0x3>;
  99. lantiq,phy1 = <0x7>;
  100. lantiq,phy2 = <0x7>;
  101. /* lantiq,rising; */
  102. };
  103. ifxhcd@E101000 {
  104. status = "okay";
  105. gpios = <&gpio 33 0>;
  106. lantiq,portmask = <0x3>;
  107. };
  108. pci@E105400 {
  109. #address-cells = <3>;
  110. #size-cells = <2>;
  111. #interrupt-cells = <1>;
  112. compatible = "lantiq,pci-xway1";
  113. bus-range = <0x0 0x0>;
  114. ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
  115. 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
  116. reg = <0x7000000 0x8000 /* config space */
  117. 0xE105400 0x400>; /* pci bridge */
  118. lantiq,bus-clock = <33333333>;
  119. /*lantiq,external-clock;*/
  120. lantiq,delay-hi = <0>; /* 0ns delay */
  121. lantiq,delay-lo = <0>; /* 0.0ns delay */
  122. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  123. interrupt-map = <
  124. 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
  125. >;
  126. gpios-reset = <&gpio 21 0>;
  127. req-mask = <0x1>; /* GNT1 */
  128. };
  129. };
  130. gphy-xrx200 {
  131. compatible = "lantiq,phy-xrx200";
  132. firmware1 = "lantiq/vr9_phy11g_a1x.bin";
  133. firmware2 = "lantiq/vr9_phy11g_a2x.bin";
  134. phys = [ 00 01 ];
  135. };
  136. gpio-keys-polled {
  137. compatible = "gpio-keys-polled";
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. poll-interval = <100>;
  141. /* reset {
  142. label = "reset";
  143. gpios = <&gpio 7 1>;
  144. linux,code = <0x198>;
  145. };*/
  146. paging {
  147. label = "paging";
  148. gpios = <&gpio 11 1>;
  149. linux,code = <0x100>;
  150. };
  151. };
  152. gpio-leds {
  153. compatible = "gpio-leds";
  154. power: power {
  155. label = "easy80920:green:power";
  156. gpios = <&stp 9 0>;
  157. default-state = "keep";
  158. };
  159. warning {
  160. label = "easy80920:green:warning";
  161. gpios = <&stp 22 0>;
  162. };
  163. fxs1 {
  164. label = "easy80920:green:fxs1";
  165. gpios = <&stp 21 0>;
  166. };
  167. fxs2 {
  168. label = "easy80920:green:fxs2";
  169. gpios = <&stp 20 0>;
  170. };
  171. fxo {
  172. label = "easy80920:green:fxo";
  173. gpios = <&stp 19 0>;
  174. };
  175. usb1: usb1 {
  176. label = "easy80920:green:usb1";
  177. gpios = <&stp 18 0>;
  178. };
  179. usb2: usb2 {
  180. label = "easy80920:green:usb2";
  181. gpios = <&stp 15 0>;
  182. };
  183. sd {
  184. label = "easy80920:green:sd";
  185. gpios = <&stp 14 0>;
  186. };
  187. wps {
  188. label = "easy80920:green:wps";
  189. gpios = <&stp 12 0>;
  190. };
  191. };
  192. };
  193. &spi {
  194. pinctrl-names = "default";
  195. pinctrl-0 = <&pins_spi_default>;
  196. status = "ok";
  197. m25p80@4 {
  198. #address-cells = <1>;
  199. #size-cells = <1>;
  200. compatible = "jedec,spi-nor";
  201. reg = <4 0>;
  202. spi-max-frequency = <1000000>;
  203. partitions {
  204. compatible = "fixed-partitions";
  205. #address-cells = <1>;
  206. #size-cells = <1>;
  207. partition@0 {
  208. reg = <0x0 0x20000>;
  209. label = "SPI (RO) U-Boot Image";
  210. read-only;
  211. };
  212. partition@20000 {
  213. reg = <0x20000 0x10000>;
  214. label = "ENV_MAC";
  215. read-only;
  216. };
  217. partition@30000 {
  218. reg = <0x30000 0x10000>;
  219. label = "DPF";
  220. read-only;
  221. };
  222. partition@40000 {
  223. reg = <0x40000 0x10000>;
  224. label = "NVRAM";
  225. read-only;
  226. };
  227. partition@500000 {
  228. reg = <0x50000 0x003a0000>;
  229. label = "kernel";
  230. };
  231. };
  232. };
  233. };
  234. &eth0 {
  235. lan: interface@0 {
  236. compatible = "lantiq,xrx200-pdi";
  237. #address-cells = <1>;
  238. #size-cells = <0>;
  239. reg = <0>;
  240. mac-address = [ 00 11 22 33 44 55 ];
  241. ethernet@0 {
  242. compatible = "lantiq,xrx200-pdi-port";
  243. reg = <0>;
  244. phy-mode = "rgmii";
  245. phy-handle = <&phy0>;
  246. };
  247. ethernet@1 {
  248. compatible = "lantiq,xrx200-pdi-port";
  249. reg = <1>;
  250. phy-mode = "rgmii";
  251. phy-handle = <&phy1>;
  252. };
  253. ethernet@2 {
  254. compatible = "lantiq,xrx200-pdi-port";
  255. reg = <2>;
  256. phy-mode = "gmii";
  257. phy-handle = <&phy11>;
  258. };
  259. };
  260. wan: interface@1 {
  261. compatible = "lantiq,xrx200-pdi";
  262. #address-cells = <1>;
  263. #size-cells = <0>;
  264. reg = <1>;
  265. mac-address = [ 00 11 22 33 44 56 ];
  266. lantiq,wan;
  267. ethernet@5 {
  268. compatible = "lantiq,xrx200-pdi-port";
  269. reg = <5>;
  270. phy-mode = "rgmii";
  271. phy-handle = <&phy5>;
  272. };
  273. };
  274. test: interface@2 {
  275. compatible = "lantiq,xrx200-pdi";
  276. #address-cells = <1>;
  277. #size-cells = <0>;
  278. reg = <2>;
  279. mac-address = [ 00 11 22 33 44 57 ];
  280. ethernet@4 {
  281. compatible = "lantiq,xrx200-pdi-port";
  282. reg = <4>;
  283. phynmode0 = "gmii";
  284. phy-handle = <&phy13>;
  285. };
  286. };
  287. mdio@0 {
  288. #address-cells = <1>;
  289. #size-cells = <0>;
  290. compatible = "lantiq,xrx200-mdio";
  291. phy0: ethernet-phy@0 {
  292. reg = <0x0>;
  293. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  294. };
  295. phy1: ethernet-phy@1 {
  296. reg = <0x1>;
  297. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  298. };
  299. phy5: ethernet-phy@5 {
  300. reg = <0x5>;
  301. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  302. };
  303. phy11: ethernet-phy@11 {
  304. reg = <0x11>;
  305. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  306. };
  307. phy13: ethernet-phy@13 {
  308. reg = <0x13>;
  309. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  310. };
  311. };
  312. };