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- --- a/arch/mips/lantiq/xway/sysctrl.c
- +++ b/arch/mips/lantiq/xway/sysctrl.c
- @@ -423,6 +423,20 @@ static void clkdev_add_clkout(void)
- }
- }
-
- +static void set_phy_clock_source(struct device_node *np_cgu)
- +{
- + u32 phy_clk_src, ifcc;
- +
- + if (!np_cgu)
- + return;
- +
- + if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
- + return;
- +
- + ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
- + ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
- +}
- +
- /* bring up all register ranges that we need for basic system control */
- void __init ltq_soc_init(void)
- {
- @@ -608,4 +622,6 @@ void __init ltq_soc_init(void)
-
- if (of_machine_is_compatible("lantiq,vr9"))
- xbar_fpi_burst_disable();
- +
- + set_phy_clock_source(np_cgu);
- }
|
