DIR-620-D1.dts 1.5 KB

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  1. /dts-v1/;
  2. #include "rt3352.dtsi"
  3. / {
  4. compatible = "DIR-620-D1", "ralink,rt3352-soc";
  5. model = "D-Link DIR-620 D1";
  6. gpio-leds {
  7. compatible = "gpio-leds";
  8. status {
  9. label = "dir-620-d1:green:status";
  10. gpios = <&gpio0 9 1>;
  11. };
  12. wifi {
  13. label = "dir-620-d1:green:wifi";
  14. gpios = <&gpio0 17 1>;
  15. };
  16. };
  17. gpio-keys-polled {
  18. compatible = "gpio-keys-polled";
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. poll-interval = <20>;
  22. reset_wps {
  23. label = "reset_wps";
  24. gpios = <&gpio0 7 1>;
  25. linux,code = <0x198>;
  26. };
  27. };
  28. };
  29. &spi0 {
  30. status = "okay";
  31. m25p80@0 {
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. compatible = "jedec,spi-nor";
  35. reg = <0>;
  36. linux,modalias = "m25p80", "mx25l6405d";
  37. spi-max-frequency = <10000000>;
  38. partition@0 {
  39. label = "u-boot";
  40. reg = <0x0 0x30000>;
  41. read-only;
  42. };
  43. partition@30000 {
  44. label = "u-boot-env";
  45. reg = <0x30000 0x10000>;
  46. read-only;
  47. };
  48. factory: partition@40000 {
  49. label = "factory";
  50. reg = <0x40000 0x10000>;
  51. read-only;
  52. };
  53. partition@50000 {
  54. label = "firmware";
  55. reg = <0x50000 0x7b0000>;
  56. };
  57. };
  58. };
  59. &pinctrl {
  60. state_default: pinctrl0 {
  61. gpio {
  62. ralink,group = "i2c", "jtag", "uartf";
  63. ralink,function = "gpio";
  64. };
  65. rgmii {
  66. ralink,group = "rgmii";
  67. ralink,function = "rgmii";
  68. };
  69. mdio {
  70. ralink,group = "mdio";
  71. ralink,function = "mdio";
  72. };
  73. };
  74. };
  75. &ethernet {
  76. mtd-mac-address = <&factory 0x4>;
  77. };
  78. &esw {
  79. mediatek,portmap = <0x2f>;
  80. };
  81. &wmac {
  82. ralink,mtd-eeprom = <&factory 0>;
  83. };
  84. &ehci {
  85. status = "okay";
  86. };
  87. &ohci {
  88. status = "okay";
  89. };