SL-R7205.dts 1.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293
  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. / {
  4. compatible = "SL-R7205", "ralink,rt3052-soc";
  5. model = "Skyline SL-R7205 Wireless 3G Router";
  6. cfi@1f000000 {
  7. compatible = "cfi-flash";
  8. reg = <0x1f000000 0x800000>;
  9. bank-width = <2>;
  10. device-width = <2>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. partition@0 {
  14. label = "u-boot";
  15. reg = <0x0 0x30000>;
  16. read-only;
  17. };
  18. partition@30000 {
  19. label = "u-boot-env";
  20. reg = <0x30000 0x10000>;
  21. read-only;
  22. };
  23. factory: partition@40000 {
  24. label = "factory";
  25. reg = <0x40000 0x10000>;
  26. read-only;
  27. };
  28. partition@50000 {
  29. label = "firmware";
  30. reg = <0x50000 0x3b0000>;
  31. };
  32. };
  33. gpio-leds {
  34. compatible = "gpio-leds";
  35. wifi {
  36. label = "sl-r7205:green:wifi";
  37. gpios = <&gpio0 7 1>;
  38. };
  39. };
  40. gpio-keys-polled {
  41. compatible = "gpio-keys-polled";
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. poll-interval = <20>;
  45. reset {
  46. label = "reset";
  47. gpios = <&gpio0 10 1>;
  48. linux,code = <0x198>;
  49. };
  50. wps {
  51. label = "wps";
  52. gpios = <&gpio0 0 1>;
  53. linux,code = <0x211>;
  54. };
  55. };
  56. };
  57. &pinctrl {
  58. state_default: pinctrl0 {
  59. gpio {
  60. ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
  61. ralink,function = "gpio";
  62. };
  63. };
  64. };
  65. &ethernet {
  66. mtd-mac-address = <&factory 0x4>;
  67. };
  68. &esw {
  69. mediatek,portmap = <0x3e>;
  70. };
  71. &wmac {
  72. ralink,mtd-eeprom = <&factory 0>;
  73. };
  74. &otg {
  75. status = "okay";
  76. };