WIZFI630A.dts 2.8 KB

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  1. /dts-v1/;
  2. #include "rt5350.dtsi"
  3. / {
  4. compatible = "wizfi630a", "ralink,rt5350-soc";
  5. model = "WIZnet WizFi630A";
  6. chosen {
  7. bootargs = "console=ttyS1,115200";
  8. };
  9. gpio-export {
  10. compatible = "gpio-export";
  11. #size-cells = <0>;
  12. };
  13. gpio-leds {
  14. compatible = "gpio-leds";
  15. run {
  16. label = "wizfi630a::run";
  17. gpios = <&gpio0 1 1>;
  18. };
  19. wps {
  20. label = "wizfi630a::wps";
  21. gpios = <&gpio0 20 1>;
  22. };
  23. uart1 {
  24. label = "wizfi630a::uart1";
  25. gpios = <&gpio0 18 1>;
  26. };
  27. uart2 {
  28. label = "wizfi630a::uart2";
  29. gpios = <&gpio0 21 1>;
  30. };
  31. };
  32. gpio-keys-polled {
  33. compatible = "gpio-keys-polled";
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. poll-interval = <20>;
  37. reset {
  38. label = "reset";
  39. gpios = <&gpio0 17 1>;
  40. linux,code = <0x198>;
  41. };
  42. wps {
  43. label = "wps";
  44. gpios = <&gpio0 0 1>;
  45. linux,code = <0x211>;
  46. };
  47. scm1 {
  48. label = "SCM1";
  49. gpios = <&gpio0 19 1>;
  50. linux,code = <0x100>;
  51. };
  52. scm2 {
  53. label = "SCM2";
  54. gpios = <&gpio0 2 1>;
  55. linux,code = <0x101>;
  56. };
  57. };
  58. };
  59. &gpio1 {
  60. status = "okay";
  61. };
  62. &spi0 {
  63. status = "okay";
  64. m25p80@0 {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "jedec,spi-nor";
  68. reg = <0>;
  69. linux,modalias = "m25p80", "w25q128";
  70. spi-max-frequency = <10000000>;
  71. partition@0 {
  72. #size-cells = <1>;
  73. label = "uboot";
  74. reg = <0x0 0x30000>;
  75. read-only;
  76. };
  77. partition@30000 {
  78. #size-cells = <1>;
  79. label = "uboot-env";
  80. reg = <0x30000 0x10000>;
  81. read-only;
  82. };
  83. factory: partition@40000 {
  84. #size-cells = <1>;
  85. label = "factory";
  86. reg = <0x40000 0x10000>;
  87. read-only;
  88. };
  89. partition@50000 {
  90. #size-cells = <1>;
  91. label = "firmware";
  92. reg = <0x50000 0xfb0000>;
  93. };
  94. };
  95. };
  96. &uart {
  97. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  98. reg = <0x500 0x100>;
  99. resets = <&rstctrl 12>;
  100. reset-names = "uart";
  101. interrupt-parent = <&intc>;
  102. interrupts = <5>;
  103. reg-shift = <2>;
  104. pinctrl-names = "default";
  105. pinctrl-0 = <&uartf_pins>;
  106. status = "okay";
  107. };
  108. &uartlite {
  109. compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
  110. reg = <0xc00 0x100>;
  111. resets = <&rstctrl 19>;
  112. reset-names = "uartl";
  113. interrupt-parent = <&intc>;
  114. interrupts = <12>;
  115. reg-shift = <2>;
  116. pinctrl-names = "default";
  117. pinctrl-0 = <&uartlite_pins>;
  118. };
  119. &pinctrl {
  120. state_default: pinctrl0 {
  121. gpio {
  122. ralink,group = "i2c", "jtag" ;
  123. ralink,function = "gpio";
  124. };
  125. };
  126. uartf_gpio_pins: uartf_gpio {
  127. uartf_gpio {
  128. ralink,group = "uartf";
  129. ralink,function = "uartf";
  130. };
  131. };
  132. uartlite_pins: uartlite {
  133. uart {
  134. ralink,group = "uartlite";
  135. ralink,function = "uartlite";
  136. };
  137. };
  138. };
  139. &ethernet {
  140. mtd-mac-address = <&factory 0x4>;
  141. };
  142. &esw {
  143. mediatek,portmap = <0x17>;
  144. };
  145. &wmac {
  146. ralink,mtd-eeprom = <&factory 0>;
  147. };
  148. &ehci {
  149. status = "okay";
  150. };
  151. &ohci {
  152. status = "okay";
  153. };