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126-2-dt-sun5i-add-nand-ctrlpin-defs.patch

126-2-dt-sun5i-add-nand-ctrlpin-defs.patch 2.0 KB
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  1. From a8ad7637cec0c2c2b1322d78b142beea4621dd23 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Hans de Goede <hdegoede@redhat.com>
    3. 

  3. Date: Tue, 26 May 2015 17:18:26 +0200
    4. 

  4. Subject: [PATCH] ARM: dts: sun5i: Add NAND controller pin definitions
    5. 

  5. 

  6. Define the NAND controller pin configs.
    7. 

  7. 

  8. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
    9. 

  9. ---
    10. 

  10.  arch/arm/boot/dts/sun5i-a10s.dtsi | 14 ++++++++++++++
    11. 

  11.  arch/arm/boot/dts/sun5i.dtsi      | 38 ++++++++++++++++++++++++++++++++++++++
    12. 

  12.  2 files changed, 52 insertions(+)
    13. 

  13. 

  14. --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
    15. 

  15. +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
    16. 

  16. @@ -656,4 +656,18 @@
    17. 

  17.  			clocks = <&ahb_gates 28>;
    18. 

  18.  		};
    19. 

  19.  	};
    20. 

  20. +
    21. 

  21. +	nand_cs2_pins_a: nand_cs@2 {
    22. 

  22. +		allwinner,pins = "PC17";
    23. 

  23. +		allwinner,function = "nand0";
    24. 

  24. +		allwinner,drive = <0>;
    25. 

  25. +		allwinner,pull = <0>;
    26. 

  26. +	};
    27. 

  27. +
    28. 

  28. +	nand_cs3_pins_a: nand_cs@3 {
    29. 

  29. +		allwinner,pins = "PC18";
    30. 

  30. +		allwinner,function = "nand0";
    31. 

  31. +		allwinner,drive = <0>;
    32. 

  32. +		allwinner,pull = <0>;
    33. 

  33. +	};
    34. 

  34.  };
    35. 

  35. --- a/arch/arm/boot/dts/sun5i-a13.dtsi
    36. 

  36. +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
    37. 

  37. @@ -528,6 +528,44 @@
    38. 

  38.  				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
    39. 

  39.  				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
    40. 

  40.  			};
    41. 

  41. +
    42. 

  42. +			nand_pins_a: nand_base0@0 {
    43. 

  43. +				allwinner,pins = "PC0", "PC1", "PC2",
    44. 

  44. +						"PC5", "PC8", "PC9", "PC10",
    45. 

  45. +						"PC11", "PC12", "PC13", "PC14",
    46. 

  46. +						"PC15";
    47. 

  47. +				allwinner,function = "nand0";
    48. 

  48. +				allwinner,drive = <0>;
    49. 

  49. +				allwinner,pull = <0>;
    50. 

  50. +			};
    51. 

  51. +
    52. 

  52. +			nand_cs0_pins_a: nand_cs@0 {
    53. 

  53. +				allwinner,pins = "PC4";
    54. 

  54. +				allwinner,function = "nand0";
    55. 

  55. +				allwinner,drive = <0>;
    56. 

  56. +				allwinner,pull = <0>;
    57. 

  57. +			};
    58. 

  58. +
    59. 

  59. +			nand_cs1_pins_a: nand_cs@1 {
    60. 

  60. +				allwinner,pins = "PC3";
    61. 

  61. +				allwinner,function = "nand0";
    62. 

  62. +				allwinner,drive = <0>;
    63. 

  63. +				allwinner,pull = <0>;
    64. 

  64. +			};
    65. 

  65. +
    66. 

  66. +			nand_rb0_pins_a: nand_rb@0 {
    67. 

  67. +				allwinner,pins = "PC6";
    68. 

  68. +				allwinner,function = "nand0";
    69. 

  69. +				allwinner,drive = <0>;
    70. 

  70. +				allwinner,pull = <0>;
    71. 

  71. +			};
    72. 

  72. +
    73. 

  73. +			nand_rb1_pins_a: nand_rb@1 {
    74. 

  74. +				allwinner,pins = "PC7";
    75. 

  75. +				allwinner,function = "nand0";
    76. 

  76. +				allwinner,drive = <0>;
    77. 

  77. +				allwinner,pull = <0>;
    78. 

  78. +			};
    79. 

  79.  		};
    80. 

  80.  
    81. 

  81.  		timer@01c20c00 {
    82.