164-3-dt-sun7i-add-mod1-clocknodes.patch 2.1 KB

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  1. From e9051f5dbc26e78f91cf23ca79ae4c8471119667 Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
  3. Date: Fri, 18 Jul 2014 15:26:08 -0300
  4. Subject: [PATCH] ARM: sun7i: Add mod1 clock nodes
  5. MIME-Version: 1.0
  6. Content-Type: text/plain; charset=UTF-8
  7. Content-Transfer-Encoding: 8bit
  8. This commit adds all the mod1 clocks available on A20 to its device
  9. tree. This list was created by looking at the A20 user manual.
  10. Not-signed-off-by: Emilio López <emilio@elopez.com.ar>
  11. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  12. ---
  13. arch/arm/boot/dts/sun7i-a20.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
  14. 1 file changed, 39 insertions(+)
  15. --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  16. +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  17. @@ -447,6 +447,29 @@
  18. clock-output-names = "ir1";
  19. };
  20. + iis0_clk: clk@01c200b8 {
  21. + #clock-cells = <0>;
  22. + compatible = "allwinner,sun4i-a10-mod1-clk";
  23. + reg = <0x01c200b8 0x4>;
  24. + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  25. + clock-output-names = "iis0";
  26. + };
  27. +
  28. + ac97_clk: clk@01c200bc {
  29. + #clock-cells = <0>;
  30. + compatible = "allwinner,sun4i-a10-mod1-clk";
  31. + reg = <0x01c200bc 0x4>;
  32. + clocks = <&pll2 3>, <&pll2 2>, <&pll2 1>, <&pll2 0>;
  33. + clock-output-names = "ac97";
  34. + };
  35. +
  36. + spdif_clk: clk@01c200c0 {
  37. + #clock-cells = <0>;
  38. + compatible = "allwinner,sun4i-a10-mod1-clk";
  39. + reg = <0x01c200c0 0x4>;
  40. + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  41. + clock-output-names = "spdif";
  42. + };
  43. usb_clk: clk@01c200cc {
  44. #clock-cells = <1>;
  45. #reset-cells = <1>;
  46. @@ -464,6 +487,22 @@
  47. clock-output-names = "spi3";
  48. };
  49. + iis1_clk: clk@01c200d8 {
  50. + #clock-cells = <0>;
  51. + compatible = "allwinner,sun4i-a10-mod1-clk";
  52. + reg = <0x01c200d8 0x4>;
  53. + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  54. + clock-output-names = "iis1";
  55. + };
  56. +
  57. + iis2_clk: clk@01c200dc {
  58. + #clock-cells = <0>;
  59. + compatible = "allwinner,sun4i-a10-mod1-clk";
  60. + reg = <0x01c200dc 0x4>;
  61. + clocks = <&pll2 0>, <&pll2 1>, <&pll2 2>, <&pll2 3>;
  62. + clock-output-names = "iis2";
  63. + };
  64. +
  65. codec_clk: clk@01c20140 {
  66. #clock-cells = <0>;
  67. compatible = "allwinner,sun4i-a10-codec-clk";