0031-MIPS-add-board-support-for-ZTE-ZXHN-H367N.patch 11 KB

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  1. From 0597056e2ba19ea783ef5c3d14c75c4722740e48 Mon Sep 17 00:00:00 2001
  2. From: Luka Perkov <luka@openwrt.org>
  3. Date: Sun, 10 Mar 2013 17:59:56 +0100
  4. Subject: MIPS: add board support for ZTE ZXHN H367N
  5. Signed-off-by: Luka Perkov <luka@openwrt.org>
  6. --- /dev/null
  7. +++ b/board/zte/zxhnh367n/Makefile
  8. @@ -0,0 +1,27 @@
  9. +#
  10. +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  11. +#
  12. +# SPDX-License-Identifier: GPL-2.0+
  13. +#
  14. +
  15. +include $(TOPDIR)/config.mk
  16. +
  17. +LIB = $(obj)lib$(BOARD).o
  18. +
  19. +COBJS = $(BOARD).o
  20. +
  21. +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  22. +OBJS := $(addprefix $(obj),$(COBJS))
  23. +SOBJS := $(addprefix $(obj),$(SOBJS))
  24. +
  25. +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
  26. + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  27. +
  28. +#########################################################################
  29. +
  30. +# defines $(obj).depend target
  31. +include $(SRCTREE)/rules.mk
  32. +
  33. +sinclude $(obj).depend
  34. +
  35. +#########################################################################
  36. --- /dev/null
  37. +++ b/board/zte/zxhnh367n/config.mk
  38. @@ -0,0 +1,7 @@
  39. +#
  40. +# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
  41. +#
  42. +# SPDX-License-Identifier: GPL-2.0+
  43. +#
  44. +
  45. +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
  46. --- /dev/null
  47. +++ b/board/zte/zxhnh367n/ddr_settings.h
  48. @@ -0,0 +1,70 @@
  49. +/*
  50. + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
  51. + *
  52. + * The values have been extracted from original ZTE U-Boot.
  53. + *
  54. + * SPDX-License-Identifier: GPL-2.0+
  55. + */
  56. +
  57. +#define MC_CCR00_VALUE 0x101
  58. +#define MC_CCR01_VALUE 0x1000101
  59. +#define MC_CCR02_VALUE 0x1010000
  60. +#define MC_CCR03_VALUE 0x100
  61. +#define MC_CCR04_VALUE 0x1000000
  62. +#define MC_CCR05_VALUE 0x1000101
  63. +#define MC_CCR06_VALUE 0x1000100
  64. +#define MC_CCR07_VALUE 0x1010000
  65. +#define MC_CCR08_VALUE 0x1000101
  66. +#define MC_CCR09_VALUE 0x0
  67. +#define MC_CCR10_VALUE 0x2000100
  68. +#define MC_CCR11_VALUE 0x2000401
  69. +#define MC_CCR12_VALUE 0x30000
  70. +#define MC_CCR13_VALUE 0x202
  71. +#define MC_CCR14_VALUE 0x7080A0F
  72. +#define MC_CCR15_VALUE 0x2040F
  73. +#define MC_CCR16_VALUE 0x40000
  74. +#define MC_CCR17_VALUE 0x70102
  75. +#define MC_CCR18_VALUE 0x4020002
  76. +#define MC_CCR19_VALUE 0x30302
  77. +#define MC_CCR20_VALUE 0x8000700
  78. +#define MC_CCR21_VALUE 0x40F020A
  79. +#define MC_CCR22_VALUE 0x0
  80. +#define MC_CCR23_VALUE 0xC020000
  81. +#define MC_CCR24_VALUE 0x4401B04
  82. +#define MC_CCR25_VALUE 0x0
  83. +#define MC_CCR26_VALUE 0x0
  84. +#define MC_CCR27_VALUE 0x6420000
  85. +#define MC_CCR28_VALUE 0x0
  86. +#define MC_CCR29_VALUE 0x0
  87. +#define MC_CCR30_VALUE 0x798
  88. +#define MC_CCR31_VALUE 0x0
  89. +#define MC_CCR32_VALUE 0x0
  90. +#define MC_CCR33_VALUE 0x650000
  91. +#define MC_CCR34_VALUE 0x200C8
  92. +#define MC_CCR35_VALUE 0x1D445D
  93. +#define MC_CCR36_VALUE 0xC8
  94. +#define MC_CCR37_VALUE 0xC351
  95. +#define MC_CCR38_VALUE 0x0
  96. +#define MC_CCR39_VALUE 0x141F04
  97. +#define MC_CCR40_VALUE 0x142704
  98. +#define MC_CCR41_VALUE 0x141B42
  99. +#define MC_CCR42_VALUE 0x141B42
  100. +#define MC_CCR43_VALUE 0x566504
  101. +#define MC_CCR44_VALUE 0x566504
  102. +#define MC_CCR45_VALUE 0x565F17
  103. +#define MC_CCR46_VALUE 0x565F17
  104. +#define MC_CCR47_VALUE 0x0
  105. +#define MC_CCR48_VALUE 0x0
  106. +#define MC_CCR49_VALUE 0x0
  107. +#define MC_CCR50_VALUE 0x0
  108. +#define MC_CCR51_VALUE 0x0
  109. +#define MC_CCR52_VALUE 0x133
  110. +#define MC_CCR53_VALUE 0xF3014B27
  111. +#define MC_CCR54_VALUE 0xF3014B27
  112. +#define MC_CCR55_VALUE 0xF3014B27
  113. +#define MC_CCR56_VALUE 0xF3014B27
  114. +#define MC_CCR57_VALUE 0x7800301
  115. +#define MC_CCR58_VALUE 0x7800301
  116. +#define MC_CCR59_VALUE 0x7800301
  117. +#define MC_CCR60_VALUE 0x7800301
  118. +#define MC_CCR61_VALUE 0x4
  119. --- /dev/null
  120. +++ b/board/zte/zxhnh367n/zxhnh367n.c
  121. @@ -0,0 +1,97 @@
  122. +/*
  123. + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
  124. + *
  125. + * SPDX-License-Identifier: GPL-2.0+
  126. + */
  127. +
  128. +#include <common.h>
  129. +#include <asm/gpio.h>
  130. +#include <asm/lantiq/eth.h>
  131. +#include <asm/lantiq/chipid.h>
  132. +#include <asm/lantiq/cpu.h>
  133. +#include <asm/arch/gphy.h>
  134. +
  135. +#if defined(CONFIG_SPL_BUILD)
  136. +#define do_gpio_init 1
  137. +#define do_pll_init 1
  138. +#define do_dcdc_init 0
  139. +#elif defined(CONFIG_SYS_BOOT_RAM)
  140. +#define do_gpio_init 1
  141. +#define do_pll_init 0
  142. +#define do_dcdc_init 1
  143. +#else
  144. +#define do_gpio_init 0
  145. +#define do_pll_init 0
  146. +#define do_dcdc_init 1
  147. +#endif
  148. +
  149. +static void gpio_init(void)
  150. +{
  151. + /* EBU.FL_CS1 as output for NAND CE */
  152. + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
  153. + /* EBU.FL_A23 as output for NAND CLE */
  154. + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
  155. + /* EBU.FL_A24 as output for NAND ALE */
  156. + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
  157. + /* GPIO 3.0 as input for NAND Ready Busy */
  158. + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
  159. + /* GPIO 3.1 as output for NAND Read */
  160. + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
  161. +}
  162. +
  163. +int board_early_init_f(void)
  164. +{
  165. + if (do_gpio_init)
  166. + gpio_init();
  167. +
  168. + if (do_pll_init)
  169. + ltq_pll_init();
  170. +
  171. + if (do_dcdc_init)
  172. + ltq_dcdc_init(0x7F);
  173. +
  174. + return 0;
  175. +}
  176. +
  177. +int checkboard(void)
  178. +{
  179. + puts("Board: " CONFIG_BOARD_NAME "\n");
  180. + ltq_chip_print_info();
  181. +
  182. + return 0;
  183. +}
  184. +
  185. +static const struct ltq_eth_port_config eth_port_config[] = {
  186. + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
  187. + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
  188. + /* GMAC1: unused */
  189. + { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
  190. + /* GMAC2: internal GPHY0 with 10/100 firmware for LAN port 1 */
  191. + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
  192. + /* GMAC3: internal GPHY0 with 10/100 firmware for LAN port 2 */
  193. + { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
  194. + /* GMAC4: internal GPHY1 with 10/100 firmware for LAN port 3 */
  195. + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
  196. + /* GMAC5: internal GPHY1 with 10/100 firmware for LAN port 4 */
  197. + { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
  198. +};
  199. +
  200. +static const struct ltq_eth_board_config eth_board_config = {
  201. + .ports = eth_port_config,
  202. + .num_ports = ARRAY_SIZE(eth_port_config),
  203. +};
  204. +
  205. +int board_eth_init(bd_t * bis)
  206. +{
  207. + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
  208. + const ulong fw_addr = 0x80FF0000;
  209. +
  210. + ltq_gphy_phy22f_a2x_load(fw_addr);
  211. +
  212. + ltq_cgu_gphy_clk_src(clk);
  213. +
  214. + ltq_rcu_gphy_boot(0, fw_addr);
  215. + ltq_rcu_gphy_boot(1, fw_addr);
  216. +
  217. + return ltq_eth_initialize(&eth_board_config);
  218. +}
  219. --- a/boards.cfg
  220. +++ b/boards.cfg
  221. @@ -527,6 +527,9 @@ Active mips mips32 vrx20
  222. Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  223. Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  224. Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  225. +Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_nandspl zxhnh367n:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org>
  226. +Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_ram zxhnh367n:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
  227. +Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_zte zxhnh367n:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org>
  228. Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
  229. Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
  230. Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
  231. --- /dev/null
  232. +++ b/include/configs/zxhnh367n.h
  233. @@ -0,0 +1,72 @@
  234. +/*
  235. + * Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
  236. + *
  237. + * SPDX-License-Identifier: GPL-2.0+
  238. + */
  239. +
  240. +#ifndef __CONFIG_H
  241. +#define __CONFIG_H
  242. +
  243. +#define CONFIG_MACH_TYPE "ZXHN H367N"
  244. +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
  245. +#define CONFIG_BOARD_NAME "ZTE ZXHN H367N"
  246. +
  247. +/* Configure SoC */
  248. +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
  249. +
  250. +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
  251. +
  252. +#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a NAND flash */
  253. +
  254. +#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
  255. +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
  256. +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
  257. +
  258. +#define CONFIG_SYS_NAND_PAGE_COUNT 128
  259. +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
  260. +#define CONFIG_SYS_NAND_OOBSIZE 64
  261. +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
  262. +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  263. +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
  264. +
  265. +#define CONFIG_SYS_DRAM_PROBE
  266. +
  267. +/* Environment */
  268. +#if defined(CONFIG_SYS_BOOT_NANDSPL)
  269. +#define CONFIG_ENV_IS_IN_NAND
  270. +#define CONFIG_ENV_OVERWRITE
  271. +#define CONFIG_ENV_OFFSET (256 * 1024)
  272. +#define CONFIG_ENV_SECT_SIZE (256 * 1024)
  273. +#else
  274. +#define CONFIG_ENV_IS_NOWHERE
  275. +#endif
  276. +
  277. +#define CONFIG_ENV_SIZE (8 * 1024)
  278. +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
  279. +
  280. +#if defined(CONFIG_SYS_BOOT_ZTE)
  281. +#define CONFIG_SYS_TEXT_BASE 0x80800000
  282. +#define CONFIG_SKIP_LOWLEVEL_INIT
  283. +#endif
  284. +
  285. +/* Console */
  286. +#define CONFIG_LTQ_ADVANCED_CONSOLE
  287. +#define CONFIG_BAUDRATE 115200
  288. +#define CONFIG_CONSOLE_ASC 1
  289. +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
  290. +
  291. +/* Pull in default board configs for Lantiq XWAY VRX200 */
  292. +#include <asm/lantiq/config.h>
  293. +#include <asm/arch/config.h>
  294. +
  295. +/* Pull in default OpenWrt configs for Lantiq SoC */
  296. +#include "openwrt-lantiq-common.h"
  297. +
  298. +#define CONFIG_ENV_UPDATE_UBOOT_NAND \
  299. + "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
  300. +
  301. +#define CONFIG_EXTRA_ENV_SETTINGS \
  302. + CONFIG_ENV_LANTIQ_DEFAULTS \
  303. + CONFIG_ENV_UPDATE_UBOOT_NAND
  304. +
  305. +#endif /* __CONFIG_H */