sysctl.h 4.4 KB

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  1. #ifndef _NAS782X_SYSCTL_H
  2. #define _NAS782X_SYSCTL_H
  3. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  4. #include <asm/types.h>
  5. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  6. #include <asm/arch/hardware.h>
  7. /**
  8. * System block reset and clock control
  9. */
  10. #define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE + 0x20)
  11. #define SYS_CTRL_CLK_SET_CTRL (SYS_CONTROL_BASE + 0x2C)
  12. #define SYS_CTRL_CLK_CLR_CTRL (SYS_CONTROL_BASE + 0x30)
  13. #define SYS_CTRL_RST_SET_CTRL (SYS_CONTROL_BASE + 0x34)
  14. #define SYS_CTRL_RST_CLR_CTRL (SYS_CONTROL_BASE + 0x38)
  15. #define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE + 0x48)
  16. #define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE + 0x6C)
  17. #define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE + 0x78)
  18. /* Scratch registers */
  19. #define SYS_CTRL_SCRATCHWORD0 (SYS_CONTROL_BASE + 0xc4)
  20. #define SYS_CTRL_SCRATCHWORD1 (SYS_CONTROL_BASE + 0xc8)
  21. #define SYS_CTRL_SCRATCHWORD2 (SYS_CONTROL_BASE + 0xcc)
  22. #define SYS_CTRL_SCRATCHWORD3 (SYS_CONTROL_BASE + 0xd0)
  23. #define SYS_CTRL_PLLA_CTRL0 (SYS_CONTROL_BASE + 0x1F0)
  24. #define SYS_CTRL_PLLA_CTRL1 (SYS_CONTROL_BASE + 0x1F4)
  25. #define SYS_CTRL_PLLA_CTRL2 (SYS_CONTROL_BASE + 0x1F8)
  26. #define SYS_CTRL_PLLA_CTRL3 (SYS_CONTROL_BASE + 0x1FC)
  27. #define SYS_CTRL_GMAC_AUTOSPEED 3
  28. #define SYS_CTRL_GMAC_RGMII 2
  29. #define SYS_CTRL_GMAC_SIMPLE_MUX 1
  30. #define SYS_CTRL_GMAC_CKEN_GTX 0
  31. #define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE + 0x64)
  32. #define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
  33. #define SYS_CTRL_CKCTRL_SLOW_BIT 8
  34. #define SYS_CTRL_USBHSMPH_CTRL (SYS_CONTROL_BASE + 0x40)
  35. #define SYS_CTRL_USBHSMPH_STAT (SYS_CONTROL_BASE + 0x44)
  36. #define SYS_CTRL_REF300_DIV (SYS_CONTROL_BASE + 0xF8)
  37. #define SYS_CTRL_USBHSPHY_CTRL (SYS_CONTROL_BASE + 0x84)
  38. #define SYS_CTRL_USB_CTRL (SYS_CONTROL_BASE + 0x90)
  39. /* System control multi-function pin function selection */
  40. #define SYS_CTRL_SECONDARY_SEL (SYS_CONTROL_BASE + 0x14)
  41. #define SYS_CTRL_TERTIARY_SEL (SYS_CONTROL_BASE + 0x8c)
  42. #define SYS_CTRL_QUATERNARY_SEL (SYS_CONTROL_BASE + 0x94)
  43. #define SYS_CTRL_DEBUG_SEL (SYS_CONTROL_BASE + 0x9c)
  44. #define SYS_CTRL_ALTERNATIVE_SEL (SYS_CONTROL_BASE + 0xa4)
  45. #define SYS_CTRL_PULLUP_SEL (SYS_CONTROL_BASE + 0xac)
  46. /* Secure control multi-function pin function selection */
  47. #define SEC_CTRL_SECONDARY_SEL (SEC_CONTROL_BASE + 0x14)
  48. #define SEC_CTRL_TERTIARY_SEL (SEC_CONTROL_BASE + 0x8c)
  49. #define SEC_CTRL_QUATERNARY_SEL (SEC_CONTROL_BASE + 0x94)
  50. #define SEC_CTRL_DEBUG_SEL (SEC_CONTROL_BASE + 0x9c)
  51. #define SEC_CTRL_ALTERNATIVE_SEL (SEC_CONTROL_BASE + 0xa4)
  52. #define SEC_CTRL_PULLUP_SEL (SEC_CONTROL_BASE + 0xac)
  53. #define SEC_CTRL_COPRO_CTRL (SEC_CONTROL_BASE + 0x68)
  54. #define SEC_CTRL_SECURE_CTRL (SEC_CONTROL_BASE + 0x98)
  55. #define SEC_CTRL_LEON_DEBUG (SEC_CONTROL_BASE + 0xF0)
  56. #define SEC_CTRL_PLLB_DIV_CTRL (SEC_CONTROL_BASE + 0xF8)
  57. #define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0)
  58. #define SEC_CTRL_PLLB_CTRL1 (SEC_CONTROL_BASE + 0x1F4)
  59. #define SEC_CTRL_PLLB_CTRL8 (SEC_CONTROL_BASE + 0x1F4)
  60. #define REF300_DIV_INT_SHIFT 8
  61. #define REF300_DIV_FRAC_SHIFT 0
  62. #define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
  63. #define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
  64. #define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
  65. #define USBHSPHY_SUSPENDM_MANUAL_STATE 15
  66. #define USBHSPHY_ATE_ESET 14
  67. #define USBHSPHY_TEST_DIN 6
  68. #define USBHSPHY_TEST_ADD 2
  69. #define USBHSPHY_TEST_DOUT_SEL 1
  70. #define USBHSPHY_TEST_CLK 0
  71. #define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
  72. #define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
  73. #define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
  74. #define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
  75. #define USBAMUX_DEVICE BIT(4)
  76. #define USBPHY_REFCLKDIV_SHIFT 2
  77. #define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
  78. #define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
  79. #define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
  80. #define USB_CTRL_USB_CKO_SEL_BIT 0
  81. #define USB_INT_CLK_XTAL 0
  82. #define USB_INT_CLK_REF300 2
  83. #define USB_INT_CLK_PLLB 3
  84. #define SYS_CTRL_GMAC_AUTOSPEED 3
  85. #define SYS_CTRL_GMAC_RGMII 2
  86. #define SYS_CTRL_GMAC_SIMPLE_MUX 1
  87. #define SYS_CTRL_GMAC_CKEN_GTX 0
  88. #define PLLB_ENSAT 3
  89. #define PLLB_OUTDIV 4
  90. #define PLLB_REFDIV 8
  91. #define PLLB_DIV_INT_SHIFT 8
  92. #define PLLB_DIV_FRAC_SHIFT 0
  93. #define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
  94. #define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
  95. #ifndef __KERNEL_STRICT_NAMES
  96. #ifndef __ASSEMBLY__
  97. #endif /* __ASSEMBLY__ */
  98. #endif /* __KERNEL_STRICT_NAMES */
  99. #endif /* _NAS782X_SYSCTL_H */