130-dt-bindings-add-SMP-enable-method-for-Broadcom-NSP.patch 2.4 KB

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  1. From 204b9dbd7c4bd5a223fd104b9cba56c12fe04add Mon Sep 17 00:00:00 2001
  2. From: Kapil Hali <kapilh@broadcom.com>
  3. Date: Wed, 19 Aug 2015 13:42:23 -0400
  4. Subject: [PATCH 130/134] dt-bindings: add SMP enable-method for Broadcom NSP
  5. Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
  6. Northstar Plus CPU to the 32-bit ARM CPU device tree binding
  7. documentation file and create a new binding documentation for
  8. Northstar Plus CPU.
  9. Signed-off-by: Kapil Hali <kapilh@broadcom.com>
  10. ---
  11. .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
  12. Documentation/devicetree/bindings/arm/cpus.txt | 1 +
  13. 2 files changed, 40 insertions(+)
  14. create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
  15. --- /dev/null
  16. +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
  17. @@ -0,0 +1,39 @@
  18. +Broadcom Northstar Plus SoC CPU Enable Method
  19. +---------------------------------------------
  20. +This binding defines the enable method used for starting secondary
  21. +CPUs in the following Broadcom SoCs:
  22. + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
  23. +
  24. +The enable method is specified by defining the following required
  25. +properties in the "cpus" device tree node:
  26. + - enable-method = "brcm,bcm-nsp-smp";
  27. + - secondary-boot-reg = <...>;
  28. +
  29. +The secondary-boot-reg property is a u32 value that specifies the
  30. +physical address of the register which should hold the common
  31. +entry point for a secondary CPU. This entry is cpu node specific
  32. +and should be added per cpu. E.g., in case of NSP (BCM58625) which
  33. +is a dual core CPU SoC, this entry should be added to cpu1 node.
  34. +
  35. +
  36. +Example:
  37. + cpus {
  38. + #address-cells = <1>;
  39. + #size-cells = <0>;
  40. + enable-method = "brcm,bcm-nsp-smp";
  41. +
  42. + cpu0: cpu@0 {
  43. + device_type = "cpu";
  44. + compatible = "arm,cortex-a9";
  45. + next-level-cache = <&L2>;
  46. + reg = <0>;
  47. + };
  48. +
  49. + cpu1: cpu@1 {
  50. + device_type = "cpu";
  51. + compatible = "arm,cortex-a9";
  52. + next-level-cache = <&L2>;
  53. + reg = <1>;
  54. + secondary-boot-reg = <0xffff042c>;
  55. + };
  56. + };
  57. --- a/Documentation/devicetree/bindings/arm/cpus.txt
  58. +++ b/Documentation/devicetree/bindings/arm/cpus.txt
  59. @@ -190,6 +190,7 @@ nodes to be present and contain the prop
  60. "allwinner,sun6i-a31"
  61. "allwinner,sun8i-a23"
  62. "arm,psci"
  63. + "brcm,bcm-nsp-smp"
  64. "brcm,brahma-b15"
  65. "marvell,armada-375-smp"
  66. "marvell,armada-380-smp"