pata_gemini.c 6.3 KB

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  1. /*
  2. * Support for Gemini PATA
  3. *
  4. * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
  5. * Copyright (C) 2010 Frederic Pecourt <opengemini@free.fr>
  6. * Copyright (C) 2011 Tobias Waldvogel <tobias.waldvogel@gmail.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, write to the Free Software Foundation, Inc.,
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  21. */
  22. /* Values of IOMUX
  23. * 26:24 bits is "IDE IO Select"
  24. * 111:100 - Reserved
  25. * 011 - ata0 <-> sata0, sata1; bring out ata1
  26. * 010 - ata1 <-> sata1, sata0; bring out ata0
  27. * 001 - ata0 <-> sata0, ata1 <-> sata1; bring out ata1
  28. * 000 - ata0 <-> sata0, ata1 <-> sata1; bring out ata0
  29. *
  30. */
  31. #include <linux/platform_device.h>
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/libata.h>
  35. #include <linux/leds.h>
  36. #include <mach/hardware.h>
  37. #include <mach/global_reg.h>
  38. #define DRV_NAME "pata-gemini"
  39. #define PATA_GEMINI_PORTS 1
  40. #define PIO_TIMING_REG 0x10
  41. #define MDMA_TIMING_REG 0x11
  42. #define UDMA_TIMING0_REG 0x12
  43. #define UDMA_TIMING1_REG 0x13
  44. #define CLK_MOD_REG 0x14
  45. #define CLK_MOD_66M_DEV0_BIT 0
  46. #define CLK_MOD_66M_DEV1_BIT 1
  47. #define CLK_MOD_UDMA_DEV0_BIT 4
  48. #define CLK_MOD_UDMA_DEV1_BIT 5
  49. #define CLK_MOD_66M_DEV0 (1 << CLK_MOD_66M_DEV0_BIT)
  50. #define CLK_MOD_66M_DEV1 (1 << CLK_MOD_66M_DEV1_BIT)
  51. #define CLK_MOD_UDMA_DEV0 (1 << CLK_MOD_UDMA_DEV0_BIT)
  52. #define CLK_MOD_UDMA_DEV1 (1 << CLK_MOD_UDMA_DEV1_BIT)
  53. #define SATA_ENABLE_PDEV_MASK 0x01
  54. #define SATA_ENABLE_PDEV_PM 0x02
  55. #define SATA_ENABLE_PDEV_ADDED 0x04
  56. #define SATA_ENABLE_PDEV_REMOVED 0x08
  57. #define SATA_ENABLE_SDEV_MASK 0x10
  58. #define SATA_ENABLE_SDEV_PM 0x20
  59. #define SATA_ENABLE_SDEV_ADDED 0x40
  60. #define SATA_ENABLE_SDEV_REMOVED 0x80
  61. MODULE_AUTHOR("Janos Laube <janos.dev@gmail.com>");
  62. MODULE_LICENSE("GPL");
  63. MODULE_ALIAS("platform:" DRV_NAME);
  64. static unsigned char PIO_TIMING[5] = {
  65. 0xaa, 0xa3, 0xa1, 0x33, 0x31
  66. };
  67. static unsigned char TIMING_MW_DMA[4][2] = {
  68. { 0x44, 1 }, // 480 4.2
  69. { 0x42, 1 }, // 150 13.3
  70. { 0x31, 1 }, // 120 16.7
  71. { 0x21, 1 }, // 100 20
  72. };
  73. static unsigned char TIMING_UDMA[7][2] = {
  74. { 0x33, 0 }, //240 16.7
  75. { 0x31, 0 }, //160 25
  76. { 0x21, 0 }, //120 33.3
  77. { 0x21, 1 }, //90 44.4
  78. { 0x11, 1 }, //60 66.7
  79. { 0x11 | 0x80, 0 }, //40 100
  80. { 0x11 | 0x80, 1 }, //30 133
  81. };
  82. static struct scsi_host_template pata_gemini_sht = {
  83. ATA_NCQ_SHT(DRV_NAME),
  84. .can_queue = 1,
  85. .sg_tablesize = 128,
  86. .dma_boundary = 0xffffU,
  87. };
  88. static void gemini_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  89. {
  90. void __iomem *clk_reg = ap->ioaddr.bmdma_addr + CLK_MOD_REG;
  91. void __iomem *tim_reg = ap->ioaddr.bmdma_addr + UDMA_TIMING0_REG;
  92. unsigned short udma = adev->dma_mode;
  93. unsigned short speed = udma;
  94. unsigned short devno = adev->devno & 1;
  95. unsigned short i;
  96. u8 mod_udma_mask = 1 << (CLK_MOD_UDMA_DEV0_BIT + devno);
  97. u8 mod_66m_mask = 1 << (CLK_MOD_66M_DEV0_BIT + devno);
  98. u8 clk_mod;
  99. u8 timing;
  100. clk_mod = ioread8(clk_reg);
  101. clk_mod &= ~mod_udma_mask;
  102. if (speed & XFER_UDMA_0) {
  103. i = speed & ~XFER_UDMA_0;
  104. timing = TIMING_UDMA[i][0];
  105. clk_mod |= mod_udma_mask;
  106. if (TIMING_UDMA[i][1])
  107. clk_mod |= mod_66m_mask;
  108. } else {
  109. i = speed & ~XFER_MW_DMA_0;
  110. timing = TIMING_MW_DMA[i][0];
  111. clk_mod |= mod_udma_mask;
  112. if (TIMING_MW_DMA[i][1])
  113. clk_mod |= mod_66m_mask;
  114. }
  115. iowrite8(clk_mod, clk_reg);
  116. iowrite8(timing, tim_reg + devno);
  117. return;
  118. }
  119. static void gemini_set_piomode(struct ata_port *ap, struct ata_device *adev)
  120. {
  121. void __iomem *pio_reg = ap->ioaddr.bmdma_addr + PIO_TIMING_REG;
  122. unsigned int pio = adev->pio_mode - XFER_PIO_0;
  123. iowrite8(PIO_TIMING[pio], pio_reg);
  124. }
  125. unsigned int gemini_qc_issue(struct ata_queued_cmd *qc)
  126. {
  127. ledtrig_ide_activity();
  128. return ata_bmdma_qc_issue(qc);
  129. }
  130. static struct ata_port_operations pata_gemini_port_ops = {
  131. .inherits = &ata_bmdma_port_ops,
  132. .set_dmamode = gemini_set_dmamode,
  133. .set_piomode = gemini_set_piomode,
  134. .qc_issue = gemini_qc_issue,
  135. };
  136. static struct ata_port_info pata_gemini_portinfo = {
  137. .flags = 0,
  138. .udma_mask = ATA_UDMA6,
  139. .pio_mask = ATA_PIO4,
  140. .port_ops = &pata_gemini_port_ops,
  141. };
  142. static const struct ata_port_info *pata_gemini_ports = &pata_gemini_portinfo;
  143. static int pata_gemini_probe(struct platform_device *pdev)
  144. {
  145. struct ata_host *host;
  146. struct resource *res;
  147. unsigned int irq, i;
  148. void __iomem *mmio_base;
  149. /* standard bdma init */
  150. irq = platform_get_irq(pdev, 0);
  151. if (irq < 0)
  152. return irq;
  153. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  154. if (!res)
  155. return -ENODEV;
  156. pr_info(DRV_NAME ": irq %d, io base 0x%08x\n", irq, res->start);
  157. mmio_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  158. host = ata_host_alloc_pinfo(&pdev->dev, &pata_gemini_ports, 1);
  159. if (!host)
  160. return -ENOMEM;
  161. for (i = 0; i < host->n_ports; i++) {
  162. struct ata_port *ap = host->ports[i];
  163. struct ata_ioports *ioaddr = &ap->ioaddr;
  164. ioaddr->bmdma_addr = mmio_base;
  165. ioaddr->cmd_addr = mmio_base + 0x20;
  166. ioaddr->ctl_addr = mmio_base + 0x36;
  167. ioaddr->altstatus_addr = ioaddr->ctl_addr;
  168. ata_sff_std_ports(ioaddr);
  169. host->ports[i]->cbl = ATA_CBL_SATA;
  170. }
  171. return ata_host_activate(host, irq, ata_bmdma_interrupt,
  172. IRQF_SHARED, &pata_gemini_sht);
  173. }
  174. static int pata_gemini_remove(struct platform_device *pdev)
  175. {
  176. struct device *dev = &pdev->dev;
  177. struct ata_host *host = dev_get_drvdata(dev);
  178. ata_host_detach(host);
  179. return 0;
  180. }
  181. static struct platform_driver pata_gemini_driver = {
  182. .probe = pata_gemini_probe,
  183. .remove = pata_gemini_remove,
  184. .driver.owner = THIS_MODULE,
  185. .driver.name = DRV_NAME,
  186. };
  187. static int __init pata_gemini_module_init(void)
  188. {
  189. return platform_driver_probe(&pata_gemini_driver, pata_gemini_probe);
  190. }
  191. static void __exit pata_gemini_module_exit(void)
  192. {
  193. platform_driver_unregister(&pata_gemini_driver);
  194. }
  195. module_init(pata_gemini_module_init);
  196. module_exit(pata_gemini_module_exit);