103-ARM-DT-ipq8064-Add-TCSR-support.patch 1.5 KB

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  1. --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  2. +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  3. @@ -132,6 +132,7 @@
  4. gsbi2: gsbi@12480000 {
  5. compatible = "qcom,gsbi-v1.0.0";
  6. + cell-index = <2>;
  7. reg = <0x12480000 0x100>;
  8. clocks = <&gcc GSBI2_H_CLK>;
  9. clock-names = "iface";
  10. @@ -140,6 +141,8 @@
  11. ranges;
  12. status = "disabled";
  13. + syscon-tcsr = <&tcsr>;
  14. +
  15. uart2: serial@12490000 {
  16. compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  17. reg = <0x12490000 0x1000>,
  18. @@ -167,6 +170,7 @@
  19. gsbi4: gsbi@16300000 {
  20. compatible = "qcom,gsbi-v1.0.0";
  21. + cell-index = <4>;
  22. reg = <0x16300000 0x100>;
  23. clocks = <&gcc GSBI4_H_CLK>;
  24. clock-names = "iface";
  25. @@ -175,6 +179,8 @@
  26. ranges;
  27. status = "disabled";
  28. + syscon-tcsr = <&tcsr>;
  29. +
  30. uart4: serial@16340000 {
  31. compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  32. reg = <0x16340000 0x1000>,
  33. @@ -201,6 +207,7 @@
  34. gsbi5: gsbi@1a200000 {
  35. compatible = "qcom,gsbi-v1.0.0";
  36. + cell-index = <5>;
  37. reg = <0x1a200000 0x100>;
  38. clocks = <&gcc GSBI5_H_CLK>;
  39. clock-names = "iface";
  40. @@ -209,6 +216,8 @@
  41. ranges;
  42. status = "disabled";
  43. + syscon-tcsr = <&tcsr>;
  44. +
  45. uart5: serial@1a240000 {
  46. compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  47. reg = <0x1a240000 0x1000>,
  48. @@ -279,6 +288,11 @@
  49. status = "disabled";
  50. };
  51. + tcsr: syscon@1a400000 {
  52. + compatible = "qcom,tcsr-ipq8064", "syscon";
  53. + reg = <0x1a400000 0x100>;
  54. + };
  55. +
  56. qcom,ssbi@500000 {
  57. compatible = "qcom,ssbi";
  58. reg = <0x00500000 0x1000>;