vr9.dtsi 4.7 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "lantiq,xway", "lantiq,vr9";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips34Kc";
  8. };
  9. };
  10. memory@0 {
  11. device_type = "memory";
  12. };
  13. biu@1F800000 {
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. compatible = "lantiq,biu", "simple-bus";
  17. reg = <0x1F800000 0x800000>;
  18. ranges = <0x0 0x1F800000 0x7FFFFF>;
  19. icu0: icu@80200 {
  20. #interrupt-cells = <1>;
  21. interrupt-controller;
  22. compatible = "lantiq,icu";
  23. reg = <0x80200 0x28
  24. 0x80228 0x28
  25. 0x80250 0x28
  26. 0x80278 0x28
  27. 0x802a0 0x28>;
  28. };
  29. watchdog@803F0 {
  30. compatible = "lantiq,wdt";
  31. reg = <0x803F0 0x10>;
  32. };
  33. };
  34. sram@1F000000 {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. compatible = "lantiq,sram", "simple-bus";
  38. reg = <0x1F000000 0x800000>;
  39. ranges = <0x0 0x1F000000 0x7FFFFF>;
  40. eiu0: eiu@101000 {
  41. #interrupt-cells = <1>;
  42. interrupt-controller;
  43. compatible = "lantiq,eiu-xway";
  44. reg = <0x101000 0x1000>;
  45. interrupt-parent = <&icu0>;
  46. lantiq,eiu-irqs = <166 135 66 40 41 42>;
  47. };
  48. pmu0: pmu@102000 {
  49. compatible = "lantiq,pmu-xway";
  50. reg = <0x102000 0x1000>;
  51. };
  52. cgu0: cgu@103000 {
  53. compatible = "lantiq,cgu-xway";
  54. reg = <0x103000 0x1000>;
  55. };
  56. dcdc@106a00 {
  57. compatible = "lantiq,dcdc-xrx200";
  58. reg = <0x106a00 0x200>;
  59. };
  60. rcu0: rcu@203000 {
  61. compatible = "lantiq,rcu-xrx200";
  62. reg = <0x203000 0x1000>;
  63. /* irq for thermal sensor */
  64. interrupt-parent = <&icu0>;
  65. interrupts = <115>;
  66. };
  67. xbar0: xbar@400000 {
  68. compatible = "lantiq,xbar-xway";
  69. reg = <0x400000 0x1000>;
  70. };
  71. };
  72. fpi@10000000 {
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. compatible = "lantiq,fpi", "simple-bus";
  76. ranges = <0x0 0x10000000 0xEEFFFFF>;
  77. reg = <0x10000000 0xEF00000>;
  78. localbus@0 {
  79. #address-cells = <2>;
  80. #size-cells = <1>;
  81. ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
  82. 1 0 0x4000000 0x4000010>; /* addsel1 */
  83. compatible = "lantiq,localbus", "simple-bus";
  84. };
  85. gptu@E100A00 {
  86. compatible = "lantiq,gptu-xway";
  87. reg = <0xE100A00 0x100>;
  88. interrupt-parent = <&icu0>;
  89. interrupts = <126 127 128 129 130 131>;
  90. };
  91. asc0: serial@E100400 {
  92. compatible = "lantiq,asc";
  93. reg = <0xE100400 0x400>;
  94. interrupt-parent = <&icu0>;
  95. interrupts = <104 105 106>;
  96. status = "disabled";
  97. };
  98. spi: spi@E100800 {
  99. compatible = "lantiq,xrx200-spi";
  100. reg = <0xE100800 0x100>;
  101. interrupt-parent = <&icu0>;
  102. interrupts = <22 23 24>;
  103. interrupt-names = "spi_rx", "spi_tx", "spi_err",
  104. "spi_frm";
  105. #address-cells = <1>;
  106. #size-cells = <1>;
  107. status = "disabled";
  108. };
  109. gpio: pinmux@E100B10 {
  110. compatible = "lantiq,xrx200-pinctrl";
  111. #gpio-cells = <2>;
  112. gpio-controller;
  113. reg = <0xE100B10 0xA0>;
  114. };
  115. asc1: serial@E100C00 {
  116. compatible = "lantiq,asc";
  117. reg = <0xE100C00 0x400>;
  118. interrupt-parent = <&icu0>;
  119. interrupts = <112 113 114>;
  120. };
  121. deu@E103100 {
  122. compatible = "lantiq,deu-xrx200";
  123. reg = <0xE103100 0xf00>;
  124. };
  125. dma0: dma@E104100 {
  126. compatible = "lantiq,dma-xway";
  127. reg = <0xE104100 0x800>;
  128. };
  129. ebu0: ebu@E105300 {
  130. compatible = "lantiq,ebu-xway";
  131. reg = <0xE105300 0x100>;
  132. };
  133. ifxhcd@E101000 {
  134. status = "disabled";
  135. compatible = "lantiq,ifxhcd-xrx200", "lantiq,ifxhcd-xrx200-dwc2";
  136. reg = <0xE101000 0x1000
  137. 0xE120000 0x3f000>;
  138. interrupt-parent = <&icu0>;
  139. interrupts = <62 91>;
  140. };
  141. ifxhcd@E106000 {
  142. status = "disabled";
  143. compatible = "lantiq,ifxhcd-xrx200-dwc2";
  144. reg = <0xE106000 0x1000>;
  145. interrupt-parent = <&icu0>;
  146. interrupts = <91>;
  147. };
  148. eth0: eth@E108000 {
  149. #address-cells = <1>;
  150. #size-cells = <0>;
  151. compatible = "lantiq,xrx200-net";
  152. reg = < 0xE108000 0x3000 /* switch */
  153. 0xE10B100 0x70 /* mdio */
  154. 0xE10B1D8 0x30 /* mii */
  155. 0xE10B308 0x30 /* pmac */
  156. >;
  157. interrupt-parent = <&icu0>;
  158. interrupts = <73 72>;
  159. };
  160. mei@E116000 {
  161. compatible = "lantiq,mei-xrx200";
  162. reg = <0xE116000 0x9c>;
  163. interrupt-parent = <&icu0>;
  164. interrupts = <63>;
  165. };
  166. ppe@E234000 {
  167. compatible = "lantiq,ppe-xrx200";
  168. interrupt-parent = <&icu0>;
  169. interrupts = <96>;
  170. };
  171. pcie@d900000 {
  172. interrupt-parent = <&icu0>;
  173. interrupts = <161 144>;
  174. compatible = "lantiq,pcie-xrx200";
  175. gpio-reset = <&gpio 38 0>;
  176. };
  177. pci0: pci@E105400 {
  178. #address-cells = <3>;
  179. #size-cells = <2>;
  180. #interrupt-cells = <1>;
  181. compatible = "lantiq,pci-xway";
  182. bus-range = <0x0 0x0>;
  183. ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
  184. 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
  185. reg = <0x7000000 0x8000 /* config space */
  186. 0xE105400 0x400>; /* pci bridge */
  187. status = "disabled";
  188. };
  189. };
  190. vdsl {
  191. compatible = "lantiq,vdsl-vrx200";
  192. };
  193. };