0005-soc-mediatek-Add-MT2701-MT7623-scpsys-driver.patch 6.0 KB

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  1. From 8aa49d107d8a22fd6cbf37174614baf32d0976e2 Mon Sep 17 00:00:00 2001
  2. From: Shunli Wang <shunli.wang@mediatek.com>
  3. Date: Wed, 30 Dec 2015 14:41:46 +0800
  4. Subject: [PATCH 005/102] soc: mediatek: Add MT2701/MT7623 scpsys driver
  5. Add scpsys driver for MT2701 and MT7623.
  6. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
  7. Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
  8. ---
  9. drivers/soc/mediatek/Kconfig | 11 ++
  10. drivers/soc/mediatek/Makefile | 1 +
  11. drivers/soc/mediatek/mtk-scpsys-mt2701.c | 161 ++++++++++++++++++++++++++++++
  12. 3 files changed, 173 insertions(+)
  13. create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt2701.c
  14. --- a/drivers/soc/mediatek/Kconfig
  15. +++ b/drivers/soc/mediatek/Kconfig
  16. @@ -39,3 +39,14 @@ config MTK_SCPSYS_MT8173
  17. driver.
  18. The System Control Processor System (SCPSYS) has several power
  19. management related tasks in the system.
  20. +
  21. +config MTK_SCPSYS_MT2701
  22. + bool "SCPSYS Support MediaTek MT2701 and MT7623"
  23. + depends on ARCH_MEDIATEK || COMPILE_TEST
  24. + select MTK_SCPSYS
  25. + default ARCH_MEDIATEK
  26. + help
  27. + Say yes here to add support for the MT2701/MT7623 SCPSYS power
  28. + domain driver.
  29. + The System Control Processor System (SCPSYS) has several power
  30. + management related tasks in the system.
  31. --- a/drivers/soc/mediatek/Makefile
  32. +++ b/drivers/soc/mediatek/Makefile
  33. @@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infrac
  34. obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
  35. obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
  36. obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
  37. +obj-$(CONFIG_MTK_SCPSYS_MT2701) += mtk-scpsys-mt2701.o
  38. --- /dev/null
  39. +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
  40. @@ -0,0 +1,161 @@
  41. +/*
  42. + * Copyright (c) 2015 Mediatek, Shunli Wang <shunli.wang@mediatek.com>
  43. + *
  44. + * This program is free software; you can redistribute it and/or modify
  45. + * it under the terms of the GNU General Public License version 2 as
  46. + * published by the Free Software Foundation.
  47. + *
  48. + * This program is distributed in the hope that it will be useful,
  49. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  50. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  51. + * GNU General Public License for more details.
  52. + */
  53. +#include <linux/mfd/syscon.h>
  54. +#include <linux/module.h>
  55. +#include <linux/of_device.h>
  56. +#include <linux/pm_domain.h>
  57. +#include <linux/soc/mediatek/infracfg.h>
  58. +#include <dt-bindings/power/mt2701-power.h>
  59. +
  60. +#include "mtk-scpsys.h"
  61. +
  62. +#define SPM_VDE_PWR_CON 0x0210
  63. +#define SPM_MFG_PWR_CON 0x0214
  64. +#define SPM_ISP_PWR_CON 0x0238
  65. +#define SPM_DIS_PWR_CON 0x023C
  66. +#define SPM_CONN_PWR_CON 0x0280
  67. +#define SPM_BDP_PWR_CON 0x029C
  68. +#define SPM_ETH_PWR_CON 0x02A0
  69. +#define SPM_HIF_PWR_CON 0x02A4
  70. +#define SPM_IFR_MSC_PWR_CON 0x02A8
  71. +#define SPM_PWR_STATUS 0x060c
  72. +#define SPM_PWR_STATUS_2ND 0x0610
  73. +
  74. +#define CONN_PWR_STA_MASK BIT(1)
  75. +#define DIS_PWR_STA_MASK BIT(3)
  76. +#define MFG_PWR_STA_MASK BIT(4)
  77. +#define ISP_PWR_STA_MASK BIT(5)
  78. +#define VDE_PWR_STA_MASK BIT(7)
  79. +#define BDP_PWR_STA_MASK BIT(14)
  80. +#define ETH_PWR_STA_MASK BIT(15)
  81. +#define HIF_PWR_STA_MASK BIT(16)
  82. +#define IFR_MSC_PWR_STA_MASK BIT(17)
  83. +
  84. +#define MT2701_TOP_AXI_PROT_EN_CONN 0x0104
  85. +#define MT2701_TOP_AXI_PROT_EN_DISP 0x0002
  86. +
  87. +static const struct scp_domain_data scp_domain_data[] = {
  88. + [MT2701_POWER_DOMAIN_CONN] = {
  89. + .name = "conn",
  90. + .sta_mask = CONN_PWR_STA_MASK,
  91. + .ctl_offs = SPM_CONN_PWR_CON,
  92. + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN,
  93. + .active_wakeup = true,
  94. + },
  95. + [MT2701_POWER_DOMAIN_DISP] = {
  96. + .name = "disp",
  97. + .sta_mask = DIS_PWR_STA_MASK,
  98. + .ctl_offs = SPM_DIS_PWR_CON,
  99. + .sram_pdn_bits = GENMASK(11, 8),
  100. + .clk_id = {CLK_MM},
  101. + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_DISP,
  102. + .active_wakeup = true,
  103. + },
  104. + [MT2701_POWER_DOMAIN_MFG] = {
  105. + .name = "mfg",
  106. + .sta_mask = MFG_PWR_STA_MASK,
  107. + .ctl_offs = SPM_MFG_PWR_CON,
  108. + .sram_pdn_bits = GENMASK(11, 8),
  109. + .sram_pdn_ack_bits = GENMASK(12, 12),
  110. + .active_wakeup = true,
  111. + },
  112. + [MT2701_POWER_DOMAIN_VDEC] = {
  113. + .name = "vdec",
  114. + .sta_mask = VDE_PWR_STA_MASK,
  115. + .ctl_offs = SPM_VDE_PWR_CON,
  116. + .sram_pdn_bits = GENMASK(11, 8),
  117. + .sram_pdn_ack_bits = GENMASK(12, 12),
  118. + .clk_id = {CLK_MM},
  119. + .active_wakeup = true,
  120. + },
  121. + [MT2701_POWER_DOMAIN_ISP] = {
  122. + .name = "isp",
  123. + .sta_mask = ISP_PWR_STA_MASK,
  124. + .ctl_offs = SPM_ISP_PWR_CON,
  125. + .sram_pdn_bits = GENMASK(11, 8),
  126. + .sram_pdn_ack_bits = GENMASK(13, 12),
  127. + .active_wakeup = true,
  128. + },
  129. + [MT2701_POWER_DOMAIN_BDP] = {
  130. + .name = "bdp",
  131. + .sta_mask = BDP_PWR_STA_MASK,
  132. + .ctl_offs = SPM_BDP_PWR_CON,
  133. + .sram_pdn_bits = GENMASK(11, 8),
  134. + .active_wakeup = true,
  135. + },
  136. + [MT2701_POWER_DOMAIN_ETH] = {
  137. + .name = "eth",
  138. + .sta_mask = ETH_PWR_STA_MASK,
  139. + .ctl_offs = SPM_ETH_PWR_CON,
  140. + .sram_pdn_bits = GENMASK(11, 8),
  141. + .sram_pdn_ack_bits = GENMASK(15, 12),
  142. + .active_wakeup = true,
  143. + },
  144. + [MT2701_POWER_DOMAIN_HIF] = {
  145. + .name = "hif",
  146. + .sta_mask = HIF_PWR_STA_MASK,
  147. + .ctl_offs = SPM_HIF_PWR_CON,
  148. + .sram_pdn_bits = GENMASK(11, 8),
  149. + .sram_pdn_ack_bits = GENMASK(15, 12),
  150. + .active_wakeup = true,
  151. + },
  152. + [MT2701_POWER_DOMAIN_IFR_MSC] = {
  153. + .name = "ifr_msc",
  154. + .sta_mask = IFR_MSC_PWR_STA_MASK,
  155. + .ctl_offs = SPM_IFR_MSC_PWR_CON,
  156. + .active_wakeup = true,
  157. + },
  158. +};
  159. +
  160. +#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
  161. +
  162. +static int __init scpsys_probe(struct platform_device *pdev)
  163. +{
  164. + struct scp *scp;
  165. +
  166. + scp = init_scp(pdev, scp_domain_data, NUM_DOMAINS);
  167. + if (IS_ERR(scp))
  168. + return PTR_ERR(scp);
  169. +
  170. + mtk_register_power_domains(pdev, scp, NUM_DOMAINS);
  171. +
  172. + return 0;
  173. +}
  174. +
  175. +static const struct of_device_id of_scpsys_match_tbl[] = {
  176. + {
  177. + .compatible = "mediatek,mt2701-scpsys",
  178. + }, {
  179. + /* sentinel */
  180. + }
  181. +};
  182. +MODULE_DEVICE_TABLE(of, of_scpsys_match_tbl);
  183. +
  184. +static struct platform_driver scpsys_drv = {
  185. + .driver = {
  186. + .name = "mtk-scpsys-mt2701",
  187. + .owner = THIS_MODULE,
  188. + .of_match_table = of_match_ptr(of_scpsys_match_tbl),
  189. + },
  190. + .probe = scpsys_probe,
  191. +};
  192. +
  193. +static int __init scpsys_init(void)
  194. +{
  195. + return platform_driver_register(&scpsys_drv);
  196. +}
  197. +
  198. +subsys_initcall(scpsys_init);
  199. +
  200. +MODULE_DESCRIPTION("MediaTek MT2701 scpsys driver");
  201. +MODULE_LICENSE("GPL v2");