0070-net-mediatek-update-the-IRQ-part-of-the-binding-docu.patch 1.8 KB

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  1. From 297ef52cd21e28da671996d7b4f39f268d2d0ec1 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Tue, 29 Mar 2016 14:32:07 +0200
  4. Subject: [PATCH 070/102] net: mediatek: update the IRQ part of the binding
  5. document
  6. The current binding document only describes a single interrupt. Update the
  7. document by adding the 2 other interrupts.
  8. The driver currently only uses a single interrupt. The HW is however able
  9. to using IRQ grouping to split TX and RX onto separate GIC irqs.
  10. Signed-off-by: John Crispin <blogic@openwrt.org>
  11. Acked-by: Rob Herring <robh@kernel.org>
  12. ---
  13. Documentation/devicetree/bindings/net/mediatek-net.txt | 7 +++++--
  14. 1 file changed, 5 insertions(+), 2 deletions(-)
  15. --- a/Documentation/devicetree/bindings/net/mediatek-net.txt
  16. +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
  17. @@ -9,7 +9,8 @@ have dual GMAC each represented by a chi
  18. Required properties:
  19. - compatible: Should be "mediatek,mt7623-eth"
  20. - reg: Address and length of the register set for the device
  21. -- interrupts: Should contain the frame engines interrupt
  22. +- interrupts: Should contain the three frame engines interrupts in numeric
  23. + order. These are fe_int0, fe_int1 and fe_int2.
  24. - clocks: the clock used by the core
  25. - clock-names: the names of the clock listed in the clocks property. These are
  26. "ethif", "esw", "gp2", "gp1"
  27. @@ -42,7 +43,9 @@ eth: ethernet@1b100000 {
  28. <&ethsys CLK_ETHSYS_GP2>,
  29. <&ethsys CLK_ETHSYS_GP1>;
  30. clock-names = "ethif", "esw", "gp2", "gp1";
  31. - interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
  32. + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
  33. + GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
  34. + GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
  35. power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
  36. resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
  37. reset-names = "eth";