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patches-4.4
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320-oxnas-irqchip.patch

320-oxnas-irqchip.patch 1.3 KB
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  1. --- a/drivers/irqchip/Kconfig
    2. 

  2. +++ b/drivers/irqchip/Kconfig
    3. 

  3. @@ -27,6 +27,11 @@ config ARM_GIC_V3_ITS
    4. 

  4.  	bool
    5. 

  5.  	select PCI_MSI_IRQ_DOMAIN
    6. 

  6.  
    7. 

  7. +config PLXTECH_RPS
    8. 

  8. +	def_bool y if ARHC_OXNAS
    9. 

  9. +	depends on ARCH_OXNAS
    10. 

  10. +	select IRQ_DOMAIN
    11. 

  11. +
    12. 

  12.  config ARM_NVIC
    13. 

  13.  	bool
    14. 

  14.  	select IRQ_DOMAIN
    15. 

  15. --- a/drivers/irqchip/Makefile
    16. 

  16. +++ b/drivers/irqchip/Makefile
    17. 

  17. @@ -34,6 +34,7 @@ obj-$(CONFIG_IRQ_MIPS_CPU)		+= irq-mips-
    18. 

  18.  obj-$(CONFIG_SIRF_IRQ)			+= irq-sirfsoc.o
    19. 

  19.  obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o
    20. 

  20.  obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o
    21. 

  21. +obj-$(CONFIG_PLXTECH_RPS)		+= irq-rps.o
    22. 

  22.  obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o
    23. 

  23.  obj-$(CONFIG_ARCH_NSPIRE)		+= irq-zevio.o
    24. 

  24.  obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o
    25. 

  25. --- a/drivers/irqchip/irq-gic.c
    26. 

  26. +++ b/drivers/irqchip/irq-gic.c
    27. 

  27. @@ -1253,6 +1253,7 @@ IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,
    28. 

  28.  IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
    29. 

  29.  IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
    30. 

  30.  IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
    31. 

  31. +IRQCHIP_DECLARE(arm11_mpcore_gic, "arm,arm11mp-gic", gic_of_init);
    32. 

  32.  IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
    33. 

  33.  IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
    34. 

  34.  IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
    35.