ArcherC20i.dts 1.6 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. / {
  4. compatible = "ralink,mt7620a-soc";
  5. model = "TP-Link Archer C20i";
  6. chosen {
  7. bootargs = "console=ttyS0,115200";
  8. };
  9. gpio-leds {
  10. compatible = "gpio-leds";
  11. };
  12. gpio-keys-polled {
  13. compatible = "gpio-keys-polled";
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. poll-interval = <20>;
  17. };
  18. };
  19. &gpio2 {
  20. status = "okay";
  21. };
  22. &spi0 {
  23. status = "okay";
  24. m25p80@0 {
  25. #address-cells = <1>;
  26. #size-cells = <1>;
  27. compatible = "jedec,spi-nor";
  28. reg = <0>;
  29. linux,modalias = "m25p80", "mx25l6405d";
  30. spi-max-frequency = <10000000>;
  31. partition@0 {
  32. label = "u-boot";
  33. reg = <0x0 0x20000>;
  34. read-only;
  35. };
  36. partition@20000 {
  37. label = "firmware";
  38. reg = <0x20000 0x7a0000>;
  39. };
  40. partition@7c0000 {
  41. label = "config";
  42. reg = <0x7c0000 0x10000>;
  43. };
  44. rom: partition@7d0000 {
  45. label = "rom";
  46. reg = <0x7d0000 0x10000>;
  47. };
  48. partition@7e0000 {
  49. label = "romfile";
  50. reg = <0x7e0000 0x10000>;
  51. };
  52. radio: partition@7f0000 {
  53. label = "radio";
  54. reg = <0x7f0000 0x10000>;
  55. };
  56. };
  57. };
  58. &pinctrl {
  59. state_default: pinctrl0 {
  60. gpio {
  61. ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd";
  62. ralink,function = "gpio";
  63. };
  64. };
  65. };
  66. &ethernet {
  67. pinctrl-names = "default";
  68. pinctrl-0 = <&ephy_pins>;
  69. mtd-mac-address = <&rom 0xf100>;
  70. mediatek,portmap = "wllll";
  71. };
  72. &ehci {
  73. status = "okay";
  74. };
  75. &ohci {
  76. status = "okay";
  77. };
  78. &gsw {
  79. mediatek,port4 = "ephy";
  80. };
  81. &wmac {
  82. ralink,mtd-eeprom = <&radio 0>;
  83. };
  84. &pcie {
  85. status = "okay";
  86. pcie-bridge {
  87. mt76@0,0 {
  88. reg = <0x0000 0 0 0 0>;
  89. device_type = "pci";
  90. mediatek,mtd-eeprom = <&radio 32768>;
  91. mediatek,2ghz = <0>;
  92. };
  93. };
  94. };