0028-GPIO-ralink-add-mt7621-gpio-controller.patch 10 KB

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  1. From 61ac7d9b4228de8c332900902c2b93189b042eab Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 11:00:32 +0100
  4. Subject: [PATCH 28/53] GPIO: ralink: add mt7621 gpio controller
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. arch/mips/Kconfig | 3 +
  8. drivers/gpio/Kconfig | 6 +
  9. drivers/gpio/Makefile | 1 +
  10. drivers/gpio/gpio-mt7621.c | 354 ++++++++++++++++++++++++++++++++++++++++++++
  11. 4 files changed, 364 insertions(+)
  12. create mode 100644 drivers/gpio/gpio-mt7621.c
  13. --- a/arch/mips/Kconfig
  14. +++ b/arch/mips/Kconfig
  15. @@ -587,6 +587,9 @@ config RALINK
  16. select RESET_CONTROLLER
  17. select PINCTRL
  18. select PINCTRL_RT2880
  19. + select ARCH_HAS_RESET_CONTROLLER
  20. + select RESET_CONTROLLER
  21. + select ARCH_REQUIRE_GPIOLIB
  22. config SGI_IP22
  23. bool "SGI IP22 (Indy/Indigo2)"
  24. --- a/drivers/gpio/Kconfig
  25. +++ b/drivers/gpio/Kconfig
  26. @@ -260,6 +260,12 @@ config GPIO_MB86S7X
  27. help
  28. Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs.
  29. +config GPIO_MT7621
  30. + bool "Mediatek GPIO Support"
  31. + depends on SOC_MT7620 || SOC_MT7621
  32. + help
  33. + Say yes here to support the Mediatek SoC GPIO device
  34. +
  35. config GPIO_MM_LANTIQ
  36. bool "Lantiq Memory mapped GPIOs"
  37. depends on LANTIQ && SOC_XWAY
  38. --- a/drivers/gpio/Makefile
  39. +++ b/drivers/gpio/Makefile
  40. @@ -120,3 +120,4 @@ obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa
  41. obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
  42. obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
  43. obj-$(CONFIG_GPIO_ZX) += gpio-zx.o
  44. +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
  45. --- /dev/null
  46. +++ b/drivers/gpio/gpio-mt7621.c
  47. @@ -0,0 +1,354 @@
  48. +/*
  49. + * This program is free software; you can redistribute it and/or modify it
  50. + * under the terms of the GNU General Public License version 2 as published
  51. + * by the Free Software Foundation.
  52. + *
  53. + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  54. + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  55. + */
  56. +
  57. +#include <linux/io.h>
  58. +#include <linux/err.h>
  59. +#include <linux/gpio.h>
  60. +#include <linux/module.h>
  61. +#include <linux/of_irq.h>
  62. +#include <linux/spinlock.h>
  63. +#include <linux/irqdomain.h>
  64. +#include <linux/interrupt.h>
  65. +#include <linux/platform_device.h>
  66. +
  67. +#define MTK_MAX_BANK 3
  68. +#define MTK_BANK_WIDTH 32
  69. +
  70. +enum mediatek_gpio_reg {
  71. + GPIO_REG_CTRL = 0,
  72. + GPIO_REG_POL,
  73. + GPIO_REG_DATA,
  74. + GPIO_REG_DSET,
  75. + GPIO_REG_DCLR,
  76. + GPIO_REG_REDGE,
  77. + GPIO_REG_FEDGE,
  78. + GPIO_REG_HLVL,
  79. + GPIO_REG_LLVL,
  80. + GPIO_REG_STAT,
  81. + GPIO_REG_EDGE,
  82. +};
  83. +
  84. +static void __iomem *mediatek_gpio_membase;
  85. +static int mediatek_gpio_irq;
  86. +static struct irq_domain *mediatek_gpio_irq_domain;
  87. +static atomic_t irq_refcount = ATOMIC_INIT(0);
  88. +
  89. +struct mtk_gc {
  90. + struct gpio_chip chip;
  91. + spinlock_t lock;
  92. + int bank;
  93. + u32 rising;
  94. + u32 falling;
  95. +} *gc_map[MTK_MAX_BANK];
  96. +
  97. +static inline struct mtk_gc
  98. +*to_mediatek_gpio(struct gpio_chip *chip)
  99. +{
  100. + struct mtk_gc *mgc;
  101. +
  102. + mgc = container_of(chip, struct mtk_gc, chip);
  103. +
  104. + return mgc;
  105. +}
  106. +
  107. +static inline void
  108. +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
  109. +{
  110. + iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
  111. +}
  112. +
  113. +static inline u32
  114. +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
  115. +{
  116. + return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
  117. +}
  118. +
  119. +static void
  120. +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  121. +{
  122. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  123. +
  124. + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
  125. +}
  126. +
  127. +static int
  128. +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
  129. +{
  130. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  131. +
  132. + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
  133. +}
  134. +
  135. +static int
  136. +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  137. +{
  138. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  139. + unsigned long flags;
  140. + u32 t;
  141. +
  142. + spin_lock_irqsave(&rg->lock, flags);
  143. + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
  144. + t &= ~BIT(offset);
  145. + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
  146. + spin_unlock_irqrestore(&rg->lock, flags);
  147. +
  148. + return 0;
  149. +}
  150. +
  151. +static int
  152. +mediatek_gpio_direction_output(struct gpio_chip *chip,
  153. + unsigned offset, int value)
  154. +{
  155. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  156. + unsigned long flags;
  157. + u32 t;
  158. +
  159. + spin_lock_irqsave(&rg->lock, flags);
  160. + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
  161. + t |= BIT(offset);
  162. + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
  163. + mediatek_gpio_set(chip, offset, value);
  164. + spin_unlock_irqrestore(&rg->lock, flags);
  165. +
  166. + return 0;
  167. +}
  168. +
  169. +static int
  170. +mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  171. +{
  172. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  173. + unsigned long flags;
  174. + u32 t;
  175. +
  176. + spin_lock_irqsave(&rg->lock, flags);
  177. + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
  178. + spin_unlock_irqrestore(&rg->lock, flags);
  179. +
  180. + if (t & BIT(offset))
  181. + return 0;
  182. +
  183. + return 1;
  184. +}
  185. +
  186. +static int
  187. +mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
  188. +{
  189. + struct mtk_gc *rg = to_mediatek_gpio(chip);
  190. +
  191. + return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH));
  192. +}
  193. +
  194. +static int
  195. +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
  196. +{
  197. + const __be32 *id = of_get_property(bank, "reg", NULL);
  198. + struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
  199. + sizeof(struct mtk_gc), GFP_KERNEL);
  200. +
  201. + if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK)
  202. + return -ENOMEM;
  203. +
  204. + gc_map[be32_to_cpu(*id)] = rg;
  205. +
  206. + memset(rg, 0, sizeof(struct mtk_gc));
  207. +
  208. + spin_lock_init(&rg->lock);
  209. +
  210. + rg->chip.dev = &pdev->dev;
  211. + rg->chip.label = dev_name(&pdev->dev);
  212. + rg->chip.of_node = bank;
  213. + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
  214. + rg->chip.ngpio = MTK_BANK_WIDTH;
  215. + rg->chip.direction_input = mediatek_gpio_direction_input;
  216. + rg->chip.direction_output = mediatek_gpio_direction_output;
  217. + rg->chip.get_direction = mediatek_gpio_get_direction;
  218. + rg->chip.get = mediatek_gpio_get;
  219. + rg->chip.set = mediatek_gpio_set;
  220. + if (mediatek_gpio_irq_domain)
  221. + rg->chip.to_irq = mediatek_gpio_to_irq;
  222. + rg->bank = be32_to_cpu(*id);
  223. +
  224. + /* set polarity to low for all gpios */
  225. + mtk_gpio_w32(rg, GPIO_REG_POL, 0);
  226. +
  227. + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
  228. +
  229. + return gpiochip_add(&rg->chip);
  230. +}
  231. +
  232. +static void
  233. +mediatek_gpio_irq_handler(struct irq_desc *desc)
  234. +{
  235. + int i;
  236. +
  237. + for (i = 0; i < MTK_MAX_BANK; i++) {
  238. + struct mtk_gc *rg = gc_map[i];
  239. + unsigned long pending;
  240. + int bit;
  241. +
  242. + if (!rg)
  243. + continue;
  244. +
  245. + pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
  246. +
  247. + for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
  248. + u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit);
  249. +
  250. + generic_handle_irq(map);
  251. + mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
  252. + }
  253. + }
  254. +}
  255. +
  256. +static void
  257. +mediatek_gpio_irq_unmask(struct irq_data *d)
  258. +{
  259. + int pin = d->hwirq;
  260. + int bank = pin / 32;
  261. + struct mtk_gc *rg = gc_map[bank];
  262. + unsigned long flags;
  263. + u32 rise, fall;
  264. +
  265. + if (!rg)
  266. + return;
  267. +
  268. + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
  269. + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
  270. +
  271. + spin_lock_irqsave(&rg->lock, flags);
  272. + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
  273. + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
  274. + spin_unlock_irqrestore(&rg->lock, flags);
  275. +}
  276. +
  277. +static void
  278. +mediatek_gpio_irq_mask(struct irq_data *d)
  279. +{
  280. + int pin = d->hwirq;
  281. + int bank = pin / 32;
  282. + struct mtk_gc *rg = gc_map[bank];
  283. + unsigned long flags;
  284. + u32 rise, fall;
  285. +
  286. + if (!rg)
  287. + return;
  288. +
  289. + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
  290. + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
  291. +
  292. + spin_lock_irqsave(&rg->lock, flags);
  293. + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
  294. + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
  295. + spin_unlock_irqrestore(&rg->lock, flags);
  296. +}
  297. +
  298. +static int
  299. +mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
  300. +{
  301. + int pin = d->hwirq;
  302. + int bank = pin / 32;
  303. + struct mtk_gc *rg = gc_map[bank];
  304. + u32 mask = BIT(d->hwirq);
  305. +
  306. + if (!rg)
  307. + return -1;
  308. +
  309. + if (type == IRQ_TYPE_PROBE) {
  310. + if ((rg->rising | rg->falling) & mask)
  311. + return 0;
  312. +
  313. + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  314. + }
  315. +
  316. + if (type & IRQ_TYPE_EDGE_RISING)
  317. + rg->rising |= mask;
  318. + else
  319. + rg->rising &= ~mask;
  320. +
  321. + if (type & IRQ_TYPE_EDGE_FALLING)
  322. + rg->falling |= mask;
  323. + else
  324. + rg->falling &= ~mask;
  325. +
  326. + return 0;
  327. +}
  328. +
  329. +static struct irq_chip mediatek_gpio_irq_chip = {
  330. + .name = "GPIO",
  331. + .irq_unmask = mediatek_gpio_irq_unmask,
  332. + .irq_mask = mediatek_gpio_irq_mask,
  333. + .irq_mask_ack = mediatek_gpio_irq_mask,
  334. + .irq_set_type = mediatek_gpio_irq_type,
  335. +};
  336. +
  337. +static int
  338. +mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
  339. +{
  340. + irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
  341. + irq_set_handler_data(irq, d);
  342. +
  343. + return 0;
  344. +}
  345. +
  346. +static const struct irq_domain_ops irq_domain_ops = {
  347. + .xlate = irq_domain_xlate_onecell,
  348. + .map = mediatek_gpio_gpio_map,
  349. +};
  350. +
  351. +static int
  352. +mediatek_gpio_probe(struct platform_device *pdev)
  353. +{
  354. + struct device_node *bank, *np = pdev->dev.of_node;
  355. + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  356. +
  357. + mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res);
  358. + if (IS_ERR(mediatek_gpio_membase))
  359. + return PTR_ERR(mediatek_gpio_membase);
  360. +
  361. + mediatek_gpio_irq = irq_of_parse_and_map(np, 0);
  362. + if (mediatek_gpio_irq) {
  363. + mediatek_gpio_irq_domain = irq_domain_add_linear(np,
  364. + MTK_MAX_BANK * MTK_BANK_WIDTH,
  365. + &irq_domain_ops, NULL);
  366. + if (!mediatek_gpio_irq_domain)
  367. + dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
  368. + }
  369. +
  370. + for_each_child_of_node(np, bank)
  371. + if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
  372. + mediatek_gpio_bank_probe(pdev, bank);
  373. +
  374. + if (mediatek_gpio_irq_domain)
  375. + irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler);
  376. +
  377. + return 0;
  378. +}
  379. +
  380. +static const struct of_device_id mediatek_gpio_match[] = {
  381. + { .compatible = "mtk,mt7621-gpio" },
  382. + {},
  383. +};
  384. +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
  385. +
  386. +static struct platform_driver mediatek_gpio_driver = {
  387. + .probe = mediatek_gpio_probe,
  388. + .driver = {
  389. + .name = "mt7621_gpio",
  390. + .owner = THIS_MODULE,
  391. + .of_match_table = mediatek_gpio_match,
  392. + },
  393. +};
  394. +
  395. +static int __init
  396. +mediatek_gpio_init(void)
  397. +{
  398. + return platform_driver_register(&mediatek_gpio_driver);
  399. +}
  400. +
  401. +subsys_initcall(mediatek_gpio_init);