openwrt_chaos_calmer/package/kernel/lantiq/ltq-vmmc/patches/100-target.patch

--- a/src/drv_vmmc_access.h
+++ b/src/drv_vmmc_access.h
@@ -24,6 +24,10 @@
 #include "drv_mps_vmmc.h"
 #endif
 
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+#  define IFX_MPS IFXMIPS_MPS_BASE_ADDR
+#endif
+
 /* ============================= */
 /* Global Defines                */
 /* ============================= */
--- a/src/drv_vmmc_danube.h
+++ b/src/drv_vmmc_danube.h
@@ -15,56 +15,18 @@
 */
 
 #if defined SYSTEM_DANUBE
-#include <asm/ifx/ifx_gpio.h>
+#include <lantiq_soc.h>
+
 #else
 #error no system selected
 #endif
 
-#define VMMC_TAPI_GPIO_MODULE_ID                        IFX_GPIO_MODULE_TAPI_VMMC
+#define VMMC_TAPI_GPIO_MODULE_ID             IFX_GPIO_MODULE_TAPI_VMMC
 /**
 
 */
 #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
 do { \
-   ret = VMMC_statusOk; \
-   /* Reserve P0.0 as TDM/FSC */ \
-   if (!GPIOreserved) \
-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
-   \
-   /* Reserve P1.9 as TDM/DO */ \
-   if (!GPIOreserved) \
-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
-   \
-   /* Reserve P1.10 as TDM/DI */ \
-   if (!GPIOreserved) \
-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\
-   ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
-   \
-   /* Reserve P1.11 as TDM/DCL */ \
-   if (!GPIOreserved) \
-      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
-   \
-   if (mode == 2) { \
-      /* TDM/FSC+DCL Master */ \
-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
-      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
-   } else { \
-      /* TDM/FSC+DCL Slave */ \
-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
-      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
-   } \
 } while(0);
 
 /**
@@ -72,11 +34,6 @@
 */
 #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
 do { \
-   ret = VMMC_statusOk; \
-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
-   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
 } while (0)
 
 #endif /* _DRV_VMMC_AMAZON_S_H */
--- a/src/drv_vmmc_init.c
+++ b/src/drv_vmmc_init.c
@@ -52,6 +52,14 @@
 #include "ifx_pmu.h"
 #endif /* PMU_SUPPORTED */
 
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+#  define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
+#  define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
+#  define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
+#  define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
+#  define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
+#  define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
+#endif
 
 /* ============================= */
 /* Local Macros & Definitions    */
@@ -1591,7 +1599,7 @@
 #ifdef VMMC_DRIVER_UNLOAD_HOOK
    if (VDevices[0].nDevState & DS_GPIO_RESERVED)
    {
-      IFX_int32_t ret;
+      IFX_int32_t ret = 0;
       VMMC_DRIVER_UNLOAD_HOOK(ret);
       if (!VMMC_SUCCESS(ret))
       {
--- a/src/drv_vmmc_init_cap.c
+++ b/src/drv_vmmc_init_cap.c
@@ -22,6 +22,11 @@
 #include "drv_mps_vmmc.h"
 #include "drv_mps_vmmc_device.h"
 
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+#  define IFX_MPS_CHIPID_VERSION_GET   IFXMIPS_MPS_CHIPID_VERSION_GET
+#  define IFX_MPS_CHIPID               IFXMIPS_MPS_CHIPID
+#endif
+
 /* ============================= */
 /* Configuration defintions      */
 /* ============================= */
--- a/src/mps/drv_mps_vmmc_common.c
+++ b/src/mps/drv_mps_vmmc_common.c
@@ -17,6 +17,7 @@
 /* Includes                      */
 /* ============================= */
 #include "drv_config.h"
+#include "drv_vmmc_init.h"
 
 #undef USE_PLAIN_VOICE_FIRMWARE
 #undef PRINT_ON_ERR_INTERRUPT
@@ -39,8 +40,32 @@
 #include "ifxos_interrupt.h"
 #include "ifxos_time.h"
 
-#include <asm/ifx/ifx_regs.h>
-#include <asm/ifx/ifx_gptu.h>
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+#  include <lantiq.h>
+#  include <irq.h>
+#  include <lantiq_timer.h>
+
+#  define ifx_gptu_timer_request    lq_request_timer
+#  define ifx_gptu_timer_start      lq_start_timer
+#  define ifx_gptu_countvalue_get   lq_get_count_value
+#  define ifx_gptu_timer_free       lq_free_timer
+
+
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))
+#  define bsp_mask_and_ack_irq      ltq_mask_and_ack_irq
+#else
+extern void ltq_mask_and_ack_irq(struct irq_data *d);
+static void inline bsp_mask_and_ack_irq(int x)
+{
+	struct irq_data d;
+	d.hwirq = x;
+	ltq_mask_and_ack_irq(&d);
+}
+#endif
+#else
+#  include <asm/ifx/ifx_regs.h>
+#  include <asm/ifx/ifx_gptu.h>
+#endif
 
 #include "drv_mps_vmmc.h"
 #include "drv_mps_vmmc_dbg.h"
@@ -104,6 +129,9 @@
 extern IFX_void_t mask_and_ack_danube_irq (IFX_uint32_t irq_nr);
 
 #endif /* */
+
+extern void sys_hw_setup (void);
+
 extern IFXOS_event_t fw_ready_evt;
 /* callback function to free all data buffers currently used by voice FW */
 IFX_void_t (*ifx_mps_bufman_freeall)(IFX_void_t) = IFX_NULL;
@@ -207,7 +235,8 @@
  */
 IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
 {
-   IFX_uint32_t ptr, flags;
+   IFXOS_INTSTAT flags;
+   IFX_uint32_t ptr;
    IFX_int32_t index = fastbuf_index;
 
    if (fastbuf_initialized == 0)
@@ -261,7 +290,7 @@
  */
 IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
 {
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
    IFX_int32_t index = fastbuf_index;
 
    IFXOS_LOCKINT (flags);
@@ -457,7 +486,7 @@
  */
 static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
 {
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
 
    if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
    {
@@ -484,7 +513,7 @@
  */
 static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
 {
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
 
    if (mps_buffer.buf_level < value)
    {
@@ -636,7 +665,7 @@
       mem_seg_ptr[i] =
          (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) mps_buffer.
                                      malloc (segment_size, FASTBUF_FW_OWNED));
-      if (mem_seg_ptr[i] == CPHYSADDR (IFX_NULL))
+      if (mem_seg_ptr[i] == (IFX_uint32_t *)CPHYSADDR (IFX_NULL))
       {
          TRACE (MPS, DBG_LEVEL_HIGH,
                 ("%s(): cannot allocate buffer\n", __FUNCTION__));
@@ -952,7 +981,7 @@
                                  mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
                                  IFX_boolean_t from_kernel)
 {
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
 
    IFXOS_LOCKINT (flags);
 
@@ -1068,7 +1097,7 @@
 IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
 {
    IFX_int32_t count;
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
 
    IFXOS_LOCKINT (flags);
    IFXOS_BlockFree (pFW_img_data);
@@ -1117,7 +1146,7 @@
 
    /* Initialize MPS main structure */
    memset ((IFX_void_t *) pDev, 0, sizeof (mps_comm_dev));
-   pDev->base_global = (mps_mbx_reg *) IFX_MPS_SRAM;
+   pDev->base_global = (mps_mbx_reg *) IFXMIPS_MPS_SRAM;
    pDev->flags = 0x00000000;
    MBX_Memory = pDev->base_global;
 
@@ -1125,9 +1154,11 @@
       for MBX communication. These are: mailbox base address, mailbox size, *
       mailbox read index and mailbox write index. for command and voice
       mailbox, * upstream and downstream direction. */
-   memset ((IFX_void_t *) MBX_Memory,   /* avoid to overwrite CPU boot
-                                           registers */
-           0, sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
+   memset (
+	/* avoid to overwrite CPU boot registers */
+	   (IFX_void_t *) MBX_Memory,
+           0,
+           sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
    MBX_Memory->MBX_UPSTR_CMD_BASE =
       (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) MBX_UPSTRM_CMD_FIFO_BASE);
    MBX_Memory->MBX_UPSTR_CMD_SIZE = MBX_CMD_FIFO_SIZE;
@@ -1564,7 +1595,7 @@
                                       IFX_uint32_t * bytes)
 {
    IFX_int32_t i, ret;
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
 
    IFXOS_LOCKINT (flags);
 
@@ -1774,7 +1805,7 @@
 {
    mps_fifo *mbx;
    IFX_uint32_t i;
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
    IFX_int32_t retval = -EAGAIN;
    IFX_int32_t retries = 0;
    IFX_uint32_t word = 0;
@@ -2169,6 +2200,7 @@
       TRACE (MPS, DBG_LEVEL_HIGH,
              ("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
    }
+
    return retval;
 }
 
@@ -2192,7 +2224,7 @@
    mps_mbx_dev *mbx_dev;
    MbxMsg_s msg;
    IFX_uint32_t bytes_read = 0;
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
    IFX_int32_t ret;
 
    /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
@@ -2283,7 +2315,7 @@
          {
             ifx_mps_bufman_dec_level (1);
             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
+                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
             {
                IFXOS_LockRelease (pMPSDev->provide_buffer);
             }
@@ -2326,7 +2358,7 @@
 #endif /* CONFIG_PROC_FS */
             ifx_mps_bufman_dec_level (1);
             if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
-                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
+                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
             {
                IFXOS_LockRelease (pMPSDev->provide_buffer);
             }
@@ -2356,7 +2388,7 @@
 IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
 {
    mps_fifo *mbx;
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
 
    /* set pointer to upstream command mailbox */
    mbx = &(pMPSDev->cmd_upstrm_fifo);
@@ -2404,7 +2436,7 @@
    mps_event_msg msg;
    IFX_int32_t length = 0;
    IFX_int32_t read_length = 0;
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
 
    /* set pointer to upstream event mailbox */
    mbx = &(pMPSDev->event_upstrm_fifo);
@@ -2619,6 +2651,7 @@
 #endif
 
    *IFX_MPS_AD0ENR = Ad0Reg.val;
+
 }
 
 /**
@@ -2647,7 +2680,7 @@
 */
 IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
 {
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
    MPS_Ad0Reg_u Ad0Reg;
 
    IFXOS_LOCKINT (flags);
@@ -2673,7 +2706,7 @@
 */
 IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
 {
-   IFX_uint32_t flags;
+   IFXOS_INTSTAT flags;
    MPS_Ad0Reg_u Ad0Reg;
 
    IFXOS_LOCKINT (flags);
@@ -2738,7 +2771,6 @@
 #else /* */
    mask_and_ack_danube_irq (irq);
 #endif /* */
-
    /* FW is up and ready to process commands */
    if (MPS_Ad0StatusReg.fld.dl_end)
    {
@@ -2800,6 +2832,7 @@
       }
    }
 
+
    if (MPS_Ad0StatusReg.fld.du_mbx)
    {
 #ifdef CONFIG_PROC_FS
@@ -2944,12 +2977,12 @@
    IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
    /* handle only enabled interrupts */
    MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
-
 #ifdef LINUX_2_6
    bsp_mask_and_ack_irq (irq);
 #else /* */
    mask_and_ack_danube_irq (irq);
 #endif /* */
+
    pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;
 #ifdef PRINT_ON_ERR_INTERRUPT
    if (MPS_VCStatusReg.fld.rcv_ov)
@@ -3093,7 +3126,8 @@
  */
 IFX_return_t ifx_mps_init_gpt ()
 {
-   IFX_uint32_t flags, timer_flags, timer, loops = 0;
+   unsigned long flags;
+   IFX_uint32_t timer_flags, timer, loops = 0;
    IFX_ulong_t count;
 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
    timer = TIMER1A;
@@ -3166,6 +3200,7 @@
 #else /* Danube */
    timer = TIMER1B;
 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
+
    ifx_gptu_timer_free (timer);
 }
 
--- a/src/mps/drv_mps_vmmc_danube.c
+++ b/src/mps/drv_mps_vmmc_danube.c
@@ -16,6 +16,7 @@
 /* ============================= */
 /* Includes                      */
 /* ============================= */
+#include "linux/version.h"
 #include "drv_config.h"
 
 #ifdef SYSTEM_DANUBE            /* defined in drv_mps_vmmc_config.h */
@@ -36,9 +37,22 @@
 #include "ifxos_select.h"
 #include "ifxos_interrupt.h"
 
-#include <asm/ifx/ifx_regs.h>
-#include <asm/ifx/ifx_gpio.h>
-#include <asm/ifx/common_routines.h>
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+#  include <lantiq.h>
+#  include <irq.h>
+#  include <lantiq_timer.h>
+#  include <linux/dma-mapping.h>
+
+
+#define LQ_RCU_BASE_ADDR	(KSEG1 + LTQ_RCU_BASE_ADDR)
+# define LQ_RCU_RST		((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
+#define IFX_RCU_RST_REQ_CPU1             (1 << 3)
+#  define IFX_RCU_RST_REQ        LQ_RCU_RST
+#else
+#  include <asm/ifx/ifx_regs.h>
+#  include <asm/ifx_vpe.h>
+#  include <asm/ifx/ifx_gpio.h>
+#endif
 
 #include "drv_mps_vmmc.h"
 #include "drv_mps_vmmc_dbg.h"
@@ -75,6 +89,20 @@
 /* Local function definition     */
 /* ============================= */
 
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+IFX_uint32_t ifx_get_cp1_size(IFX_void_t)
+{
+	return 1;
+}
+
+unsigned int *ltq_get_cp1_base(void);
+
+IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)
+{
+	return ltq_get_cp1_base();
+}
+#endif
+
 /******************************************************************************
  * DANUBE Specific Routines
  ******************************************************************************/
@@ -134,6 +162,15 @@
    }
 
    /* check if FW image fits in available memory space */
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+   if (mem > ifx_get_cp1_size()<<20)
+   {
+      TRACE (MPS, DBG_LEVEL_HIGH,
+      ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
+                 __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));
+      return IFX_ERROR;
+   }
+#else
    if (mem > ifx_get_cp1_size())
    {
       TRACE (MPS, DBG_LEVEL_HIGH,
@@ -141,6 +178,7 @@
                  __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
       return IFX_ERROR;
    }
+#endif
 
    /* reset the driver */
    ifx_mps_reset ();
@@ -361,7 +399,7 @@
  */
 IFX_void_t ifx_mps_wdog_expiry()
 {
-   IFX_uint32_t flags;
+   unsigned long flags;
 
    IFXOS_LOCKINT (flags);
    /* recalculate and compare the firmware checksum */
--- a/src/mps/drv_mps_vmmc_device.h
+++ b/src/mps/drv_mps_vmmc_device.h
@@ -16,8 +16,58 @@
                  declarations.
 *******************************************************************************/
 
-#include <asm/ifx/ifx_regs.h>
-#include <asm/ifx_vpe.h>
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
+#  include <lantiq.h>
+#  include <irq.h>
+#  include <lantiq_soc.h>
+#  include <gpio.h>
+#define IFXMIPS_MPS_SRAM		((u32 *)(KSEG1 + 0x1F200000))
+#define IFXMIPS_MPS_BASE_ADDR		(KSEG1 + 0x1F107000)
+#define IFXMIPS_MPS_CHIPID		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
+#define IFXMIPS_MPS_VC0ENR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
+#define IFXMIPS_MPS_RVC0SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
+#define IFXMIPS_MPS_CVC0SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
+#define IFXMIPS_MPS_CVC1SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
+#define IFXMIPS_MPS_CVC2SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
+#define IFXMIPS_MPS_CVC3SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
+#define IFXMIPS_MPS_RAD0SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
+#define IFXMIPS_MPS_RAD1SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
+#define IFXMIPS_MPS_SAD0SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
+#define IFXMIPS_MPS_SAD1SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
+#define IFXMIPS_MPS_CAD0SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
+#define IFXMIPS_MPS_CAD1SR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
+#define IFXMIPS_MPS_AD0ENR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
+#define IFXMIPS_MPS_AD1ENR		((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
+
+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)	(((value) >> 28) & ((1 << 4) - 1))
+#define IFXMIPS_MPS_CHIPID_VERSION_SET(value)	((((1 << 4) - 1) & (value)) << 28)
+#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)	(((value) >> 12) & ((1 << 16) - 1))
+#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)	((((1 << 16) - 1) & (value)) << 12)
+#define IFXMIPS_MPS_CHIPID_MANID_GET(value)	(((value) >> 1) & ((1 << 10) - 1))
+#define IFXMIPS_MPS_CHIPID_MANID_SET(value)	((((1 << 10) - 1) & (value)) << 1)
+#else
+#  include <asm/ifx/ifx_regs.h>
+#  include <asm/ifx_vpe.h>
+#endif
+/* MPS register */
+#  define IFX_MPS_AD0ENR      IFXMIPS_MPS_AD0ENR
+#  define IFX_MPS_AD1ENR      IFXMIPS_MPS_AD1ENR
+#  define IFX_MPS_RAD0SR      IFXMIPS_MPS_RAD0SR
+#  define IFX_MPS_RAD1SR      IFXMIPS_MPS_RAD1SR
+#  define IFX_MPS_VC0ENR      IFXMIPS_MPS_VC0ENR
+#  define IFX_MPS_RVC0SR      IFXMIPS_MPS_RVC0SR
+#  define IFX_MPS_CVC0SR      IFXMIPS_MPS_CVC0SR
+#  define IFX_MPS_CAD0SR      IFXMIPS_MPS_CAD0SR
+#  define IFX_MPS_CAD1SR      IFXMIPS_MPS_CAD1SR
+#  define IFX_MPS_CVC1SR      IFXMIPS_MPS_CVC1SR
+#  define IFX_MPS_CVC2SR      IFXMIPS_MPS_CVC2SR
+#  define IFX_MPS_CVC3SR      IFXMIPS_MPS_CVC3SR
+#  define IFX_MPS_SAD0SR      IFXMIPS_MPS_SAD0SR
+/* interrupt vectors */
+#  define INT_NUM_IM4_IRL14   (INT_NUM_IM4_IRL0 + 14)
+#  define INT_NUM_IM4_IRL18   (INT_NUM_IM4_IRL0 + 18)
+#  define INT_NUM_IM4_IRL19   (INT_NUM_IM4_IRL0 + 19)
+#  define IFX_ICU_IM4_IER     IFXMIPS_ICU_IM4_IER
 
 /* ============================= */
 /* MPS Common defines            */
@@ -26,32 +76,28 @@
 #define MPS_BASEADDRESS 0xBF107000
 #define MPS_RAD0SR      MPS_BASEADDRESS + 0x0004
 
-#define MPS_RAD0SR_DU   (1<<0)
-#define MPS_RAD0SR_CU   (1<<1)
-
 #define MBX_BASEADDRESS 0xBF200000
 #define VCPU_BASEADDRESS 0xBF208000     /* 0xBF108000 */
 /*---------------------------------------------------------------------------*/
+#if !defined(CONFIG_LANTIQ)
+/* enabling interrupts is done with request_irq by the BSP
+   The related code should not be needed anymore */
 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 /* TODO: doublecheck - IM4 or different! */
 #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
 #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
-#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
-#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
 #else /* Danube */
 /* TODO: possibly needs to be changed to IM4 !!!!!! */
 #ifdef LINUX_2_6
 #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
 #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
-#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
-#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
 #else /* */
 #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) |= X;
 #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) &= ~X;
-#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_ISR) = X;
-#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IRSR) = X;/* |= ? */
 #endif /* LINUX_2_6 */
 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
+#endif /* !defined(CONFIG_LANTIQ) */
+
 /*---------------------------------------------------------------------------*/
 
 /*---------------------------------------------------------------------------*/
@@ -142,53 +188,9 @@
 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 /* ***** Amazon-S specific defines ***** */
 #define IFX_MPS_Base      AMAZON_S_MPS
-
-//#define IFX_MPS_CHIPID              AMAZON_S_MPS_CHIPID
-//#define IFX_MPS_CHIPID_VERSION_GET  AMAZON_S_MPS_CHIPID_VERSION_GET
-
-//#define IFX_MPS_AD0ENR    AMAZON_S_MPS_AD0ENR
-//#define IFX_MPS_AD1ENR    AMAZON_S_MPS_AD1ENR
-//#define IFX_MPS_VC0ENR    AMAZON_S_MPS_VC0ENR
-//#define IFX_MPS_SAD0SR    AMAZON_S_MPS_SAD0SR
-//#define IFX_MPS_RAD0SR    AMAZON_S_MPS_RAD0SR
-//#define IFX_MPS_CAD0SR    AMAZON_S_MPS_CAD0SR
-//#define IFX_MPS_RAD1SR    AMAZON_S_MPS_RAD1SR
-//#define IFX_MPS_CAD1SR    AMAZON_S_MPS_CAD1SR
-//#define IFX_MPS_RVC0SR    AMAZON_S_MPS_RVC0SR
-//#define IFX_MPS_CVC0SR    AMAZON_S_MPS_CVC0SR
-//#define IFX_MPS_CVC1SR    AMAZON_S_MPS_CVC1SR
-//#define IFX_MPS_CVC2SR    AMAZON_S_MPS_CVC2SR
-//#define IFX_MPS_CVC3SR    AMAZON_S_MPS_CVC3SR
-
-//#define IFX_MPS_SRAM      AMAZON_S_MPS_SRAM
 #else /* */
 /* ***** DANUBE specific defines ***** */
 #define IFX_MPS_Base      DANUBE_MPS
-
-//#define IFX_MPS_CHIPID    DANUBE_MPS_CHIPID
-//#define IFX_MPS_CHIPID_VERSION_GET  DANUBE_MPS_CHIPID_VERSION_GET
-//#define IFX_MPS_CHIPID_VERSION_SET  DANUBE_MPS_CHIPID_VERSION_SET
-//#define IFX_MPS_CHIPID_PARTNUM_GET  DANUBE_MPS_CHIPID_PARTNUM_GET
-//#define IFX_MPS_CHIPID_PARTNUM_SET  DANUBE_MPS_CHIPID_PARTNUM_SET
-//#define IFX_MPS_CHIPID_MANID_GET    DANUBE_MPS_CHIPID_MANID_GET
-//#define IFX_MPS_CHIPID_MANID_SET    DANUBE_MPS_CHIPID_MANID_SET
-//#define IFX_MPS_SUBVER              DANUBE_MPS_SUBVER
-
-//#define IFX_MPS_AD0ENR    DANUBE_MPS_AD0ENR
-//#define IFX_MPS_AD1ENR    DANUBE_MPS_AD1ENR
-//#define IFX_MPS_VC0ENR    DANUBE_MPS_VC0ENR
-//#define IFX_MPS_SAD0SR    DANUBE_MPS_SAD0SR
-//#define IFX_MPS_RAD0SR    DANUBE_MPS_RAD0SR
-//#define IFX_MPS_CAD0SR    DANUBE_MPS_CAD0SR
-//#define IFX_MPS_RAD1SR    DANUBE_MPS_RAD1SR
-//#define IFX_MPS_CAD1SR    DANUBE_MPS_CAD1SR
-//#define IFX_MPS_RVC0SR    DANUBE_MPS_RVC0SR
-//#define IFX_MPS_CVC0SR    DANUBE_MPS_CVC0SR
-//#define IFX_MPS_CVC1SR    DANUBE_MPS_CVC1SR
-//#define IFX_MPS_CVC2SR    DANUBE_MPS_CVC2SR
-//#define IFX_MPS_CVC3SR    DANUBE_MPS_CVC3SR
-
-//#define IFX_MPS_SRAM      DANUBE_MPS_SRAM
 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
 typedef enum
 {
--- a/src/mps/drv_mps_vmmc_linux.c
+++ b/src/mps/drv_mps_vmmc_linux.c
@@ -57,10 +57,11 @@
 #include <linux/moduleparam.h>
 #endif /* */
 
-
+#if !defined CONFIG_LANTIQ
 #include <asm/ifx/irq.h>
 #include <asm/ifx/ifx_regs.h>
 #include <asm/ifx_vpe.h>
+#endif
 
 /* lib_ifxos headers */
 #include "ifx_types.h"
@@ -959,7 +960,7 @@
 #endif /* MPS_FIFO_BLOCKING_WRITE */
       case FIO_MPS_GET_STATUS:
          {
-            IFX_uint32_t flags;
+            unsigned long flags;
 
             /* get the status of the channel */
             if (!from_kernel)
@@ -993,7 +994,7 @@
 #if CONFIG_MPS_HISTORY_SIZE > 0
       case FIO_MPS_GET_CMD_HISTORY:
          {
-            IFX_uint32_t flags;
+            unsigned long flags;
 
             if (from_kernel)
             {
@@ -1685,6 +1686,7 @@
          sprintf (buf + len, "   minLv: \t  %8d\n",
                   ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
    }
+
    return len;
 }
 
@@ -2291,9 +2293,11 @@
          return result;
    }
 
+#if !defined(CONFIG_LANTIQ)
+   /** \todo This is handled already with request_irq, remove */
    /* Enable all MPS Interrupts at ICU0 */
    MPS_INTERRUPTS_ENABLE (0x0000FF80);
-
+#endif
    /* enable mailbox interrupts */
    ifx_mps_enable_mailbox_int ();
    /* init FW ready event */
@@ -2421,9 +2425,11 @@
    /* disable mailbox interrupts */
    ifx_mps_disable_mailbox_int ();
 
+#if !defined(CONFIG_LANTIQ)
    /* disable Interrupts at ICU0 */
-   MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4); /* Disable DFE/AFE 0 Interrupts
-                                                 */
+   /* Disable DFE/AFE 0 Interrupts*/
+   MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4);
+#endif
 
    /* disable all MPS interrupts */
    ifx_mps_disable_all_int ();
--- a/src/drv_vmmc_ioctl.c
+++ b/src/drv_vmmc_ioctl.c
@@ -18,6 +18,7 @@
 /* Includes                      */
 /* ============================= */
 #include "drv_api.h"
+#include "drv_vmmc_init.h"
 #include "drv_vmmc_api.h"
 #include "drv_vmmc_bbd.h"

Index: drv_vmmc-1.9.0/src/mps/drv_mps_vmmc_danube.c
===================================================================
--- drv_vmmc-1.9.0.orig/src/mps/drv_mps_vmmc_danube.c	2012-12-13 08:43:16.080109377 +0100
+++ drv_vmmc-1.9.0/src/mps/drv_mps_vmmc_danube.c	2012-12-13 08:43:48.584110192 +0100
@@ -44,7 +44,7 @@
 #  include <linux/dma-mapping.h>
 
 
-#define LQ_RCU_BASE_ADDR	(KSEG1 + LTQ_RCU_BASE_ADDR)
+#define LQ_RCU_BASE_ADDR	(KSEG1 + 0x1F203000)
 # define LQ_RCU_RST		((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
 #define IFX_RCU_RST_REQ_CPU1             (1 << 3)
 #  define IFX_RCU_RST_REQ        LQ_RCU_RST