321-irqchip-add-support-for-bcm6345-style-external-inter.patch 10 KB

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  1. From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001
  2. From: Jonas Gorski <jogo@openwrt.org>
  3. Date: Sun, 30 Nov 2014 14:54:27 +0100
  4. Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
  5. interrupt controller
  6. Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  7. ---
  8. .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++
  9. drivers/irqchip/Kconfig | 4 +
  10. drivers/irqchip/Makefile | 1 +
  11. drivers/irqchip/irq-bcm6345-ext.c | 287 ++++++++++++++++++++
  12. include/linux/irqchip/irq-bcm6345-ext.h | 14 +
  13. 5 files changed, 335 insertions(+)
  14. create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  15. create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
  16. create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h
  17. --- /dev/null
  18. +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
  19. @@ -0,0 +1,29 @@
  20. +Broadcom BCM6345-style external interrupt controller
  21. +
  22. +Required properties:
  23. +
  24. +- compatible: Should be "brcm,bcm6345-l2-intc".
  25. +- reg: Specifies the base physical addresses and size of the registers.
  26. +- interrupt-controller: identifies the node as an interrupt controller.
  27. +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
  28. + source, Should be 2.
  29. +- interrupt-parent: Specifies the phandle to the parent interrupt controller
  30. + this one is cascaded from.
  31. +- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
  32. + node, valid values depend on the type of parent interrupt controller.
  33. +
  34. +Optional properties:
  35. +
  36. +- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the
  37. + register. Defaults to 4.
  38. +
  39. +Example:
  40. +
  41. +ext_intc: interrupt-controller@10000018 {
  42. + compatible = "brcm,bcm6345-l2-intc";
  43. + interrupt-parent = <&periph_intc>;
  44. + #interrupt-cells = <2>;
  45. + reg = <0x10000018 0x4>;
  46. + interrupt-controller;
  47. + interrupts = <24>, <25>, <26>, <27>;
  48. +};
  49. --- a/drivers/irqchip/Kconfig
  50. +++ b/drivers/irqchip/Kconfig
  51. @@ -54,6 +54,10 @@ config BRCMSTB_L2_IRQ
  52. select GENERIC_IRQ_CHIP
  53. select IRQ_DOMAIN
  54. +config BCM6345_EXT_IRQ
  55. + bool
  56. + select IRQ_DOMAIN
  57. +
  58. config BCM6345_PERIPH_IRQ
  59. bool
  60. select IRQ_DOMAIN
  61. --- a/drivers/irqchip/Makefile
  62. +++ b/drivers/irqchip/Makefile
  63. @@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
  64. obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
  65. obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
  66. obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
  67. +obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o
  68. obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
  69. obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
  70. obj-$(CONFIG_METAG) += irq-metag-ext.o
  71. --- /dev/null
  72. +++ b/drivers/irqchip/irq-bcm6345-ext.c
  73. @@ -0,0 +1,287 @@
  74. +/*
  75. + * This file is subject to the terms and conditions of the GNU General Public
  76. + * License. See the file "COPYING" in the main directory of this archive
  77. + * for more details.
  78. + *
  79. + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
  80. + */
  81. +
  82. +#include <linux/ioport.h>
  83. +#include <linux/irq.h>
  84. +#include <linux/irqchip/chained_irq.h>
  85. +#include <linux/irqchip/irq-bcm6345-ext.h>
  86. +#include <linux/kernel.h>
  87. +#include <linux/of.h>
  88. +#include <linux/of_irq.h>
  89. +#include <linux/of_address.h>
  90. +#include <linux/slab.h>
  91. +#include <linux/spinlock.h>
  92. +
  93. +#include "irqchip.h"
  94. +
  95. +#ifdef CONFIG_BCM63XX
  96. +#include <asm/mach-bcm63xx/bcm63xx_irq.h>
  97. +
  98. +#define VIRQ_BASE IRQ_EXTERNAL_BASE
  99. +#else
  100. +#define VIRQ_BASE 0
  101. +#endif
  102. +
  103. +#define MAX_IRQS 4
  104. +
  105. +#define EXTIRQ_CFG_SENSE 0
  106. +#define EXTIRQ_CFG_STAT 1
  107. +#define EXTIRQ_CFG_CLEAR 2
  108. +#define EXTIRQ_CFG_MASK 3
  109. +#define EXTIRQ_CFG_BOTHEDGE 4
  110. +#define EXTIRQ_CFG_LEVELSENSE 5
  111. +
  112. +struct intc_data {
  113. + struct irq_chip chip;
  114. + struct irq_domain *domain;
  115. + raw_spinlock_t lock;
  116. +
  117. + int parent_irq[MAX_IRQS];
  118. + void __iomem *reg;
  119. + int shift;
  120. +};
  121. +
  122. +static void bcm6345_ext_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
  123. +{
  124. + struct intc_data *data = irq_desc_get_handler_data(desc);
  125. + struct irq_chip *chip = irq_desc_get_chip(desc);
  126. + unsigned int idx;
  127. +
  128. + chained_irq_enter(chip, desc);
  129. +
  130. + for (idx = 0; idx < MAX_IRQS; idx++) {
  131. + if (data->parent_irq[idx] != irq)
  132. + continue;
  133. +
  134. + generic_handle_irq(irq_find_mapping(data->domain, idx));
  135. + }
  136. +
  137. + chained_irq_exit(chip, desc);
  138. +}
  139. +
  140. +static void bcm6345_ext_intc_irq_ack(struct irq_data *data)
  141. +{
  142. + struct intc_data *priv = data->domain->host_data;
  143. + irq_hw_number_t hwirq = irqd_to_hwirq(data);
  144. + u32 reg;
  145. +
  146. + raw_spin_lock(&priv->lock);
  147. + reg = __raw_readl(priv->reg);
  148. + reg |= hwirq << (EXTIRQ_CFG_CLEAR * priv->shift);
  149. + __raw_writel(reg, priv->reg);
  150. + raw_spin_unlock(&priv->lock);
  151. +}
  152. +
  153. +static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
  154. +{
  155. + struct intc_data *priv = data->domain->host_data;
  156. + irq_hw_number_t hwirq = irqd_to_hwirq(data);
  157. + u32 reg;
  158. +
  159. + raw_spin_lock(&priv->lock);
  160. + reg = __raw_readl(priv->reg);
  161. + reg &= ~(hwirq << (EXTIRQ_CFG_MASK * priv->shift));
  162. + __raw_writel(reg, priv->reg);
  163. + raw_spin_unlock(&priv->lock);
  164. +}
  165. +
  166. +static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
  167. +{
  168. + struct intc_data *priv = data->domain->host_data;
  169. + irq_hw_number_t hwirq = irqd_to_hwirq(data);
  170. + u32 reg;
  171. +
  172. + raw_spin_lock(&priv->lock);
  173. + reg = __raw_readl(priv->reg);
  174. + reg |= hwirq << (EXTIRQ_CFG_MASK * priv->shift);
  175. + __raw_writel(reg, priv->reg);
  176. + raw_spin_unlock(&priv->lock);
  177. +}
  178. +
  179. +static int bcm6345_ext_intc_set_type(struct irq_data *data,
  180. + unsigned int flow_type)
  181. +{
  182. + struct intc_data *priv = data->domain->host_data;
  183. + irq_hw_number_t hwirq = irqd_to_hwirq(data);
  184. + bool levelsense = 0, sense = 0, bothedge = 0;
  185. + u32 reg;
  186. +
  187. + flow_type &= IRQ_TYPE_SENSE_MASK;
  188. +
  189. + if (flow_type == IRQ_TYPE_NONE)
  190. + flow_type = IRQ_TYPE_LEVEL_LOW;
  191. +
  192. + switch (flow_type) {
  193. + case IRQ_TYPE_EDGE_BOTH:
  194. + bothedge = 1;
  195. + break;
  196. +
  197. + case IRQ_TYPE_EDGE_RISING:
  198. + break;
  199. +
  200. + case IRQ_TYPE_EDGE_FALLING:
  201. + sense = 1;
  202. + break;
  203. +
  204. + case IRQ_TYPE_LEVEL_HIGH:
  205. + levelsense = 1;
  206. + sense = 1;
  207. + break;
  208. +
  209. + case IRQ_TYPE_LEVEL_LOW:
  210. + levelsense = 1;
  211. + break;
  212. +
  213. + default:
  214. + pr_err("bogus flow type combination given!\n");
  215. + return -EINVAL;
  216. + }
  217. +
  218. + raw_spin_lock(&priv->lock);
  219. + reg = __raw_readl(priv->reg);
  220. +
  221. + if (levelsense)
  222. + reg |= hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift);
  223. + else
  224. + reg &= ~(hwirq << (EXTIRQ_CFG_LEVELSENSE * priv->shift));
  225. + if (sense)
  226. + reg |= hwirq << (EXTIRQ_CFG_SENSE * priv->shift);
  227. + else
  228. + reg &= ~(hwirq << (EXTIRQ_CFG_SENSE * priv->shift));
  229. + if (bothedge)
  230. + reg |= hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift);
  231. + else
  232. + reg &= ~(hwirq << (EXTIRQ_CFG_BOTHEDGE * priv->shift));
  233. +
  234. + __raw_writel(reg, priv->reg);
  235. + raw_spin_unlock(&priv->lock);
  236. +
  237. + irqd_set_trigger_type(data, flow_type);
  238. + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
  239. + __irq_set_handler_locked(data->irq, handle_level_irq);
  240. + else
  241. + __irq_set_handler_locked(data->irq, handle_edge_irq);
  242. +
  243. + return 0;
  244. +}
  245. +
  246. +static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,
  247. + irq_hw_number_t hw)
  248. +{
  249. + struct intc_data *priv = d->host_data;
  250. +
  251. + irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
  252. +
  253. + return 0;
  254. +}
  255. +
  256. +static const struct irq_domain_ops bcm6345_ext_domain_ops = {
  257. + .xlate = irq_domain_xlate_twocell,
  258. + .map = bcm6345_ext_intc_map,
  259. +};
  260. +
  261. +static int __init __bcm6345_ext_intc_init(struct device_node *node,
  262. + int num_irqs, int *irqs,
  263. + void __iomem *reg, int shift)
  264. +{
  265. + struct intc_data *data;
  266. + unsigned int i;
  267. + int start = VIRQ_BASE;
  268. +
  269. + data = kzalloc(sizeof(*data), GFP_KERNEL);
  270. + if (!data)
  271. + return -ENOMEM;
  272. +
  273. + raw_spin_lock_init(&data->lock);
  274. +
  275. + for (i = 0; i < num_irqs; i++) {
  276. + data->parent_irq[i] = irqs[i];
  277. +
  278. + irq_set_handler_data(irqs[i], data);
  279. + irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);
  280. + }
  281. +
  282. + data->reg = reg;
  283. +
  284. + data->chip.name = "bcm6345-ext-intc";
  285. + data->chip.irq_ack = bcm6345_ext_intc_irq_ack;
  286. + data->chip.irq_mask = bcm6345_ext_intc_irq_mask;
  287. + data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;
  288. + data->chip.irq_set_type = bcm6345_ext_intc_set_type;
  289. +
  290. + /*
  291. + * If we have less than 4 irqs, this is the second controller on
  292. + * bcm63xx. So increase the VIRQ start to not overlap with the first
  293. + * one, but only do so if we actually use a non-zero start.
  294. + *
  295. + * This can be removed when bcm63xx has no legacy users anymore.
  296. + */
  297. + if (start && num_irqs < 4)
  298. + start += 4;
  299. +
  300. + data->domain = irq_domain_add_simple(node, num_irqs, start,
  301. + &bcm6345_ext_domain_ops, data);
  302. + if (!data->domain) {
  303. + kfree(data);
  304. + return -ENOMEM;
  305. + }
  306. +
  307. + return 0;
  308. +}
  309. +
  310. +void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,
  311. + int shift)
  312. +{
  313. + __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift);
  314. +}
  315. +
  316. +#ifdef CONFIG_OF
  317. +static int __init bcm6345_ext_intc_of_init(struct device_node *node,
  318. + struct device_node *parent)
  319. +{
  320. + int num_irqs, ret = -EINVAL;
  321. + unsigned i;
  322. + void __iomem *base;
  323. + int irqs[MAX_IRQS] = { 0 };
  324. + u32 shift;
  325. +
  326. + num_irqs = of_irq_count(node);
  327. +
  328. + if (!num_irqs || num_irqs > MAX_IRQS)
  329. + return -EINVAL;
  330. +
  331. + if (of_property_read_u32(node, "brcm,field-width", &shift))
  332. + shift = 4;
  333. +
  334. + for (i = 0; i < num_irqs; i++) {
  335. + irqs[i] = irq_of_parse_and_map(node, i);
  336. + if (!irqs[i]) {
  337. + ret = -ENOMEM;
  338. + goto out_unmap;
  339. + }
  340. + }
  341. +
  342. + base = of_iomap(node, 0);
  343. + if (!base)
  344. + goto out_unmap;
  345. +
  346. + ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift);
  347. + if (!ret)
  348. + return 0;
  349. +out_unmap:
  350. + iounmap(base);
  351. +
  352. + for (i = 0; i < num_irqs; i++)
  353. + irq_dispose_mapping(irqs[i]);
  354. +
  355. + return ret;
  356. +}
  357. +
  358. +IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
  359. + bcm6345_ext_intc_of_init);
  360. +#endif
  361. --- /dev/null
  362. +++ b/include/linux/irqchip/irq-bcm6345-ext.h
  363. @@ -0,0 +1,14 @@
  364. +/*
  365. + * This file is subject to the terms and conditions of the GNU General Public
  366. + * License. See the file "COPYING" in the main directory of this archive
  367. + * for more details.
  368. + *
  369. + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
  370. + */
  371. +
  372. +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
  373. +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
  374. +
  375. +void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
  376. +
  377. +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */