EASY80920.dtsi 6.8 KB

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  1. /include/ "vr9.dtsi"
  2. / {
  3. chosen {
  4. bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
  5. };
  6. memory@0 {
  7. reg = <0x0 0x4000000>;
  8. };
  9. fpi@10000000 {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. compatible = "lantiq,fpi", "simple-bus";
  13. ranges = <0x0 0x10000000 0xEEFFFFF>;
  14. reg = <0x10000000 0xEF00000>;
  15. localbus@0 {
  16. #address-cells = <2>;
  17. #size-cells = <1>;
  18. compatible = "lantiq,localbus", "simple-bus";
  19. };
  20. spi@E100800 {
  21. compatible = "lantiq,spi-xway-broken";
  22. reg = <0xE100800 0x100>;
  23. interrupt-parent = <&icu0>;
  24. interrupts = <22 23 24>;
  25. #address-cells = <1>;
  26. #size-cells = <1>;
  27. m25p80@0 {
  28. #address-cells = <1>;
  29. #size-cells = <1>;
  30. compatible = "s25fl129p0";
  31. reg = <0 0>;
  32. linux,modalias = "m25p80", "mx25l3205d";
  33. spi-max-frequency = <1000000>;
  34. partition@0 {
  35. reg = <0x0 0x20000>;
  36. label = "SPI (RO) U-Boot Image";
  37. read-only;
  38. };
  39. partition@20000 {
  40. reg = <0x20000 0x10000>;
  41. label = "ENV_MAC";
  42. read-only;
  43. };
  44. partition@30000 {
  45. reg = <0x30000 0x10000>;
  46. label = "DPF";
  47. read-only;
  48. };
  49. partition@40000 {
  50. reg = <0x40000 0x10000>;
  51. label = "NVRAM";
  52. read-only;
  53. };
  54. partition@500000 {
  55. reg = <0x50000 0x003a0000>;
  56. label = "kernel";
  57. };
  58. };
  59. };
  60. gpio: pinmux@E100B10 {
  61. compatible = "lantiq,pinctrl-xr9";
  62. pinctrl-names = "default";
  63. pinctrl-0 = <&state_default>;
  64. interrupt-parent = <&icu0>;
  65. interrupts = <166 135 66 40 41 42 38>;
  66. #gpio-cells = <2>;
  67. gpio-controller;
  68. reg = <0xE100B10 0xA0>;
  69. state_default: pinmux {
  70. exin3 {
  71. lantiq,groups = "exin3";
  72. lantiq,function = "exin";
  73. };
  74. stp {
  75. lantiq,groups = "stp";
  76. lantiq,function = "stp";
  77. };
  78. spi {
  79. lantiq,groups = "spi", "spi_cs4";
  80. lantiq,function = "spi";
  81. };
  82. nand {
  83. lantiq,groups = "nand cle", "nand ale",
  84. "nand rd", "nand rdy";
  85. lantiq,function = "ebu";
  86. };
  87. mdio {
  88. lantiq,groups = "mdio";
  89. lantiq,function = "mdio";
  90. };
  91. pci {
  92. lantiq,groups = "gnt1", "req1";
  93. lantiq,function = "pci";
  94. };
  95. conf_out {
  96. lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
  97. "io4", "io5", "io6", /* stp */
  98. "io21",
  99. "io33";
  100. lantiq,open-drain;
  101. lantiq,pull = <0>;
  102. lantiq,output = <1>;
  103. };
  104. pcie-rst {
  105. lantiq,pins = "io38";
  106. lantiq,pull = <0>;
  107. lantiq,output = <1>;
  108. };
  109. conf_in {
  110. lantiq,pins = "io39", /* exin3 */
  111. "io48"; /* nand rdy */
  112. lantiq,pull = <2>;
  113. };
  114. };
  115. };
  116. eth@E108000 {
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. compatible = "lantiq,xrx200-net";
  120. reg = < 0xE108000 0x3000 /* switch */
  121. 0xE10B100 0x70 /* mdio */
  122. 0xE10B1D8 0x30 /* mii */
  123. 0xE10B308 0x30 /* pmac */
  124. >;
  125. interrupt-parent = <&icu0>;
  126. interrupts = <73 72>;
  127. lan: interface@0 {
  128. compatible = "lantiq,xrx200-pdi";
  129. #address-cells = <1>;
  130. #size-cells = <0>;
  131. reg = <0>;
  132. mac-address = [ 00 11 22 33 44 55 ];
  133. ethernet@0 {
  134. compatible = "lantiq,xrx200-pdi-port";
  135. reg = <0>;
  136. phy-mode = "rgmii";
  137. phy-handle = <&phy0>;
  138. };
  139. ethernet@1 {
  140. compatible = "lantiq,xrx200-pdi-port";
  141. reg = <1>;
  142. phy-mode = "rgmii";
  143. phy-handle = <&phy1>;
  144. };
  145. ethernet@2 {
  146. compatible = "lantiq,xrx200-pdi-port";
  147. reg = <2>;
  148. phy-mode = "gmii";
  149. phy-handle = <&phy11>;
  150. };
  151. };
  152. wan: interface@1 {
  153. compatible = "lantiq,xrx200-pdi";
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. reg = <1>;
  157. mac-address = [ 00 11 22 33 44 56 ];
  158. lantiq,wan;
  159. ethernet@5 {
  160. compatible = "lantiq,xrx200-pdi-port";
  161. reg = <5>;
  162. phy-mode = "rgmii";
  163. phy-handle = <&phy5>;
  164. };
  165. };
  166. test: interface@2 {
  167. compatible = "lantiq,xrx200-pdi";
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. reg = <2>;
  171. mac-address = [ 00 11 22 33 44 57 ];
  172. ethernet@4 {
  173. compatible = "lantiq,xrx200-pdi-port";
  174. reg = <4>;
  175. phynmode0 = "gmii";
  176. phy-handle = <&phy13>;
  177. };
  178. };
  179. mdio@0 {
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. compatible = "lantiq,xrx200-mdio";
  183. phy0: ethernet-phy@0 {
  184. reg = <0x0>;
  185. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  186. };
  187. phy1: ethernet-phy@1 {
  188. reg = <0x1>;
  189. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  190. };
  191. phy5: ethernet-phy@5 {
  192. reg = <0x5>;
  193. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  194. };
  195. phy11: ethernet-phy@11 {
  196. reg = <0x11>;
  197. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  198. };
  199. phy13: ethernet-phy@13 {
  200. reg = <0x13>;
  201. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  202. };
  203. };
  204. };
  205. stp: stp@E100BB0 {
  206. compatible = "lantiq,gpio-stp-xway";
  207. reg = <0xE100BB0 0x40>;
  208. #gpio-cells = <2>;
  209. gpio-controller;
  210. lantiq,shadow = <0xffff>;
  211. lantiq,groups = <0x7>;
  212. lantiq,dsl = <0x3>;
  213. lantiq,phy1 = <0x7>;
  214. lantiq,phy2 = <0x7>;
  215. /* lantiq,rising; */
  216. };
  217. ifxhcd@E101000 {
  218. status = "okay";
  219. gpios = <&gpio 33 0>;
  220. lantiq,portmask = <0x3>;
  221. };
  222. pci@E105400 {
  223. #address-cells = <3>;
  224. #size-cells = <2>;
  225. #interrupt-cells = <1>;
  226. compatible = "lantiq,pci-xway1";
  227. bus-range = <0x0 0x0>;
  228. ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
  229. 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
  230. reg = <0x7000000 0x8000 /* config space */
  231. 0xE105400 0x400>; /* pci bridge */
  232. lantiq,bus-clock = <33333333>;
  233. /*lantiq,external-clock;*/
  234. lantiq,delay-hi = <0>; /* 0ns delay */
  235. lantiq,delay-lo = <0>; /* 0.0ns delay */
  236. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  237. interrupt-map = <
  238. 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
  239. >;
  240. gpios-reset = <&gpio 21 0>;
  241. req-mask = <0x1>; /* GNT1 */
  242. };
  243. };
  244. gphy-xrx200 {
  245. compatible = "lantiq,phy-xrx200";
  246. firmware = "lantiq/vr9_phy11g_a2x.bin";
  247. phys = [ 00 01 ];
  248. };
  249. gpio-keys-polled {
  250. compatible = "gpio-keys-polled";
  251. #address-cells = <1>;
  252. #size-cells = <0>;
  253. poll-interval = <100>;
  254. /* reset {
  255. label = "reset";
  256. gpios = <&gpio 7 1>;
  257. linux,code = <0x198>;
  258. };*/
  259. paging {
  260. label = "paging";
  261. gpios = <&gpio 11 1>;
  262. linux,code = <0x100>;
  263. };
  264. };
  265. gpio-leds {
  266. compatible = "gpio-leds";
  267. power {
  268. label = "power";
  269. gpios = <&stp 9 0>;
  270. default-state = "on";
  271. };
  272. warning {
  273. label = "warning";
  274. gpios = <&stp 22 0>;
  275. };
  276. fxs1 {
  277. label = "fxs1";
  278. gpios = <&stp 21 0>;
  279. };
  280. fxs2 {
  281. label = "fxs2";
  282. gpios = <&stp 20 0>;
  283. };
  284. fxo {
  285. label = "fxo";
  286. gpios = <&stp 19 0>;
  287. };
  288. usb1 {
  289. label = "usb1";
  290. gpios = <&stp 18 0>;
  291. };
  292. usb2 {
  293. label = "usb2";
  294. gpios = <&stp 15 0>;
  295. };
  296. sd {
  297. label = "sd";
  298. gpios = <&stp 14 0>;
  299. };
  300. wps {
  301. label = "wps";
  302. gpios = <&stp 12 0>;
  303. };
  304. };
  305. };