025-ARM-mvebu-Use-arm_coherent_dma_ops.patch 3.4 KB

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  1. From 1bd4d8a6de5cda605e8b99fbf081be2ea2959380 Mon Sep 17 00:00:00 2001
  2. From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  3. Date: Fri, 16 Jan 2015 17:11:29 +0100
  4. Subject: ARM: mvebu: use arm_coherent_dma_ops and re-enable hardware I/O
  5. coherency
  6. Now that we have enabled automatic I/O synchronization barriers, we no
  7. longer need any explicit barriers. We can therefore simplify
  8. arch/arm/mach-mvebu/coherency.c by using the existing
  9. arm_coherent_dma_ops instead of our custom mvebu_hwcc_dma_ops, and
  10. re-enable hardware I/O coherency support.
  11. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  12. [Andrew Lunn <andrew@lunn.ch>: Remove forgotten comment]
  13. Signed-off-by: Andrew Lunn <andrew@lunn.ch>
  14. --- a/arch/arm/mach-mvebu/coherency.c
  15. +++ b/arch/arm/mach-mvebu/coherency.c
  16. @@ -33,6 +33,7 @@
  17. #include <asm/smp_plat.h>
  18. #include <asm/cacheflush.h>
  19. #include <asm/mach/map.h>
  20. +#include <asm/dma-mapping.h>
  21. #include "armada-370-xp.h"
  22. #include "coherency.h"
  23. #include "mvebu-soc-id.h"
  24. @@ -223,59 +224,6 @@ static void __init armada_375_coherency_
  25. coherency_wa_enabled = true;
  26. }
  27. -static inline void mvebu_hwcc_sync_io_barrier(void)
  28. -{
  29. - if (coherency_wa_enabled) {
  30. - mvebu_hwcc_armada375_sync_io_barrier_wa();
  31. - return;
  32. - }
  33. -
  34. - writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
  35. - while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
  36. -}
  37. -
  38. -static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
  39. - unsigned long offset, size_t size,
  40. - enum dma_data_direction dir,
  41. - struct dma_attrs *attrs)
  42. -{
  43. - if (dir != DMA_TO_DEVICE)
  44. - mvebu_hwcc_sync_io_barrier();
  45. - return pfn_to_dma(dev, page_to_pfn(page)) + offset;
  46. -}
  47. -
  48. -
  49. -static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
  50. - size_t size, enum dma_data_direction dir,
  51. - struct dma_attrs *attrs)
  52. -{
  53. - if (dir != DMA_TO_DEVICE)
  54. - mvebu_hwcc_sync_io_barrier();
  55. -}
  56. -
  57. -static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
  58. - size_t size, enum dma_data_direction dir)
  59. -{
  60. - if (dir != DMA_TO_DEVICE)
  61. - mvebu_hwcc_sync_io_barrier();
  62. -}
  63. -
  64. -static struct dma_map_ops mvebu_hwcc_dma_ops = {
  65. - .alloc = arm_dma_alloc,
  66. - .free = arm_dma_free,
  67. - .mmap = arm_dma_mmap,
  68. - .map_page = mvebu_hwcc_dma_map_page,
  69. - .unmap_page = mvebu_hwcc_dma_unmap_page,
  70. - .get_sgtable = arm_dma_get_sgtable,
  71. - .map_sg = arm_dma_map_sg,
  72. - .unmap_sg = arm_dma_unmap_sg,
  73. - .sync_single_for_cpu = mvebu_hwcc_dma_sync,
  74. - .sync_single_for_device = mvebu_hwcc_dma_sync,
  75. - .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
  76. - .sync_sg_for_device = arm_dma_sync_sg_for_device,
  77. - .set_dma_mask = arm_dma_set_mask,
  78. -};
  79. -
  80. static int mvebu_hwcc_notifier(struct notifier_block *nb,
  81. unsigned long event, void *__dev)
  82. {
  83. @@ -283,7 +231,7 @@ static int mvebu_hwcc_notifier(struct no
  84. if (event != BUS_NOTIFY_ADD_DEVICE)
  85. return NOTIFY_DONE;
  86. - set_dma_ops(dev, &mvebu_hwcc_dma_ops);
  87. + set_dma_ops(dev, &arm_coherent_dma_ops);
  88. return NOTIFY_OK;
  89. }
  90. @@ -399,14 +347,9 @@ static int coherency_type(void)
  91. return type;
  92. }
  93. -/*
  94. - * As a precaution, we currently completely disable hardware I/O
  95. - * coherency, until enough testing is done with automatic I/O
  96. - * synchronization barriers to validate that it is a proper solution.
  97. - */
  98. int coherency_available(void)
  99. {
  100. - return false;
  101. + return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
  102. }
  103. int __init coherency_init(void)