606-MIPS-ath79-pb44-fixes.patch 3.9 KB

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  1. --- a/arch/mips/ath79/mach-pb44.c
  2. +++ b/arch/mips/ath79/mach-pb44.c
  3. @@ -8,23 +8,48 @@
  4. * by the Free Software Foundation.
  5. */
  6. +#include <linux/delay.h>
  7. #include <linux/init.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/i2c.h>
  10. #include <linux/i2c-gpio.h>
  11. #include <linux/i2c/pcf857x.h>
  12. +#include <linux/i2c/pcf857x.h>
  13. +#include <linux/spi/flash.h>
  14. +#include <linux/spi/vsc7385.h>
  15. -#include "machtypes.h"
  16. +#include <asm/mach-ath79/ar71xx_regs.h>
  17. +#include <asm/mach-ath79/ath79.h>
  18. +
  19. +#include "dev-eth.h"
  20. #include "dev-gpio-buttons.h"
  21. #include "dev-leds-gpio.h"
  22. #include "dev-spi.h"
  23. #include "dev-usb.h"
  24. +#include "machtypes.h"
  25. #include "pci.h"
  26. #define PB44_GPIO_I2C_SCL 0
  27. #define PB44_GPIO_I2C_SDA 1
  28. +#define PB44_PCF8757_VSC7395_CS 0
  29. +#define PB44_PCF8757_STEREO_CS 1
  30. +#define PB44_PCF8757_SLIC_CS0 2
  31. +#define PB44_PCF8757_SLIC_TEST 3
  32. +#define PB44_PCF8757_SLIC_INT0 4
  33. +#define PB44_PCF8757_SLIC_INT1 5
  34. +#define PB44_PCF8757_SW_RESET 6
  35. +#define PB44_PCF8757_SW_JUMP 8
  36. +#define PB44_PCF8757_LED_JUMP1 9
  37. +#define PB44_PCF8757_LED_JUMP2 10
  38. +#define PB44_PCF8757_TP24 11
  39. +#define PB44_PCF8757_TP25 12
  40. +#define PB44_PCF8757_TP26 13
  41. +#define PB44_PCF8757_TP27 14
  42. +#define PB44_PCF8757_TP28 15
  43. +
  44. #define PB44_GPIO_EXP_BASE 16
  45. +#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS)
  46. #define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + 6)
  47. #define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + 8)
  48. #define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + 9)
  49. @@ -92,21 +117,66 @@ static struct ath79_spi_controller_data
  50. .cs_line = 0,
  51. };
  52. +static struct ath79_spi_controller_data pb44_spi1_data = {
  53. + .cs_type = ATH79_SPI_CS_TYPE_GPIO,
  54. + .cs_line = PB44_GPIO_VSC7395_CS,
  55. +};
  56. +
  57. +static void pb44_vsc7395_reset(void)
  58. +{
  59. + ath79_device_reset_set(AR71XX_RESET_GE1_PHY);
  60. + udelay(10);
  61. + ath79_device_reset_clear(AR71XX_RESET_GE1_PHY);
  62. + mdelay(50);
  63. +}
  64. +
  65. +static struct vsc7385_platform_data pb44_vsc7395_data = {
  66. + .reset = pb44_vsc7395_reset,
  67. + .ucode_name = "vsc7395_ucode_pb44.bin",
  68. + .mac_cfg = {
  69. + .tx_ipg = 6,
  70. + .bit2 = 1,
  71. + .clk_sel = 0,
  72. + },
  73. +};
  74. +
  75. +static const char *pb44_part_probes[] = {
  76. + "RedBoot",
  77. + NULL,
  78. +};
  79. +
  80. +static struct flash_platform_data pb44_flash_data = {
  81. + .part_probes = pb44_part_probes,
  82. +};
  83. +
  84. static struct spi_board_info pb44_spi_info[] = {
  85. {
  86. .bus_num = 0,
  87. .chip_select = 0,
  88. .max_speed_hz = 25000000,
  89. .modalias = "m25p64",
  90. + .platform_data = &pb44_flash_data,
  91. .controller_data = &pb44_spi0_data,
  92. },
  93. + {
  94. + .bus_num = 0,
  95. + .chip_select = 1,
  96. + .max_speed_hz = 25000000,
  97. + .modalias = "spi-vsc7385",
  98. + .platform_data = &pb44_vsc7395_data,
  99. + .controller_data = &pb44_spi1_data,
  100. + }
  101. };
  102. static struct ath79_spi_platform_data pb44_spi_data = {
  103. .bus_num = 0,
  104. - .num_chipselect = 1,
  105. + .num_chipselect = 2,
  106. };
  107. +#define PB44_WAN_PHYMASK BIT(0)
  108. +#define PB44_LAN_PHYMASK 0
  109. +#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK)
  110. +
  111. static void __init pb44_init(void)
  112. {
  113. i2c_register_board_info(0, pb44_i2c_board_info,
  114. @@ -122,6 +192,22 @@ static void __init pb44_init(void)
  115. ARRAY_SIZE(pb44_spi_info));
  116. ath79_register_usb();
  117. ath79_register_pci();
  118. +
  119. + ath79_register_mdio(0, ~PB44_MDIO_PHYMASK);
  120. +
  121. + ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  122. + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  123. + ath79_eth0_data.phy_mask = PB44_WAN_PHYMASK;
  124. +
  125. + ath79_register_eth(0);
  126. +
  127. + ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
  128. + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  129. + ath79_eth1_data.speed = SPEED_1000;
  130. + ath79_eth1_data.duplex = DUPLEX_FULL;
  131. + ath79_eth1_pll_data.pll_1000 = 0x110000;
  132. +
  133. + ath79_register_eth(1);
  134. }
  135. MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
  136. --- a/arch/mips/ath79/Kconfig
  137. +++ b/arch/mips/ath79/Kconfig
  138. @@ -58,6 +58,7 @@ config ATH79_MACH_DB120
  139. config ATH79_MACH_PB44
  140. bool "Atheros PB44 reference board"
  141. select SOC_AR71XX
  142. + select ATH79_DEV_ETH
  143. select ATH79_DEV_GPIO_BUTTONS
  144. select ATH79_DEV_LEDS_GPIO
  145. select ATH79_DEV_SPI