0045-dwc_otg-Fix-various-issues-with-root-port-and-transa.patch 2.8 KB

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  1. From 8eb79690a70cce34e9a1c35cf165716f78301d2e Mon Sep 17 00:00:00 2001
  2. From: P33M <P33M@github.com>
  3. Date: Fri, 20 Jun 2014 16:03:12 +0100
  4. Subject: [PATCH 045/114] dwc_otg: Fix various issues with root port and
  5. transaction errors
  6. Process the host port interrupts correctly (and don't trample them).
  7. Root port hotplug now functional again.
  8. Fix a few thinkos with the transaction error passthrough for fiq_fsm.
  9. ---
  10. drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 7 +++----
  11. drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 6 +++++-
  12. drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2 +-
  13. 3 files changed, 9 insertions(+), 6 deletions(-)
  14. --- a/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
  15. +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
  16. @@ -1348,10 +1348,9 @@ static inline uint32_t dwc_otg_read_comm
  17. local_fiq_disable();
  18. /* Pull in the interrupts that the FIQ has masked */
  19. gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
  20. + gintmsk.d32 |= gintmsk_common.d32;
  21. /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
  22. - reenable_gintmsk->d32 |= gintmsk.d32;
  23. - reenable_gintmsk->d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
  24. - reenable_gintmsk->d32 &= gintmsk_common.d32;
  25. + reenable_gintmsk->d32 = gintmsk.d32;
  26. local_fiq_enable();
  27. }
  28. @@ -1535,7 +1534,7 @@ int32_t dwc_otg_handle_common_intr(void
  29. // fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
  30. // fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
  31. // fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
  32. - if (retval) {
  33. + if (retval && fiq_enable) {
  34. DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
  35. }
  36. --- a/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  37. +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
  38. @@ -696,7 +696,11 @@ static int notrace noinline fiq_fsm_do_h
  39. fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
  40. if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
  41. fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
  42. - st->nr_errors = 0;
  43. + /* In some random cases we can get a NAK interrupt coincident with a Xacterr
  44. + * interrupt, after the device has disappeared.
  45. + */
  46. + if (!hcint.b.xacterr)
  47. + st->nr_errors = 0;
  48. hcintmsk.b.nak = 0;
  49. hcintmsk.b.ack = 0;
  50. hcintmsk.b.datatglerr = 0;
  51. --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  52. +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  53. @@ -2619,7 +2619,7 @@ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc
  54. case FIQ_PASSTHROUGH_ERRORSTATE:
  55. /* Hook into the error count */
  56. fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
  57. - if (dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
  58. + if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
  59. qtd->error_count = 0;
  60. fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET ");
  61. }