0105-dwc_otg-fixup-read-modify-write-in-critical-paths.patch 4.5 KB

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  1. From a05cd269cbf2623efe2499459efdd123ee04ab81 Mon Sep 17 00:00:00 2001
  2. From: P33M <P33M@github.com>
  3. Date: Wed, 4 Feb 2015 12:16:50 +0000
  4. Subject: [PATCH 105/114] dwc_otg: fixup read-modify-write in critical paths
  5. Be more careful about read-modify-write on registers that the FIQ
  6. also touches.
  7. ---
  8. drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 13 +++++++++---
  9. drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 30 +++++++++++++++++++++++++---
  10. drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 22 ++++++++++++++++----
  11. 3 files changed, 55 insertions(+), 10 deletions(-)
  12. --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
  13. +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
  14. @@ -2447,9 +2447,16 @@ void dwc_otg_hcd_queue_transactions(dwc_
  15. */
  16. gintmsk_data_t gintmsk = {.d32 = 0 };
  17. gintmsk.b.nptxfempty = 1;
  18. - DWC_MODIFY_REG32(&hcd->core_if->
  19. - core_global_regs->gintmsk, gintmsk.d32,
  20. - 0);
  21. +
  22. + if (fiq_enable) {
  23. + local_fiq_disable();
  24. + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  25. + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
  26. + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  27. + local_fiq_enable();
  28. + } else {
  29. + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
  30. + }
  31. }
  32. }
  33. }
  34. --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  35. +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  36. @@ -165,7 +165,15 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_
  37. gintmsk_data_t gintmsk = { .b.portintr = 1};
  38. retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
  39. - DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
  40. + if (fiq_enable) {
  41. + local_fiq_disable();
  42. + fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
  43. + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
  44. + fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
  45. + local_fiq_enable();
  46. + } else {
  47. + DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
  48. + }
  49. }
  50. if (gintsts.b.hcintr) {
  51. retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
  52. @@ -1069,7 +1077,15 @@ static void halt_channel(dwc_otg_hcd_t *
  53. * be processed.
  54. */
  55. gintmsk.b.nptxfempty = 1;
  56. - DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  57. + if (fiq_enable) {
  58. + local_fiq_disable();
  59. + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  60. + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  61. + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  62. + local_fiq_enable();
  63. + } else {
  64. + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  65. + }
  66. } else {
  67. /*
  68. * Move the QH from the periodic queued schedule to
  69. @@ -1086,7 +1102,15 @@ static void halt_channel(dwc_otg_hcd_t *
  70. * processed.
  71. */
  72. gintmsk.b.ptxfempty = 1;
  73. - DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  74. + if (fiq_enable) {
  75. + local_fiq_disable();
  76. + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  77. + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  78. + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  79. + local_fiq_enable();
  80. + } else {
  81. + DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  82. + }
  83. }
  84. }
  85. }
  86. --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
  87. +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
  88. @@ -683,8 +683,15 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * h
  89. status = schedule_periodic(hcd, qh);
  90. if ( !hcd->periodic_qh_count ) {
  91. intr_mask.b.sofintr = 1;
  92. - DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
  93. - intr_mask.d32, intr_mask.d32);
  94. + if (fiq_enable) {
  95. + local_fiq_disable();
  96. + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  97. + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
  98. + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  99. + local_fiq_enable();
  100. + } else {
  101. + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
  102. + }
  103. }
  104. hcd->periodic_qh_count++;
  105. }
  106. @@ -745,8 +752,15 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t
  107. hcd->periodic_qh_count--;
  108. if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
  109. intr_mask.b.sofintr = 1;
  110. - DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
  111. - intr_mask.d32, 0);
  112. + if (fiq_enable) {
  113. + local_fiq_disable();
  114. + fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  115. + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
  116. + fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  117. + local_fiq_enable();
  118. + } else {
  119. + DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
  120. + }
  121. }
  122. }
  123. }