bcm6318.dtsi 1.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778
  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm6318";
  5. aliases {
  6. gpio0 = &gpio0;
  7. gpio1 = &gpio1;
  8. };
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. cpu@0 {
  13. compatible = "brcm,bmips3300", "mips,mips4Kc";
  14. device_type = "cpu";
  15. reg = <0>;
  16. };
  17. };
  18. cpu_intc: interrupt-controller {
  19. #address-cells = <0>;
  20. compatible = "mti,cpu-interrupt-controller";
  21. interrupt-controller;
  22. #interrupt-cells = <1>;
  23. };
  24. memory { device_type = "memory"; reg = <0 0>; };
  25. ubus@10000000 {
  26. #address-cells = <1>;
  27. #size-cells = <1>;
  28. ranges;
  29. compatible = "simple-bus";
  30. ext_intc: interrupt-controller@10000018 {
  31. compatible = "brcm,bcm6345-ext-intc";
  32. reg = <0x10000018 0x4>;
  33. interrupt-controller;
  34. #interrupt-cells = <2>;
  35. interrupt-parent = <&periph_intc>;
  36. interrupts = <24>, <25>, <26>, <27>;
  37. };
  38. periph_intc: interrupt-controller@10000020 {
  39. compatible = "brcm,bcm6345-periph-intc";
  40. reg = <0x10000020 0x20>;
  41. interrupt-controller;
  42. #interrupt-cells = <1>;
  43. interrupt-parent = <&cpu_intc>;
  44. interrupts = <2>;
  45. };
  46. gpio1: gpio-controller@10000080 {
  47. compatible = "brcm,bcm6345-gpio";
  48. reg = <0x10000080 4>, <0x10000088 4>;
  49. gpio-controller;
  50. #gpio-cells = <2>;
  51. ngpios = <18>;
  52. };
  53. gpio0: gpio-controller@10000084 {
  54. compatible = "brcm,bcm6345-gpio";
  55. reg = <0x10000084 4>, <0x1000008c 4>;
  56. gpio-controller;
  57. #gpio-cells = <2>;
  58. };
  59. };
  60. };