bcm6338.dtsi 1.4 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm6338";
  5. aliases {
  6. pflash = &pflash;
  7. gpio0 = &gpio0;
  8. };
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. cpu@0 {
  13. compatible = "brcm,bmips3300", "mips,mips4Kc";
  14. device_type = "cpu";
  15. reg = <0>;
  16. };
  17. };
  18. cpu_intc: interrupt-controller {
  19. #address-cells = <0>;
  20. compatible = "mti,cpu-interrupt-controller";
  21. interrupt-controller;
  22. #interrupt-cells = <1>;
  23. };
  24. memory { device_type = "memory"; reg = <0 0>; };
  25. pflash: nor@1fc00000 {
  26. compatible = "cfi-flash";
  27. reg = <0x1fc00000 0x400000>;
  28. bank-width = <2>;
  29. #address-cells = <1>;
  30. #size-cells = <1>;
  31. status = "disabled";
  32. };
  33. ubus@fff00000 {
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. ranges;
  37. compatible = "simple-bus";
  38. periph_intc: interrupt-controller@fffe000c {
  39. compatible = "brcm,bcm6345-periph-intc";
  40. reg = <0xfffe000c 0x8>;
  41. interrupt-controller;
  42. #interrupt-cells = <1>;
  43. interrupt-parent = <&cpu_intc>;
  44. interrupts = <2>;
  45. };
  46. ext_intc: interrupt-controller@fffe0014 {
  47. compatible = "brcm,bcm6345-ext-intc";
  48. reg = <0xfffe0014 0x4>;
  49. interrupt-controller;
  50. #interrupt-cells = <2>;
  51. interrupt-parent = <&cpu_intc>;
  52. interrupts = <3>, <4>, <5>, <6>;
  53. };
  54. gpio0: gpio-controller@fffe0404 {
  55. compatible = "brcm,bcm6345-gpio";
  56. reg = <0xfffe0404 4>, <0xfffe040c 4>;
  57. gpio-controller;
  58. #gpio-cells = <2>;
  59. ngpios = <8>;
  60. };
  61. };
  62. };