bcm6348.dtsi 1.6 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm6348";
  5. aliases {
  6. pflash = &pflash;
  7. gpio0 = &gpio0;
  8. gpio1 = &gpio1;
  9. };
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu@0 {
  14. compatible = "brcm,bmips3300", "mips,mips4Kc";
  15. device_type = "cpu";
  16. reg = <0>;
  17. };
  18. };
  19. cpu_intc: interrupt-controller {
  20. #address-cells = <0>;
  21. compatible = "mti,cpu-interrupt-controller";
  22. interrupt-controller;
  23. #interrupt-cells = <1>;
  24. };
  25. memory { device_type = "memory"; reg = <0 0>; };
  26. pflash: nor@1fc00000 {
  27. compatible = "cfi-flash";
  28. reg = <0x1fc00000 0x400000>;
  29. bank-width = <2>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. status = "disabled";
  33. };
  34. ubus@fff00000 {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. ranges;
  38. compatible = "simple-bus";
  39. periph_intc: interrupt-controller@fffe000c {
  40. compatible = "brcm,bcm6345-periph-intc";
  41. reg = <0xfffe000c 0x8>;
  42. interrupt-controller;
  43. #interrupt-cells = <1>;
  44. interrupt-parent = <&cpu_intc>;
  45. interrupts = <2>;
  46. };
  47. ext_intc: interrupt-controller@fffe0014 {
  48. compatible = "brcm,bcm6345-ext-intc";
  49. reg = <0xfffe0014 0x4>;
  50. interrupt-controller;
  51. #interrupt-cells = <2>;
  52. interrupt-parent = <&cpu_intc>;
  53. interrupts = <3>, <4>, <5>, <6>;
  54. brcm,field-width = <5>;
  55. };
  56. gpio1: gpio-controller@fffe0400 {
  57. compatible = "brcm,bcm6345-gpio";
  58. reg = <0xfffe0400 4>, <0xfffe0408 4>;
  59. gpio-controller;
  60. #gpio-cells = <2>;
  61. ngpios = <5>;
  62. };
  63. gpio0: gpio-controller@fffe0404 {
  64. compatible = "brcm,bcm6345-gpio";
  65. reg = <0xfffe0404 4>, <0xfffe040c 4>;
  66. gpio-controller;
  67. #gpio-cells = <2>;
  68. };
  69. };
  70. };