207-ARM-dts-imx6-ventana-Add-PCI-nodes-for-on-board-PCI-.patch 2.9 KB

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  1. From 840202d23892baaff74be11ec71c3ffc6ad6298e Mon Sep 17 00:00:00 2001
  2. From: Tim Harvey <tharvey@gateworks.com>
  3. Date: Tue, 20 Jan 2015 08:46:55 -0800
  4. Subject: [PATCH] ARM: dts: imx6 ventana: Add PCI nodes for on-board PCI
  5. devices
  6. If the PCI nodes are defined, drivers can access information from the DT.
  7. For example, the sky2 enet driver can obtain the mac address configured
  8. from the bootloader (which is applied to the DT node with the ethernet1 alias).
  9. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  10. ---
  11. arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 38 +++++++++++++++++++++++++++++++++--
  12. arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 38 +++++++++++++++++++++++++++++++++--
  13. 2 files changed, 72 insertions(+), 4 deletions(-)
  14. --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
  15. +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
  16. @@ -280,8 +280,42 @@
  17. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  18. status = "okay";
  19. - eth1: sky2@8 { /* MAC/PHY on bus 8 */
  20. - compatible = "marvell,sky2";
  21. + pcie@0,0 {
  22. + /* 00:00.0 0604: 16c3:abcd root host-bridge */
  23. + #address-cells = <3>;
  24. + #size-cells = <2>;
  25. + device_type = "pci";
  26. + reg = <0x0 0 0 0 0>;
  27. +
  28. + pcie@0,0 {
  29. + /* 01:00.0 0604: 10b5:8609 PEX switch bridge */
  30. + #address-cells = <3>;
  31. + #size-cells = <2>;
  32. + device_type = "pci";
  33. + reg = <0x0 0 0 0 0>;
  34. +
  35. + /*
  36. + * GigE PCI dev node needs to be defined so that enet
  37. + * driver can use it to obtain its boot-loader
  38. + * specified MAC
  39. + */
  40. + pcie@4,0 {
  41. + /* 02:04.0 0604: 10b5:8609: PEX port bridge */
  42. + #address-cells = <3>;
  43. + #size-cells = <2>;
  44. + device_type = "pci";
  45. + reg = <0x2000 0 0 0 0>;
  46. +
  47. + eth1: pci@0,0 {
  48. + /* 04:00.0 0200: 11ab:4380: GigE */
  49. + #address-cells = <3>;
  50. + #size-cells = <2>;
  51. + device_type = "pci";
  52. + reg = <0x0 0 0 0 0>;
  53. + compatible = "marvell,sky2";
  54. + };
  55. + };
  56. + };
  57. };
  58. };
  59. --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
  60. +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
  61. @@ -369,8 +369,42 @@
  62. reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
  63. status = "okay";
  64. - eth1: sky2@8 { /* MAC/PHY on bus 8 */
  65. - compatible = "marvell,sky2";
  66. + pcie@0,0 {
  67. + /* 00:00.0 0604: 16c3:abcd root host-bridge */
  68. + #address-cells = <3>;
  69. + #size-cells = <2>;
  70. + device_type = "pci";
  71. + reg = <0x0 0 0 0 0>;
  72. +
  73. + pcie@0,0 {
  74. + /* 01:00.0 0604: 10b5:8609 PEX switch bridge */
  75. + #address-cells = <3>;
  76. + #size-cells = <2>;
  77. + device_type = "pci";
  78. + reg = <0x0 0 0 0 0>;
  79. +
  80. + /*
  81. + * GigE PCI dev node needs to be defined so that enet
  82. + * driver can use it to obtain its boot-loader
  83. + * specified MAC
  84. + */
  85. + pcie@8,0 {
  86. + /* 02:08.0 0604: 10b5:8609: PEX port bridge */
  87. + #address-cells = <3>;
  88. + #size-cells = <2>;
  89. + device_type = "pci";
  90. + reg = <0x4000 0 0 0 0>;
  91. +
  92. + eth1: pci@0,0 {
  93. + /* 08:00.0 0200: 11ab:4380: GigE */
  94. + #address-cells = <3>;
  95. + #size-cells = <2>;
  96. + device_type = "pci";
  97. + reg = <0x0 0 0 0 0>;
  98. + compatible = "marvell,sky2";
  99. + };
  100. + };
  101. + };
  102. };
  103. };