653-0030-rtl8xxxu-Initialize-GPIO-settings-for-8188eu.patch 1.4 KB

12345678910111213141516171819202122232425262728293031323334353637383940
  1. From 061838d68d2c20acb5a57fbd92e3ed0ae906142e Mon Sep 17 00:00:00 2001
  2. From: Jes Sorensen <Jes.Sorensen@redhat.com>
  3. Date: Fri, 22 Jul 2016 12:56:30 -0400
  4. Subject: [PATCH] rtl8xxxu: Initialize GPIO settings for 8188eu
  5. This matches what the vendor driver does, but is actually opposite of
  6. what it does for 8192eu.
  7. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
  8. ---
  9. drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 7 +++++++
  10. drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 1 +
  11. 2 files changed, 8 insertions(+)
  12. --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
  13. +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c
  14. @@ -4210,6 +4210,13 @@ static int rtl8xxxu_init_device(struct i
  15. * Reset USB mode switch setting
  16. */
  17. rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
  18. + } else if (priv->rtl_chip == RTL8188E) {
  19. + /*
  20. + * Init GPIO settings for 8188e
  21. + */
  22. + val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
  23. + val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
  24. + rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
  25. }
  26. rtl8723a_phy_lc_calibrate(priv);
  27. --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  28. +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  29. @@ -143,6 +143,7 @@
  30. #define REG_CAL_TIMER 0x003c
  31. #define REG_ACLK_MON 0x003e
  32. #define REG_GPIO_MUXCFG 0x0040
  33. +#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5)
  34. #define REG_GPIO_IO_SEL 0x0042
  35. #define REG_MAC_PINMUX_CFG 0x0043
  36. #define REG_GPIO_PIN_CTRL 0x0044