046-0006-ARM-BCM53573-Specify-USB-ports-of-on-SoC-controllers.patch 1.4 KB

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  1. From 92c6f000cb3a4280166d812d88cda3011717b548 Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
  3. Date: Wed, 7 Dec 2016 08:56:55 +0100
  4. Subject: [PATCH 6/6] ARM: BCM53573: Specify USB ports of on-SoC controllers
  5. MIME-Version: 1.0
  6. Content-Type: text/plain; charset=UTF-8
  7. Content-Transfer-Encoding: 8bit
  8. Broadcom OHCI and EHCI controllers always have 2 ports each on the root
  9. hub. Describe them in DT to allow specifying extra info or referencing
  10. port nodes.
  11. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  12. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  13. ---
  14. arch/arm/boot/dts/bcm53573.dtsi | 22 ++++++++++++++++++++++
  15. 1 file changed, 22 insertions(+)
  16. --- a/arch/arm/boot/dts/bcm53573.dtsi
  17. +++ b/arch/arm/boot/dts/bcm53573.dtsi
  18. @@ -124,6 +124,17 @@
  19. reg = <0x4000 0x1000>;
  20. interrupt-parent = <&gic>;
  21. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  22. +
  23. + #address-cells = <1>;
  24. + #size-cells = <0>;
  25. +
  26. + ehci_port1: port@1 {
  27. + reg = <1>;
  28. + };
  29. +
  30. + ehci_port2: port@2 {
  31. + reg = <2>;
  32. + };
  33. };
  34. ohci: ohci@d000 {
  35. @@ -133,6 +144,17 @@
  36. reg = <0xd000 0x1000>;
  37. interrupt-parent = <&gic>;
  38. interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  39. +
  40. + #address-cells = <1>;
  41. + #size-cells = <0>;
  42. +
  43. + ohci_port1: port@1 {
  44. + reg = <1>;
  45. + };
  46. +
  47. + ohci_port2: port@2 {
  48. + reg = <2>;
  49. + };
  50. };
  51. };