046-0007-ARM-BCM5301X-Set-5-GHz-wireless-frequency-limits-on-.patch 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126
  1. From d3af86018715ebb19f4111f80e545405b208f09b Mon Sep 17 00:00:00 2001
  2. From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
  3. Date: Sat, 14 Jan 2017 00:58:57 +0100
  4. Subject: [PATCH] ARM: BCM5301X: Set 5 GHz wireless frequency limits on Netgear
  5. R8000
  6. MIME-Version: 1.0
  7. Content-Type: text/plain; charset=UTF-8
  8. Content-Transfer-Encoding: 8bit
  9. Netgear R8000 is a tri-band home router. It has three BCM43602 chipsets
  10. two of them for 5 GHz band. Both seem the same and their firmwares
  11. report the same set of channels. The problem is due to hardware / board
  12. design there are extra limitations that should be respected.
  13. First PHY should be used for U-NII-2 and U-NII-3. Third PHY should be
  14. used for U-NII-1. Using them in a different way may result in wireless
  15. not working or in noticeably reduced performance. Basic version of this
  16. info was provided by Broadcom employee, then it has been verified by me
  17. using original vendor firmware (which has limitations hardcoded in UI).
  18. This patch uses recently introduced ieee80211-freq-limit property to
  19. describe these limitations at DT level.
  20. Referencing PCIe devices in DT required specifying all related bridges.
  21. Below you can see (a bit complex) PCI tree from R8000 that explains all
  22. entries that I needed to put in DT.
  23. 0000:00:00.0 14e4:8012 Bridge Device
  24. └─ 0000:01:00.0 14e4:aa52 Network Controller
  25. 0001:00:00.0 14e4:8012 Bridge Device
  26. └─ 0001:01:00.0 10b5:8603 Bridge Device
  27. ├─ 0001:02:01.0 10b5:8603 Bridge Device
  28. │ └─ 0001:03:00.0 14e4:aa52 Network Controller
  29. ├─ 0001:02:02.0 10b5:8603 Bridge Device
  30. │ └─ 0001:04:00.0 14e4:aa52 Network Controller
  31. ├─ 0001:02:03.0 000d:0000 0x000000
  32. ├─ 0001:02:04.0 000d:0000 0x000000
  33. ├─ 0001:02:05.0 000d:0000 0x000000
  34. ├─ 0001:02:06.0 000d:0000 0x000000
  35. ├─ (...)
  36. ├─ 0001:02:1d.0 000d:0000 0x000000
  37. ├─ 0001:02:1e.0 000d:0000 0x000000
  38. └─ 0001:02:1f.0 000d:0000 0x000000
  39. Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  40. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  41. ---
  42. arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 48 +++++++++++++++++++++++++++++
  43. arch/arm/boot/dts/bcm5301x.dtsi | 8 +++++
  44. 2 files changed, 56 insertions(+)
  45. --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
  46. +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
  47. @@ -108,6 +108,54 @@
  48. };
  49. };
  50. +&pcie0 {
  51. + #address-cells = <3>;
  52. + #size-cells = <2>;
  53. +
  54. + bridge@0,0,0 {
  55. + reg = <0x0000 0 0 0 0>;
  56. +
  57. + #address-cells = <3>;
  58. + #size-cells = <2>;
  59. +
  60. + wifi@0,1,0 {
  61. + reg = <0x0000 0 0 0 0>;
  62. + ieee80211-freq-limit = <5735000 5835000>;
  63. + };
  64. + };
  65. +};
  66. +
  67. +&pcie1 {
  68. + #address-cells = <3>;
  69. + #size-cells = <2>;
  70. +
  71. + bridge@1,0,0 {
  72. + reg = <0x0000 0 0 0 0>;
  73. +
  74. + #address-cells = <3>;
  75. + #size-cells = <2>;
  76. +
  77. + bridge@1,1,0 {
  78. + reg = <0x0000 0 0 0 0>;
  79. +
  80. + #address-cells = <3>;
  81. + #size-cells = <2>;
  82. +
  83. + bridge@1,2,2 {
  84. + reg = <0x1000 0 0 0 0>;
  85. +
  86. + #address-cells = <3>;
  87. + #size-cells = <2>;
  88. +
  89. + wifi@1,4,0 {
  90. + reg = <0x0000 0 0 0 0>;
  91. + ieee80211-freq-limit = <5170000 5730000>;
  92. + };
  93. + };
  94. + };
  95. + };
  96. +};
  97. +
  98. &usb2 {
  99. vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
  100. };
  101. --- a/arch/arm/boot/dts/bcm5301x.dtsi
  102. +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  103. @@ -243,6 +243,14 @@
  104. #gpio-cells = <2>;
  105. };
  106. + pcie0: pcie@12000 {
  107. + reg = <0x00012000 0x1000>;
  108. + };
  109. +
  110. + pcie1: pcie@13000 {
  111. + reg = <0x00013000 0x1000>;
  112. + };
  113. +
  114. usb2: usb2@21000 {
  115. reg = <0x00021000 0x1000>;