0027-Main-bcm2708-bcm2709-linux-port.patch 76 KB

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  1. From 20ae9d488adbe06ef257b7920fab756063e2cf38 Mon Sep 17 00:00:00 2001
  2. From: popcornmix <popcornmix@gmail.com>
  3. Date: Sun, 12 May 2013 12:24:19 +0100
  4. Subject: [PATCH] Main bcm2708/bcm2709 linux port
  5. MIME-Version: 1.0
  6. Content-Type: text/plain; charset=UTF-8
  7. Content-Transfer-Encoding: 8bit
  8. Signed-off-by: popcornmix <popcornmix@gmail.com>
  9. Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  10. ---
  11. arch/arm/Kconfig | 49 +++
  12. arch/arm/Kconfig.debug | 8 +
  13. arch/arm/Makefile | 2 +
  14. arch/arm/kernel/head.S | 8 +
  15. arch/arm/kernel/process.c | 10 +
  16. arch/arm/mach-bcm2708/Kconfig | 23 ++
  17. arch/arm/mach-bcm2708/Makefile | 5 +
  18. arch/arm/mach-bcm2708/Makefile.boot | 3 +
  19. arch/arm/mach-bcm2708/bcm2708.c | 231 ++++++++++++
  20. arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 ++
  21. arch/arm/mach-bcm2708/include/mach/io.h | 27 ++
  22. arch/arm/mach-bcm2708/include/mach/memory.h | 57 +++
  23. arch/arm/mach-bcm2708/include/mach/platform.h | 112 ++++++
  24. arch/arm/mach-bcm2708/include/mach/system.h | 37 ++
  25. arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++++
  26. arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 ++
  27. arch/arm/mach-bcm2709/Kconfig | 16 +
  28. arch/arm/mach-bcm2709/Makefile | 5 +
  29. arch/arm/mach-bcm2709/Makefile.boot | 3 +
  30. arch/arm/mach-bcm2709/bcm2709.c | 380 ++++++++++++++++++++
  31. arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 ++
  32. arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 +++++++
  33. arch/arm/mach-bcm2709/include/mach/io.h | 27 ++
  34. arch/arm/mach-bcm2709/include/mach/memory.h | 57 +++
  35. arch/arm/mach-bcm2709/include/mach/platform.h | 188 ++++++++++
  36. arch/arm/mach-bcm2709/include/mach/system.h | 37 ++
  37. arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 +++++
  38. arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 ++
  39. arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 ++
  40. arch/arm/mach-bcm2709/vc_mem.c | 431 +++++++++++++++++++++++
  41. arch/arm/mm/Kconfig | 2 +-
  42. arch/arm/mm/proc-v6.S | 15 +-
  43. arch/arm/mm/proc-v7.S | 1 +
  44. arch/arm/tools/mach-types | 2 +
  45. drivers/clocksource/Makefile | 2 +-
  46. drivers/irqchip/Makefile | 3 +
  47. include/linux/mmc/host.h | 1 +
  48. 37 files changed, 2147 insertions(+), 5 deletions(-)
  49. create mode 100644 arch/arm/mach-bcm2708/Kconfig
  50. create mode 100644 arch/arm/mach-bcm2708/Makefile
  51. create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
  52. create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
  53. create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
  54. create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
  55. create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
  56. create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
  57. create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
  58. create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
  59. create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
  60. create mode 100644 arch/arm/mach-bcm2709/Kconfig
  61. create mode 100644 arch/arm/mach-bcm2709/Makefile
  62. create mode 100644 arch/arm/mach-bcm2709/Makefile.boot
  63. create mode 100644 arch/arm/mach-bcm2709/bcm2709.c
  64. create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S
  65. create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S
  66. create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h
  67. create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h
  68. create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h
  69. create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h
  70. create mode 100644 arch/arm/mach-bcm2709/include/mach/uncompress.h
  71. create mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h
  72. create mode 100644 arch/arm/mach-bcm2709/include/mach/vmalloc.h
  73. create mode 100644 arch/arm/mach-bcm2709/vc_mem.c
  74. --- a/arch/arm/Kconfig
  75. +++ b/arch/arm/Kconfig
  76. @@ -318,6 +318,52 @@ choice
  77. default ARCH_VERSATILE if !MMU
  78. default ARCH_MULTIPLATFORM if MMU
  79. +config ARCH_BCM2708
  80. + bool "Broadcom BCM2708 family"
  81. + select CPU_V6
  82. + select ARM_AMBA
  83. + select CLKSRC_MMIO
  84. + select CLKSRC_OF if OF
  85. + select HAVE_SCHED_CLOCK
  86. + select NEED_MACH_GPIO_H
  87. + select NEED_MACH_MEMORY_H
  88. + select COMMON_CLK
  89. + select ARCH_HAS_CPUFREQ
  90. + select GENERIC_CLOCKEVENTS
  91. + select ARM_ERRATA_411920
  92. + select MACH_BCM2708
  93. + select MULTI_IRQ_HANDLER
  94. + select SPARSE_IRQ
  95. + select VC4
  96. + select FIQ
  97. + help
  98. + This enables support for Broadcom BCM2708 boards.
  99. +
  100. +config ARCH_BCM2709
  101. + bool "Broadcom BCM2709 family"
  102. + select CPU_V7
  103. + select HAVE_SMP
  104. + select ARM_AMBA
  105. + select MIGHT_HAVE_CACHE_L2X0
  106. + select HAVE_SCHED_CLOCK
  107. + select NEED_MACH_MEMORY_H
  108. + select NEED_MACH_IO_H
  109. + select COMMON_CLK
  110. + select ARCH_HAS_CPUFREQ
  111. + select GENERIC_CLOCKEVENTS
  112. + select MACH_BCM2709
  113. + select MULTI_IRQ_HANDLER
  114. + select SPARSE_IRQ
  115. + select MFD_SYSCON
  116. + select VC4
  117. + select FIQ
  118. + select USE_OF
  119. + select ARCH_REQUIRE_GPIOLIB
  120. + select PINCTRL
  121. + select PINCTRL_BCM2835
  122. + help
  123. + This enables support for Broadcom BCM2709 boards.
  124. +
  125. config ARCH_MULTIPLATFORM
  126. bool "Allow multiple platforms to be selected"
  127. depends on MMU
  128. @@ -809,6 +855,9 @@ config ARCH_VIRT
  129. # Kconfigs may be included either alphabetically (according to the
  130. # plat- suffix) or along side the corresponding mach-* source.
  131. #
  132. +source "arch/arm/mach-bcm2708/Kconfig"
  133. +source "arch/arm/mach-bcm2709/Kconfig"
  134. +
  135. source "arch/arm/mach-mvebu/Kconfig"
  136. source "arch/arm/mach-alpine/Kconfig"
  137. --- a/arch/arm/Kconfig.debug
  138. +++ b/arch/arm/Kconfig.debug
  139. @@ -1240,6 +1240,14 @@ choice
  140. options; the platform specific options are deprecated
  141. and will be soon removed.
  142. + config DEBUG_BCM2708_UART0
  143. + bool "Broadcom BCM270X UART0 (PL011)"
  144. + depends on ARCH_BCM2708 || ARCH_BCM2709
  145. + help
  146. + Say Y here if you want the debug print routines to direct
  147. + their output to UART 0. The port must have been initialised
  148. + by the boot-loader before use.
  149. +
  150. endchoice
  151. config DEBUG_EXYNOS_UART
  152. --- a/arch/arm/Makefile
  153. +++ b/arch/arm/Makefile
  154. @@ -159,6 +159,8 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080
  155. # Machine directory name. This list is sorted alphanumerically
  156. # by CONFIG_* macro name.
  157. +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
  158. +machine-$(CONFIG_ARCH_BCM2709) += bcm2709
  159. machine-$(CONFIG_ARCH_ALPINE) += alpine
  160. machine-$(CONFIG_ARCH_AT91) += at91
  161. machine-$(CONFIG_ARCH_AXXIA) += axxia
  162. --- a/arch/arm/kernel/head.S
  163. +++ b/arch/arm/kernel/head.S
  164. @@ -700,6 +700,14 @@ ARM_BE8(rev16 ip, ip)
  165. ldrcc r7, [r4], #4 @ use branch for delay slot
  166. bcc 1b
  167. ret lr
  168. + nop
  169. + nop
  170. + nop
  171. + nop
  172. + nop
  173. + nop
  174. + nop
  175. + nop
  176. #endif
  177. ENDPROC(__fixup_a_pv_table)
  178. --- a/arch/arm/kernel/process.c
  179. +++ b/arch/arm/kernel/process.c
  180. @@ -91,6 +91,16 @@ void arch_cpu_idle_exit(void)
  181. ledtrig_cpu(CPU_LED_IDLE_END);
  182. }
  183. +char bcm2708_reboot_mode = 'h';
  184. +
  185. +int __init reboot_setup(char *str)
  186. +{
  187. + bcm2708_reboot_mode = str[0];
  188. + return 1;
  189. +}
  190. +
  191. +__setup("reboot=", reboot_setup);
  192. +
  193. void __show_regs(struct pt_regs *regs)
  194. {
  195. unsigned long flags;
  196. --- /dev/null
  197. +++ b/arch/arm/mach-bcm2708/Kconfig
  198. @@ -0,0 +1,23 @@
  199. +menu "Broadcom BCM2708 Implementations"
  200. + depends on ARCH_BCM2708
  201. +
  202. +config MACH_BCM2708
  203. + bool "Broadcom BCM2708 Development Platform"
  204. + select NEED_MACH_MEMORY_H
  205. + select NEED_MACH_IO_H
  206. + select CPU_V6
  207. + select USE_OF
  208. + select ARCH_REQUIRE_GPIOLIB
  209. + select PINCTRL
  210. + select PINCTRL_BCM2835
  211. + help
  212. + Include support for the Broadcom(R) BCM2708 platform.
  213. +
  214. +config BCM2708_NOL2CACHE
  215. + bool "Videocore L2 cache disable"
  216. + depends on MACH_BCM2708
  217. + default n
  218. + help
  219. + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
  220. +
  221. +endmenu
  222. --- /dev/null
  223. +++ b/arch/arm/mach-bcm2708/Makefile
  224. @@ -0,0 +1,5 @@
  225. +#
  226. +# Makefile for the linux kernel.
  227. +#
  228. +
  229. +obj-$(CONFIG_MACH_BCM2708) += bcm2708.o
  230. --- /dev/null
  231. +++ b/arch/arm/mach-bcm2708/Makefile.boot
  232. @@ -0,0 +1,3 @@
  233. + zreladdr-y := 0x00008000
  234. +params_phys-y := 0x00000100
  235. +initrd_phys-y := 0x00800000
  236. --- /dev/null
  237. +++ b/arch/arm/mach-bcm2708/bcm2708.c
  238. @@ -0,0 +1,231 @@
  239. +/*
  240. + * linux/arch/arm/mach-bcm2708/bcm2708.c
  241. + *
  242. + * Copyright (C) 2010 Broadcom
  243. + *
  244. + * This program is free software; you can redistribute it and/or modify
  245. + * it under the terms of the GNU General Public License as published by
  246. + * the Free Software Foundation; either version 2 of the License, or
  247. + * (at your option) any later version.
  248. + *
  249. + * This program is distributed in the hope that it will be useful,
  250. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  251. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  252. + * GNU General Public License for more details.
  253. + *
  254. + * You should have received a copy of the GNU General Public License
  255. + * along with this program; if not, write to the Free Software
  256. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  257. + */
  258. +
  259. +#include <linux/init.h>
  260. +#include <linux/dma-mapping.h>
  261. +#include <linux/module.h>
  262. +#include <linux/of_platform.h>
  263. +#include <asm/system_info.h>
  264. +#include <asm/mach-types.h>
  265. +#include <asm/mach/arch.h>
  266. +#include <asm/mach/map.h>
  267. +
  268. +#include <mach/system.h>
  269. +
  270. +#include <linux/broadcom/vc_cma.h>
  271. +
  272. +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
  273. + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
  274. + * represent this window by setting our dmamasks to 26 bits but, in fact
  275. + * we're not going to use addresses outside this range (they're not in real
  276. + * memory) so we don't bother.
  277. + *
  278. + * In the future we might include code to use this IOMMU to remap other
  279. + * physical addresses onto VideoCore memory then the use of 32-bits would be
  280. + * more legitimate.
  281. + */
  282. +
  283. +/* command line parameters */
  284. +static unsigned boardrev, serial;
  285. +static unsigned reboot_part = 0;
  286. +
  287. +static struct map_desc bcm2708_io_desc[] __initdata = {
  288. + {
  289. + .virtual = IO_ADDRESS(ARMCTRL_BASE),
  290. + .pfn = __phys_to_pfn(ARMCTRL_BASE),
  291. + .length = SZ_4K,
  292. + .type = MT_DEVICE},
  293. + {
  294. + .virtual = IO_ADDRESS(UART0_BASE),
  295. + .pfn = __phys_to_pfn(UART0_BASE),
  296. + .length = SZ_4K,
  297. + .type = MT_DEVICE},
  298. + {
  299. + .virtual = IO_ADDRESS(UART1_BASE),
  300. + .pfn = __phys_to_pfn(UART1_BASE),
  301. + .length = SZ_4K,
  302. + .type = MT_DEVICE},
  303. + {
  304. + .virtual = IO_ADDRESS(DMA_BASE),
  305. + .pfn = __phys_to_pfn(DMA_BASE),
  306. + .length = SZ_4K,
  307. + .type = MT_DEVICE},
  308. + {
  309. + .virtual = IO_ADDRESS(MCORE_BASE),
  310. + .pfn = __phys_to_pfn(MCORE_BASE),
  311. + .length = SZ_4K,
  312. + .type = MT_DEVICE},
  313. + {
  314. + .virtual = IO_ADDRESS(ST_BASE),
  315. + .pfn = __phys_to_pfn(ST_BASE),
  316. + .length = SZ_4K,
  317. + .type = MT_DEVICE},
  318. + {
  319. + .virtual = IO_ADDRESS(USB_BASE),
  320. + .pfn = __phys_to_pfn(USB_BASE),
  321. + .length = SZ_128K,
  322. + .type = MT_DEVICE},
  323. + {
  324. + .virtual = IO_ADDRESS(PM_BASE),
  325. + .pfn = __phys_to_pfn(PM_BASE),
  326. + .length = SZ_4K,
  327. + .type = MT_DEVICE},
  328. + {
  329. + .virtual = IO_ADDRESS(GPIO_BASE),
  330. + .pfn = __phys_to_pfn(GPIO_BASE),
  331. + .length = SZ_4K,
  332. + .type = MT_DEVICE}
  333. +};
  334. +
  335. +void __init bcm2708_map_io(void)
  336. +{
  337. + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
  338. +}
  339. +
  340. +int calc_rsts(int partition)
  341. +{
  342. + return PM_PASSWORD |
  343. + ((partition & (1 << 0)) << 0) |
  344. + ((partition & (1 << 1)) << 1) |
  345. + ((partition & (1 << 2)) << 2) |
  346. + ((partition & (1 << 3)) << 3) |
  347. + ((partition & (1 << 4)) << 4) |
  348. + ((partition & (1 << 5)) << 5);
  349. +}
  350. +
  351. +static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
  352. +{
  353. + extern char bcm2708_reboot_mode;
  354. + uint32_t pm_rstc, pm_wdog;
  355. + uint32_t timeout = 10;
  356. + uint32_t pm_rsts = 0;
  357. +
  358. + if(bcm2708_reboot_mode == 'q')
  359. + {
  360. + // NOOBS < 1.3 booting with reboot=q
  361. + pm_rsts = readl(__io_address(PM_RSTS));
  362. + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
  363. + }
  364. + else if(bcm2708_reboot_mode == 'p')
  365. + {
  366. + // NOOBS < 1.3 halting
  367. + pm_rsts = readl(__io_address(PM_RSTS));
  368. + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
  369. + }
  370. + else
  371. + {
  372. + pm_rsts = calc_rsts(reboot_part);
  373. + }
  374. +
  375. + writel(pm_rsts, __io_address(PM_RSTS));
  376. +
  377. + /* Setup watchdog for reset */
  378. + pm_rstc = readl(__io_address(PM_RSTC));
  379. +
  380. + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
  381. + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
  382. +
  383. + writel(pm_wdog, __io_address(PM_WDOG));
  384. + writel(pm_rstc, __io_address(PM_RSTC));
  385. +}
  386. +
  387. +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
  388. +static void bcm2708_power_off(void)
  389. +{
  390. + extern char bcm2708_reboot_mode;
  391. + if(bcm2708_reboot_mode == 'q')
  392. + {
  393. + // NOOBS < v1.3
  394. + bcm2708_restart('p', "");
  395. + }
  396. + else
  397. + {
  398. + /* partition 63 is special code for HALT the bootloader knows not to boot*/
  399. + reboot_part = 63;
  400. + /* continue with normal reset mechanism */
  401. + bcm2708_restart(0, "");
  402. + }
  403. +}
  404. +
  405. +static void __init bcm2708_init_uart1(void)
  406. +{
  407. + struct device_node *np;
  408. +
  409. + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
  410. + if (of_device_is_available(np)) {
  411. + pr_info("bcm2708: Mini UART enabled\n");
  412. + writel(1, __io_address(UART1_BASE + 0x4));
  413. + }
  414. +}
  415. +
  416. +void __init bcm2708_init(void)
  417. +{
  418. + int ret;
  419. +
  420. + vc_cma_early_init();
  421. +
  422. + pm_power_off = bcm2708_power_off;
  423. +
  424. + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
  425. + NULL);
  426. + if (ret) {
  427. + pr_err("of_platform_populate failed: %d\n", ret);
  428. + BUG();
  429. + }
  430. +
  431. + bcm2708_init_uart1();
  432. +
  433. + system_rev = boardrev;
  434. + system_serial_low = serial;
  435. +}
  436. +
  437. +void __init bcm2708_init_early(void)
  438. +{
  439. + /*
  440. + * Some devices allocate their coherent buffers from atomic
  441. + * context. Increase size of atomic coherent pool to make sure such
  442. + * the allocations won't fail.
  443. + */
  444. + init_dma_coherent_pool_size(SZ_4M);
  445. +}
  446. +
  447. +static void __init board_reserve(void)
  448. +{
  449. + vc_cma_reserve();
  450. +}
  451. +
  452. +static const char * const bcm2708_compat[] = {
  453. + "brcm,bcm2708",
  454. + NULL
  455. +};
  456. +
  457. +MACHINE_START(BCM2708, "BCM2708")
  458. + /* Maintainer: Broadcom Europe Ltd. */
  459. + .map_io = bcm2708_map_io,
  460. + .init_machine = bcm2708_init,
  461. + .init_early = bcm2708_init_early,
  462. + .reserve = board_reserve,
  463. + .restart = bcm2708_restart,
  464. + .dt_compat = bcm2708_compat,
  465. +MACHINE_END
  466. +
  467. +module_param(boardrev, uint, 0644);
  468. +module_param(serial, uint, 0644);
  469. +module_param(reboot_part, uint, 0644);
  470. --- /dev/null
  471. +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
  472. @@ -0,0 +1,22 @@
  473. +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
  474. + *
  475. + * Debugging macro include header
  476. + *
  477. + * Copyright (C) 2010 Broadcom
  478. + * Copyright (C) 1994-1999 Russell King
  479. + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
  480. + *
  481. + * This program is free software; you can redistribute it and/or modify
  482. + * it under the terms of the GNU General Public License version 2 as
  483. + * published by the Free Software Foundation.
  484. + *
  485. +*/
  486. +
  487. +#include <mach/platform.h>
  488. +
  489. + .macro addruart, rp, rv, tmp
  490. + ldr \rp, =UART0_BASE
  491. + ldr \rv, =IO_ADDRESS(UART0_BASE)
  492. + .endm
  493. +
  494. +#include <debug/pl01x.S>
  495. --- /dev/null
  496. +++ b/arch/arm/mach-bcm2708/include/mach/io.h
  497. @@ -0,0 +1,27 @@
  498. +/*
  499. + * arch/arm/mach-bcm2708/include/mach/io.h
  500. + *
  501. + * Copyright (C) 2003 ARM Limited
  502. + *
  503. + * This program is free software; you can redistribute it and/or modify
  504. + * it under the terms of the GNU General Public License as published by
  505. + * the Free Software Foundation; either version 2 of the License, or
  506. + * (at your option) any later version.
  507. + *
  508. + * This program is distributed in the hope that it will be useful,
  509. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  510. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  511. + * GNU General Public License for more details.
  512. + *
  513. + * You should have received a copy of the GNU General Public License
  514. + * along with this program; if not, write to the Free Software
  515. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  516. + */
  517. +#ifndef __ASM_ARM_ARCH_IO_H
  518. +#define __ASM_ARM_ARCH_IO_H
  519. +
  520. +#define IO_SPACE_LIMIT 0xffffffff
  521. +
  522. +#define __io(a) __typesafe_io(a)
  523. +
  524. +#endif
  525. --- /dev/null
  526. +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
  527. @@ -0,0 +1,57 @@
  528. +/*
  529. + * arch/arm/mach-bcm2708/include/mach/memory.h
  530. + *
  531. + * Copyright (C) 2010 Broadcom
  532. + *
  533. + * This program is free software; you can redistribute it and/or modify
  534. + * it under the terms of the GNU General Public License as published by
  535. + * the Free Software Foundation; either version 2 of the License, or
  536. + * (at your option) any later version.
  537. + *
  538. + * This program is distributed in the hope that it will be useful,
  539. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  540. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  541. + * GNU General Public License for more details.
  542. + *
  543. + * You should have received a copy of the GNU General Public License
  544. + * along with this program; if not, write to the Free Software
  545. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  546. + */
  547. +#ifndef __ASM_ARCH_MEMORY_H
  548. +#define __ASM_ARCH_MEMORY_H
  549. +
  550. +/* Memory overview:
  551. +
  552. + [ARMcore] <--virtual addr-->
  553. + [ARMmmu] <--physical addr-->
  554. + [GERTmap] <--bus add-->
  555. + [VCperiph]
  556. +
  557. +*/
  558. +
  559. +/*
  560. + * Physical DRAM offset.
  561. + */
  562. +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
  563. +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
  564. +
  565. +#ifdef CONFIG_BCM2708_NOL2CACHE
  566. + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
  567. +#else
  568. + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
  569. +#endif
  570. +
  571. +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
  572. + * will provide the offset into this area as well as setting the bits that
  573. + * stop the L1 and L2 cache from being used
  574. + *
  575. + * WARNING: this only works because the ARM is given memory at a fixed location
  576. + * (ARMMEM_OFFSET)
  577. + */
  578. +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
  579. +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
  580. +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
  581. +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
  582. +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
  583. +
  584. +#endif
  585. --- /dev/null
  586. +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
  587. @@ -0,0 +1,112 @@
  588. +/*
  589. + * arch/arm/mach-bcm2708/include/mach/platform.h
  590. + *
  591. + * Copyright (C) 2010 Broadcom
  592. + *
  593. + * This program is free software; you can redistribute it and/or modify
  594. + * it under the terms of the GNU General Public License as published by
  595. + * the Free Software Foundation; either version 2 of the License, or
  596. + * (at your option) any later version.
  597. + *
  598. + * This program is distributed in the hope that it will be useful,
  599. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  600. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  601. + * GNU General Public License for more details.
  602. + *
  603. + * You should have received a copy of the GNU General Public License
  604. + * along with this program; if not, write to the Free Software
  605. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  606. + */
  607. +
  608. +#ifndef _BCM2708_PLATFORM_H
  609. +#define _BCM2708_PLATFORM_H
  610. +
  611. +
  612. +/* macros to get at IO space when running virtually */
  613. +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
  614. +
  615. +#define __io_address(n) IOMEM(IO_ADDRESS(n))
  616. +
  617. +
  618. +/*
  619. + * SDRAM
  620. + */
  621. +#define BCM2708_SDRAM_BASE 0x00000000
  622. +
  623. +/*
  624. + * Logic expansion modules
  625. + *
  626. + */
  627. +
  628. +
  629. +/* ------------------------------------------------------------------------
  630. + * BCM2708 ARMCTRL Registers
  631. + * ------------------------------------------------------------------------
  632. + */
  633. +
  634. +#define HW_REGISTER_RW(addr) (addr)
  635. +#define HW_REGISTER_RO(addr) (addr)
  636. +
  637. +/*
  638. + * Definitions and addresses for the ARM CONTROL logic
  639. + * This file is manually generated.
  640. + */
  641. +
  642. +#define BCM2708_PERI_BASE 0x20000000
  643. +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
  644. +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
  645. +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
  646. +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
  647. +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
  648. +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
  649. +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
  650. +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
  651. +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
  652. +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
  653. +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
  654. +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
  655. +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
  656. +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
  657. +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
  658. +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
  659. +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
  660. +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
  661. +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
  662. +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
  663. +
  664. +#define ARMCTRL_BASE (ARM_BASE + 0x000)
  665. +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
  666. +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
  667. +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
  668. +
  669. +/*
  670. + * Watchdog
  671. + */
  672. +#define PM_RSTC (PM_BASE+0x1c)
  673. +#define PM_RSTS (PM_BASE+0x20)
  674. +#define PM_WDOG (PM_BASE+0x24)
  675. +
  676. +#define PM_WDOG_RESET 0000000000
  677. +#define PM_PASSWORD 0x5a000000
  678. +#define PM_WDOG_TIME_SET 0x000fffff
  679. +#define PM_RSTC_WRCFG_CLR 0xffffffcf
  680. +#define PM_RSTC_WRCFG_SET 0x00000030
  681. +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
  682. +#define PM_RSTC_RESET 0x00000102
  683. +
  684. +#define PM_RSTS_HADPOR_SET 0x00001000
  685. +#define PM_RSTS_HADSRH_SET 0x00000400
  686. +#define PM_RSTS_HADSRF_SET 0x00000200
  687. +#define PM_RSTS_HADSRQ_SET 0x00000100
  688. +#define PM_RSTS_HADWRH_SET 0x00000040
  689. +#define PM_RSTS_HADWRF_SET 0x00000020
  690. +#define PM_RSTS_HADWRQ_SET 0x00000010
  691. +#define PM_RSTS_HADDRH_SET 0x00000004
  692. +#define PM_RSTS_HADDRF_SET 0x00000002
  693. +#define PM_RSTS_HADDRQ_SET 0x00000001
  694. +
  695. +#define UART0_CLOCK 3000000
  696. +
  697. +#endif
  698. +
  699. +/* END */
  700. --- /dev/null
  701. +++ b/arch/arm/mach-bcm2708/include/mach/system.h
  702. @@ -0,0 +1,37 @@
  703. +/*
  704. + * arch/arm/mach-bcm2708/include/mach/system.h
  705. + *
  706. + * Copyright (C) 2010 Broadcom
  707. + * Copyright (C) 2003 ARM Limited
  708. + * Copyright (C) 2000 Deep Blue Solutions Ltd
  709. + *
  710. + * This program is free software; you can redistribute it and/or modify
  711. + * it under the terms of the GNU General Public License as published by
  712. + * the Free Software Foundation; either version 2 of the License, or
  713. + * (at your option) any later version.
  714. + *
  715. + * This program is distributed in the hope that it will be useful,
  716. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  717. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  718. + * GNU General Public License for more details.
  719. + *
  720. + * You should have received a copy of the GNU General Public License
  721. + * along with this program; if not, write to the Free Software
  722. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  723. + */
  724. +#ifndef __ASM_ARCH_SYSTEM_H
  725. +#define __ASM_ARCH_SYSTEM_H
  726. +
  727. +#include <linux/io.h>
  728. +#include <mach/platform.h>
  729. +
  730. +static inline void arch_idle(void)
  731. +{
  732. + /*
  733. + * This should do all the clock switching
  734. + * and wait for interrupt tricks
  735. + */
  736. + cpu_do_idle();
  737. +}
  738. +
  739. +#endif
  740. --- /dev/null
  741. +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
  742. @@ -0,0 +1,84 @@
  743. +/*
  744. + * arch/arm/mach-bcn2708/include/mach/uncompress.h
  745. + *
  746. + * Copyright (C) 2010 Broadcom
  747. + * Copyright (C) 2003 ARM Limited
  748. + *
  749. + * This program is free software; you can redistribute it and/or modify
  750. + * it under the terms of the GNU General Public License as published by
  751. + * the Free Software Foundation; either version 2 of the License, or
  752. + * (at your option) any later version.
  753. + *
  754. + * This program is distributed in the hope that it will be useful,
  755. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  756. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  757. + * GNU General Public License for more details.
  758. + *
  759. + * You should have received a copy of the GNU General Public License
  760. + * along with this program; if not, write to the Free Software
  761. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  762. + */
  763. +
  764. +#include <linux/io.h>
  765. +#include <linux/amba/serial.h>
  766. +#include <mach/platform.h>
  767. +
  768. +#define UART_BAUD 115200
  769. +
  770. +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
  771. +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
  772. +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
  773. +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
  774. +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
  775. +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
  776. +
  777. +/*
  778. + * This does not append a newline
  779. + */
  780. +static inline void putc(int c)
  781. +{
  782. + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
  783. + barrier();
  784. +
  785. + __raw_writel(c, BCM2708_UART_DR);
  786. +}
  787. +
  788. +static inline void flush(void)
  789. +{
  790. + int fr;
  791. +
  792. + do {
  793. + fr = __raw_readl(BCM2708_UART_FR);
  794. + barrier();
  795. + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
  796. +}
  797. +
  798. +static inline void arch_decomp_setup(void)
  799. +{
  800. + int temp, div, rem, frac;
  801. +
  802. + temp = 16 * UART_BAUD;
  803. + div = UART0_CLOCK / temp;
  804. + rem = UART0_CLOCK % temp;
  805. + temp = (8 * rem) / UART_BAUD;
  806. + frac = (temp >> 1) + (temp & 1);
  807. +
  808. + /* Make sure the UART is disabled before we start */
  809. + __raw_writel(0, BCM2708_UART_CR);
  810. +
  811. + /* Set the baud rate */
  812. + __raw_writel(div, BCM2708_UART_IBRD);
  813. + __raw_writel(frac, BCM2708_UART_FBRD);
  814. +
  815. + /* Set the UART to 8n1, FIFO enabled */
  816. + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
  817. +
  818. + /* Enable the UART */
  819. + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
  820. + BCM2708_UART_CR);
  821. +}
  822. +
  823. +/*
  824. + * nothing to do
  825. + */
  826. +#define arch_decomp_wdog()
  827. --- /dev/null
  828. +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
  829. @@ -0,0 +1,20 @@
  830. +/*
  831. + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
  832. + *
  833. + * Copyright (C) 2010 Broadcom
  834. + *
  835. + * This program is free software; you can redistribute it and/or modify
  836. + * it under the terms of the GNU General Public License as published by
  837. + * the Free Software Foundation; either version 2 of the License, or
  838. + * (at your option) any later version.
  839. + *
  840. + * This program is distributed in the hope that it will be useful,
  841. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  842. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  843. + * GNU General Public License for more details.
  844. + *
  845. + * You should have received a copy of the GNU General Public License
  846. + * along with this program; if not, write to the Free Software
  847. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  848. + */
  849. +#define VMALLOC_END (0xe8000000)
  850. --- /dev/null
  851. +++ b/arch/arm/mach-bcm2709/Kconfig
  852. @@ -0,0 +1,16 @@
  853. +menu "Broadcom BCM2709 Implementations"
  854. + depends on ARCH_BCM2709
  855. +
  856. +config MACH_BCM2709
  857. + bool "Broadcom BCM2709 Development Platform"
  858. + help
  859. + Include support for the Broadcom(R) BCM2709 platform.
  860. +
  861. +config BCM2708_NOL2CACHE
  862. + bool "Videocore L2 cache disable"
  863. + depends on MACH_BCM2709
  864. + default y
  865. + help
  866. + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
  867. +
  868. +endmenu
  869. --- /dev/null
  870. +++ b/arch/arm/mach-bcm2709/Makefile
  871. @@ -0,0 +1,5 @@
  872. +#
  873. +# Makefile for the linux kernel.
  874. +#
  875. +
  876. +obj-$(CONFIG_MACH_BCM2709) += bcm2709.o
  877. --- /dev/null
  878. +++ b/arch/arm/mach-bcm2709/Makefile.boot
  879. @@ -0,0 +1,3 @@
  880. + zreladdr-y := 0x00008000
  881. +params_phys-y := 0x00000100
  882. +initrd_phys-y := 0x00800000
  883. --- /dev/null
  884. +++ b/arch/arm/mach-bcm2709/bcm2709.c
  885. @@ -0,0 +1,380 @@
  886. +/*
  887. + * linux/arch/arm/mach-bcm2709/bcm2709.c
  888. + *
  889. + * Copyright (C) 2010 Broadcom
  890. + *
  891. + * This program is free software; you can redistribute it and/or modify
  892. + * it under the terms of the GNU General Public License as published by
  893. + * the Free Software Foundation; either version 2 of the License, or
  894. + * (at your option) any later version.
  895. + *
  896. + * This program is distributed in the hope that it will be useful,
  897. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  898. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  899. + * GNU General Public License for more details.
  900. + *
  901. + * You should have received a copy of the GNU General Public License
  902. + * along with this program; if not, write to the Free Software
  903. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  904. + */
  905. +
  906. +#include <linux/init.h>
  907. +#include <linux/dma-mapping.h>
  908. +#include <linux/interrupt.h>
  909. +#include <linux/clk-provider.h>
  910. +#include <linux/clocksource.h>
  911. +#include <linux/io.h>
  912. +#include <linux/module.h>
  913. +#include <linux/of_platform.h>
  914. +
  915. +#include <asm/system_info.h>
  916. +#include <asm/mach-types.h>
  917. +#include <asm/cputype.h>
  918. +
  919. +#include <asm/mach/arch.h>
  920. +#include <asm/mach/map.h>
  921. +
  922. +#include <mach/system.h>
  923. +
  924. +#include <linux/broadcom/vc_cma.h>
  925. +
  926. +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
  927. + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
  928. + * represent this window by setting our dmamasks to 26 bits but, in fact
  929. + * we're not going to use addresses outside this range (they're not in real
  930. + * memory) so we don't bother.
  931. + *
  932. + * In the future we might include code to use this IOMMU to remap other
  933. + * physical addresses onto VideoCore memory then the use of 32-bits would be
  934. + * more legitimate.
  935. + */
  936. +
  937. +/* command line parameters */
  938. +static unsigned boardrev, serial;
  939. +static unsigned reboot_part = 0;
  940. +
  941. +static struct map_desc bcm2709_io_desc[] __initdata = {
  942. + {
  943. + .virtual = IO_ADDRESS(ARMCTRL_BASE),
  944. + .pfn = __phys_to_pfn(ARMCTRL_BASE),
  945. + .length = SZ_4K,
  946. + .type = MT_DEVICE},
  947. + {
  948. + .virtual = IO_ADDRESS(UART0_BASE),
  949. + .pfn = __phys_to_pfn(UART0_BASE),
  950. + .length = SZ_4K,
  951. + .type = MT_DEVICE},
  952. + {
  953. + .virtual = IO_ADDRESS(UART1_BASE),
  954. + .pfn = __phys_to_pfn(UART1_BASE),
  955. + .length = SZ_4K,
  956. + .type = MT_DEVICE},
  957. + {
  958. + .virtual = IO_ADDRESS(DMA_BASE),
  959. + .pfn = __phys_to_pfn(DMA_BASE),
  960. + .length = SZ_4K,
  961. + .type = MT_DEVICE},
  962. + {
  963. + .virtual = IO_ADDRESS(MCORE_BASE),
  964. + .pfn = __phys_to_pfn(MCORE_BASE),
  965. + .length = SZ_4K,
  966. + .type = MT_DEVICE},
  967. + {
  968. + .virtual = IO_ADDRESS(ST_BASE),
  969. + .pfn = __phys_to_pfn(ST_BASE),
  970. + .length = SZ_4K,
  971. + .type = MT_DEVICE},
  972. + {
  973. + .virtual = IO_ADDRESS(USB_BASE),
  974. + .pfn = __phys_to_pfn(USB_BASE),
  975. + .length = SZ_128K,
  976. + .type = MT_DEVICE},
  977. + {
  978. + .virtual = IO_ADDRESS(PM_BASE),
  979. + .pfn = __phys_to_pfn(PM_BASE),
  980. + .length = SZ_4K,
  981. + .type = MT_DEVICE},
  982. + {
  983. + .virtual = IO_ADDRESS(GPIO_BASE),
  984. + .pfn = __phys_to_pfn(GPIO_BASE),
  985. + .length = SZ_4K,
  986. + .type = MT_DEVICE},
  987. + {
  988. + .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
  989. + .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
  990. + .length = SZ_4K,
  991. + .type = MT_DEVICE},
  992. +};
  993. +
  994. +void __init bcm2709_map_io(void)
  995. +{
  996. + iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
  997. +}
  998. +
  999. +int calc_rsts(int partition)
  1000. +{
  1001. + return PM_PASSWORD |
  1002. + ((partition & (1 << 0)) << 0) |
  1003. + ((partition & (1 << 1)) << 1) |
  1004. + ((partition & (1 << 2)) << 2) |
  1005. + ((partition & (1 << 3)) << 3) |
  1006. + ((partition & (1 << 4)) << 4) |
  1007. + ((partition & (1 << 5)) << 5);
  1008. +}
  1009. +
  1010. +static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
  1011. +{
  1012. + extern char bcm2708_reboot_mode;
  1013. + uint32_t pm_rstc, pm_wdog;
  1014. + uint32_t timeout = 10;
  1015. + uint32_t pm_rsts = 0;
  1016. +
  1017. + if(bcm2708_reboot_mode == 'q')
  1018. + {
  1019. + // NOOBS < 1.3 booting with reboot=q
  1020. + pm_rsts = readl(__io_address(PM_RSTS));
  1021. + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
  1022. + }
  1023. + else if(bcm2708_reboot_mode == 'p')
  1024. + {
  1025. + // NOOBS < 1.3 halting
  1026. + pm_rsts = readl(__io_address(PM_RSTS));
  1027. + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
  1028. + }
  1029. + else
  1030. + {
  1031. + pm_rsts = calc_rsts(reboot_part);
  1032. + }
  1033. +
  1034. + writel(pm_rsts, __io_address(PM_RSTS));
  1035. +
  1036. + /* Setup watchdog for reset */
  1037. + pm_rstc = readl(__io_address(PM_RSTC));
  1038. +
  1039. + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
  1040. + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
  1041. +
  1042. + writel(pm_wdog, __io_address(PM_WDOG));
  1043. + writel(pm_rstc, __io_address(PM_RSTC));
  1044. +}
  1045. +
  1046. +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
  1047. +static void bcm2709_power_off(void)
  1048. +{
  1049. + extern char bcm2708_reboot_mode;
  1050. + if(bcm2708_reboot_mode == 'q')
  1051. + {
  1052. + // NOOBS < v1.3
  1053. + bcm2709_restart('p', "");
  1054. + }
  1055. + else
  1056. + {
  1057. + /* partition 63 is special code for HALT the bootloader knows not to boot*/
  1058. + reboot_part = 63;
  1059. + /* continue with normal reset mechanism */
  1060. + bcm2709_restart(0, "");
  1061. + }
  1062. +}
  1063. +
  1064. +static void __init bcm2709_init_uart1(void)
  1065. +{
  1066. + struct device_node *np;
  1067. +
  1068. + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
  1069. + if (of_device_is_available(np)) {
  1070. + pr_info("bcm2709: Mini UART enabled\n");
  1071. + writel(1, __io_address(UART1_BASE + 0x4));
  1072. + }
  1073. +}
  1074. +
  1075. +void __init bcm2709_init(void)
  1076. +{
  1077. + int ret;
  1078. +
  1079. + vc_cma_early_init();
  1080. +
  1081. + pm_power_off = bcm2709_power_off;
  1082. +
  1083. + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
  1084. + NULL);
  1085. + if (ret) {
  1086. + pr_err("of_platform_populate failed: %d\n", ret);
  1087. + BUG();
  1088. + }
  1089. +
  1090. + bcm2709_init_uart1();
  1091. +
  1092. + system_rev = boardrev;
  1093. + system_serial_low = serial;
  1094. +}
  1095. +
  1096. +static void __init bcm2709_timer_init(void)
  1097. +{
  1098. + // timer control
  1099. + writel(0, __io_address(ARM_LOCAL_CONTROL));
  1100. + // timer pre_scaler
  1101. + writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
  1102. + //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
  1103. +
  1104. + of_clk_init(NULL);
  1105. + clocksource_probe();
  1106. +}
  1107. +
  1108. +
  1109. +void __init bcm2709_init_early(void)
  1110. +{
  1111. + /*
  1112. + * Some devices allocate their coherent buffers from atomic
  1113. + * context. Increase size of atomic coherent pool to make sure such
  1114. + * the allocations won't fail.
  1115. + */
  1116. + init_dma_coherent_pool_size(SZ_4M);
  1117. +}
  1118. +
  1119. +static void __init board_reserve(void)
  1120. +{
  1121. + vc_cma_reserve();
  1122. +}
  1123. +
  1124. +
  1125. +#ifdef CONFIG_SMP
  1126. +#include <linux/smp.h>
  1127. +
  1128. +#include <asm/cacheflush.h>
  1129. +#include <asm/smp_plat.h>
  1130. +int dc4=0;
  1131. +//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
  1132. +void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
  1133. +
  1134. +static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
  1135. +{
  1136. + int cpu;
  1137. + /*
  1138. + * Ensure that stores to Normal memory are visible to the
  1139. + * other CPUs before issuing the IPI.
  1140. + */
  1141. + dsb();
  1142. +
  1143. + /* Convert our logical CPU mask into a physical one. */
  1144. + for_each_cpu(cpu, mask)
  1145. + {
  1146. + /* submit softirq */
  1147. + writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
  1148. + }
  1149. +}
  1150. +
  1151. +void __init bcm2709_smp_init_cpus(void)
  1152. +{
  1153. + void secondary_startup(void);
  1154. + unsigned int i, ncores;
  1155. +
  1156. + ncores = 4; // xxx scu_get_core_count(NULL);
  1157. + printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
  1158. + printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
  1159. +
  1160. + for (i = 0; i < ncores; i++) {
  1161. + set_cpu_possible(i, true);
  1162. + /* enable IRQ (not FIQ) */
  1163. + writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
  1164. + //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
  1165. + }
  1166. + set_smp_cross_call(bcm2835_send_doorbell);
  1167. +}
  1168. +
  1169. +/*
  1170. + * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
  1171. + */
  1172. +void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
  1173. +{
  1174. + //void __iomem *scu_base;
  1175. +
  1176. + printk("[%s] enter\n", __FUNCTION__);
  1177. + //scu_base = scu_base_addr();
  1178. + //scu_enable(scu_base);
  1179. +}
  1180. +
  1181. +/*
  1182. + * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
  1183. + */
  1184. +void __init bcm2709_secondary_init(unsigned int cpu)
  1185. +{
  1186. + printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
  1187. + //gic_secondary_init(0);
  1188. +}
  1189. +
  1190. +/*
  1191. + * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
  1192. + */
  1193. +int __init bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
  1194. +{
  1195. + void secondary_startup(void);
  1196. + void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
  1197. + void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
  1198. + unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
  1199. + int timeout=20;
  1200. + unsigned t = -1;
  1201. + //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
  1202. +
  1203. + dsb();
  1204. + BUG_ON(readl(mbox_clr) != 0);
  1205. + writel(secondary_boot, mbox_set);
  1206. +
  1207. + while (--timeout > 0) {
  1208. + t = readl(mbox_clr);
  1209. + if (t == 0) break;
  1210. + cpu_relax();
  1211. + }
  1212. + if (timeout==0)
  1213. + printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
  1214. + else
  1215. + printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
  1216. +
  1217. + return 0;
  1218. +}
  1219. +
  1220. +
  1221. +struct smp_operations bcm2709_smp_ops __initdata = {
  1222. + .smp_init_cpus = bcm2709_smp_init_cpus,
  1223. + .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
  1224. + .smp_secondary_init = bcm2709_secondary_init,
  1225. + .smp_boot_secondary = bcm2709_boot_secondary,
  1226. +};
  1227. +#endif
  1228. +
  1229. +static const char * const bcm2709_compat[] = {
  1230. + "brcm,bcm2709",
  1231. + "brcm,bcm2708", /* Could use bcm2708 in a pinch */
  1232. + NULL
  1233. +};
  1234. +
  1235. +MACHINE_START(BCM2709, "BCM2709")
  1236. + /* Maintainer: Broadcom Europe Ltd. */
  1237. +#ifdef CONFIG_SMP
  1238. + .smp = smp_ops(bcm2709_smp_ops),
  1239. +#endif
  1240. + .map_io = bcm2709_map_io,
  1241. + .init_time = bcm2709_timer_init,
  1242. + .init_machine = bcm2709_init,
  1243. + .init_early = bcm2709_init_early,
  1244. + .reserve = board_reserve,
  1245. + .restart = bcm2709_restart,
  1246. + .dt_compat = bcm2709_compat,
  1247. +MACHINE_END
  1248. +
  1249. +MACHINE_START(BCM2708, "BCM2709")
  1250. + /* Maintainer: Broadcom Europe Ltd. */
  1251. +#ifdef CONFIG_SMP
  1252. + .smp = smp_ops(bcm2709_smp_ops),
  1253. +#endif
  1254. + .map_io = bcm2709_map_io,
  1255. + .init_time = bcm2709_timer_init,
  1256. + .init_machine = bcm2709_init,
  1257. + .init_early = bcm2709_init_early,
  1258. + .reserve = board_reserve,
  1259. + .restart = bcm2709_restart,
  1260. + .dt_compat = bcm2709_compat,
  1261. +MACHINE_END
  1262. +
  1263. +module_param(boardrev, uint, 0644);
  1264. +module_param(serial, uint, 0644);
  1265. +module_param(reboot_part, uint, 0644);
  1266. --- /dev/null
  1267. +++ b/arch/arm/mach-bcm2709/include/mach/debug-macro.S
  1268. @@ -0,0 +1,22 @@
  1269. +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
  1270. + *
  1271. + * Debugging macro include header
  1272. + *
  1273. + * Copyright (C) 2010 Broadcom
  1274. + * Copyright (C) 1994-1999 Russell King
  1275. + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
  1276. + *
  1277. + * This program is free software; you can redistribute it and/or modify
  1278. + * it under the terms of the GNU General Public License version 2 as
  1279. + * published by the Free Software Foundation.
  1280. + *
  1281. +*/
  1282. +
  1283. +#include <mach/platform.h>
  1284. +
  1285. + .macro addruart, rp, rv, tmp
  1286. + ldr \rp, =UART0_BASE
  1287. + ldr \rv, =IO_ADDRESS(UART0_BASE)
  1288. + .endm
  1289. +
  1290. +#include <debug/pl01x.S>
  1291. --- /dev/null
  1292. +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
  1293. @@ -0,0 +1,123 @@
  1294. +/*
  1295. + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
  1296. + *
  1297. + * Low-level IRQ helper macros for BCM2708 platforms
  1298. + *
  1299. + * Copyright (C) 2010 Broadcom
  1300. + *
  1301. + * This program is free software; you can redistribute it and/or modify
  1302. + * it under the terms of the GNU General Public License as published by
  1303. + * the Free Software Foundation; either version 2 of the License, or
  1304. + * (at your option) any later version.
  1305. + *
  1306. + * This program is distributed in the hope that it will be useful,
  1307. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1308. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1309. + * GNU General Public License for more details.
  1310. + *
  1311. + * You should have received a copy of the GNU General Public License
  1312. + * along with this program; if not, write to the Free Software
  1313. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  1314. + */
  1315. +#include <mach/hardware.h>
  1316. +#include <mach/irqs.h>
  1317. +
  1318. + .macro disable_fiq
  1319. + .endm
  1320. +
  1321. + .macro get_irqnr_preamble, base, tmp
  1322. + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
  1323. + .endm
  1324. +
  1325. + .macro arch_ret_to_user, tmp1, tmp2
  1326. + .endm
  1327. +
  1328. + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
  1329. + /* get core number */
  1330. + mrc p15, 0, \tmp, c0, c0, 5
  1331. + ubfx \tmp, \tmp, #0, #2
  1332. +
  1333. + /* get core's local interrupt controller */
  1334. + ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
  1335. + add \irqstat, \irqstat, \tmp, lsl #2
  1336. + ldr \tmp, [\irqstat]
  1337. + /* ignore gpu interrupt */
  1338. + bic \tmp, #0x100
  1339. + /* ignore mailbox interrupts */
  1340. + bics \tmp, #0xf0
  1341. + beq 1005f
  1342. +
  1343. + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
  1344. + @ N.B. CLZ is an ARM5 instruction.
  1345. + mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
  1346. + sub \irqstat, \tmp, #1
  1347. + eor \irqstat, \irqstat, \tmp
  1348. + clz \tmp, \irqstat
  1349. + sub \irqnr, \tmp
  1350. + b 1020f
  1351. +1005:
  1352. + /* get core number */
  1353. + mrc p15, 0, \tmp, c0, c0, 5
  1354. + ubfx \tmp, \tmp, #0, #2
  1355. +
  1356. + cmp \tmp, #1
  1357. + beq 1020f
  1358. + cmp \tmp, #2
  1359. + beq 1020f
  1360. + cmp \tmp, #3
  1361. + beq 1020f
  1362. +
  1363. + /* get masked status */
  1364. + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
  1365. + mov \irqnr, #(ARM_IRQ0_BASE + 31)
  1366. + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
  1367. + /* clear bits 8 and 9, and test */
  1368. + bics \irqstat, \irqstat, #0x300
  1369. + bne 1010f
  1370. +
  1371. + tst \tmp, #0x100
  1372. + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
  1373. + movne \irqnr, #(ARM_IRQ1_BASE + 31)
  1374. + @ Mask out the interrupts also present in PEND0 - see SW-5809
  1375. + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
  1376. + bicne \irqstat, #((1<<18) | (1<<19))
  1377. + bne 1010f
  1378. +
  1379. + tst \tmp, #0x200
  1380. + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
  1381. + movne \irqnr, #(ARM_IRQ2_BASE + 31)
  1382. + @ Mask out the interrupts also present in PEND0 - see SW-5809
  1383. + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
  1384. + bicne \irqstat, #((1<<30))
  1385. + beq 1020f
  1386. +
  1387. +1010:
  1388. + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
  1389. + @ N.B. CLZ is an ARM5 instruction.
  1390. + sub \tmp, \irqstat, #1
  1391. + eor \irqstat, \irqstat, \tmp
  1392. + clz \tmp, \irqstat
  1393. + sub \irqnr, \tmp
  1394. +
  1395. +1020: @ EQ will be set if no irqs pending
  1396. +
  1397. + .endm
  1398. +
  1399. + .macro test_for_ipi, irqnr, irqstat, base, tmp
  1400. + /* get core number */
  1401. + mrc p15, 0, \tmp, c0, c0, 5
  1402. + ubfx \tmp, \tmp, #0, #2
  1403. + /* get core's mailbox interrupt control */
  1404. + ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
  1405. + add \irqstat, \irqstat, \tmp, lsl #4
  1406. + ldr \tmp, [\irqstat]
  1407. + cmp \tmp, #0
  1408. + beq 1030f
  1409. + clz \tmp, \tmp
  1410. + rsb \irqnr, \tmp, #31
  1411. + mov \tmp, #1
  1412. + lsl \tmp, \irqnr
  1413. + str \tmp, [\irqstat] @ clear interrupt source
  1414. + dsb
  1415. +1030: @ EQ will be set if no irqs pending
  1416. + .endm
  1417. --- /dev/null
  1418. +++ b/arch/arm/mach-bcm2709/include/mach/io.h
  1419. @@ -0,0 +1,27 @@
  1420. +/*
  1421. + * arch/arm/mach-bcm2708/include/mach/io.h
  1422. + *
  1423. + * Copyright (C) 2003 ARM Limited
  1424. + *
  1425. + * This program is free software; you can redistribute it and/or modify
  1426. + * it under the terms of the GNU General Public License as published by
  1427. + * the Free Software Foundation; either version 2 of the License, or
  1428. + * (at your option) any later version.
  1429. + *
  1430. + * This program is distributed in the hope that it will be useful,
  1431. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1432. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1433. + * GNU General Public License for more details.
  1434. + *
  1435. + * You should have received a copy of the GNU General Public License
  1436. + * along with this program; if not, write to the Free Software
  1437. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  1438. + */
  1439. +#ifndef __ASM_ARM_ARCH_IO_H
  1440. +#define __ASM_ARM_ARCH_IO_H
  1441. +
  1442. +#define IO_SPACE_LIMIT 0xffffffff
  1443. +
  1444. +#define __io(a) __typesafe_io(a)
  1445. +
  1446. +#endif
  1447. --- /dev/null
  1448. +++ b/arch/arm/mach-bcm2709/include/mach/memory.h
  1449. @@ -0,0 +1,57 @@
  1450. +/*
  1451. + * arch/arm/mach-bcm2708/include/mach/memory.h
  1452. + *
  1453. + * Copyright (C) 2010 Broadcom
  1454. + *
  1455. + * This program is free software; you can redistribute it and/or modify
  1456. + * it under the terms of the GNU General Public License as published by
  1457. + * the Free Software Foundation; either version 2 of the License, or
  1458. + * (at your option) any later version.
  1459. + *
  1460. + * This program is distributed in the hope that it will be useful,
  1461. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1462. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1463. + * GNU General Public License for more details.
  1464. + *
  1465. + * You should have received a copy of the GNU General Public License
  1466. + * along with this program; if not, write to the Free Software
  1467. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  1468. + */
  1469. +#ifndef __ASM_ARCH_MEMORY_H
  1470. +#define __ASM_ARCH_MEMORY_H
  1471. +
  1472. +/* Memory overview:
  1473. +
  1474. + [ARMcore] <--virtual addr-->
  1475. + [ARMmmu] <--physical addr-->
  1476. + [GERTmap] <--bus add-->
  1477. + [VCperiph]
  1478. +
  1479. +*/
  1480. +
  1481. +/*
  1482. + * Physical DRAM offset.
  1483. + */
  1484. +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
  1485. +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
  1486. +
  1487. +#ifdef CONFIG_BCM2708_NOL2CACHE
  1488. + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
  1489. +#else
  1490. + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
  1491. +#endif
  1492. +
  1493. +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
  1494. + * will provide the offset into this area as well as setting the bits that
  1495. + * stop the L1 and L2 cache from being used
  1496. + *
  1497. + * WARNING: this only works because the ARM is given memory at a fixed location
  1498. + * (ARMMEM_OFFSET)
  1499. + */
  1500. +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
  1501. +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
  1502. +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
  1503. +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
  1504. +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
  1505. +
  1506. +#endif
  1507. --- /dev/null
  1508. +++ b/arch/arm/mach-bcm2709/include/mach/platform.h
  1509. @@ -0,0 +1,188 @@
  1510. +/*
  1511. + * arch/arm/mach-bcm2708/include/mach/platform.h
  1512. + *
  1513. + * Copyright (C) 2010 Broadcom
  1514. + *
  1515. + * This program is free software; you can redistribute it and/or modify
  1516. + * it under the terms of the GNU General Public License as published by
  1517. + * the Free Software Foundation; either version 2 of the License, or
  1518. + * (at your option) any later version.
  1519. + *
  1520. + * This program is distributed in the hope that it will be useful,
  1521. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1522. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1523. + * GNU General Public License for more details.
  1524. + *
  1525. + * You should have received a copy of the GNU General Public License
  1526. + * along with this program; if not, write to the Free Software
  1527. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  1528. + */
  1529. +
  1530. +#ifndef _BCM2708_PLATFORM_H
  1531. +#define _BCM2708_PLATFORM_H
  1532. +
  1533. +
  1534. +/* macros to get at IO space when running virtually */
  1535. +#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
  1536. +
  1537. +#define __io_address(n) IOMEM(IO_ADDRESS(n))
  1538. +
  1539. +
  1540. +/*
  1541. + * SDRAM
  1542. + */
  1543. +#define BCM2708_SDRAM_BASE 0x00000000
  1544. +
  1545. +/*
  1546. + * Logic expansion modules
  1547. + *
  1548. + */
  1549. +
  1550. +
  1551. +/* ------------------------------------------------------------------------
  1552. + * BCM2708 ARMCTRL Registers
  1553. + * ------------------------------------------------------------------------
  1554. + */
  1555. +
  1556. +#define HW_REGISTER_RW(addr) (addr)
  1557. +#define HW_REGISTER_RO(addr) (addr)
  1558. +
  1559. +/*
  1560. + * Definitions and addresses for the ARM CONTROL logic
  1561. + * This file is manually generated.
  1562. + */
  1563. +
  1564. +#define BCM2708_PERI_BASE 0x3F000000
  1565. +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
  1566. +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
  1567. +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
  1568. +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
  1569. +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
  1570. +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
  1571. +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
  1572. +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
  1573. +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
  1574. +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
  1575. +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
  1576. +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
  1577. +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
  1578. +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
  1579. +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
  1580. +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
  1581. +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
  1582. +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
  1583. +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
  1584. +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
  1585. +
  1586. +#define ARMCTRL_BASE (ARM_BASE + 0x000)
  1587. +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
  1588. +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
  1589. +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
  1590. +
  1591. +/*
  1592. + * Watchdog
  1593. + */
  1594. +#define PM_RSTC (PM_BASE+0x1c)
  1595. +#define PM_RSTS (PM_BASE+0x20)
  1596. +#define PM_WDOG (PM_BASE+0x24)
  1597. +
  1598. +#define PM_WDOG_RESET 0000000000
  1599. +#define PM_PASSWORD 0x5a000000
  1600. +#define PM_WDOG_TIME_SET 0x000fffff
  1601. +#define PM_RSTC_WRCFG_CLR 0xffffffcf
  1602. +#define PM_RSTC_WRCFG_SET 0x00000030
  1603. +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
  1604. +#define PM_RSTC_RESET 0x00000102
  1605. +
  1606. +#define PM_RSTS_HADPOR_SET 0x00001000
  1607. +#define PM_RSTS_HADSRH_SET 0x00000400
  1608. +#define PM_RSTS_HADSRF_SET 0x00000200
  1609. +#define PM_RSTS_HADSRQ_SET 0x00000100
  1610. +#define PM_RSTS_HADWRH_SET 0x00000040
  1611. +#define PM_RSTS_HADWRF_SET 0x00000020
  1612. +#define PM_RSTS_HADWRQ_SET 0x00000010
  1613. +#define PM_RSTS_HADDRH_SET 0x00000004
  1614. +#define PM_RSTS_HADDRF_SET 0x00000002
  1615. +#define PM_RSTS_HADDRQ_SET 0x00000001
  1616. +
  1617. +#define UART0_CLOCK 3000000
  1618. +
  1619. +#define ARM_LOCAL_BASE 0x40000000
  1620. +#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
  1621. +
  1622. +#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
  1623. +#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
  1624. +#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
  1625. +#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
  1626. +#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
  1627. +#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
  1628. +#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
  1629. +#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
  1630. +#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
  1631. +#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
  1632. +#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
  1633. +#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
  1634. +
  1635. +#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
  1636. +#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
  1637. +#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
  1638. +#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
  1639. +
  1640. +#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
  1641. +#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
  1642. +#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
  1643. +#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
  1644. +
  1645. +#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
  1646. +#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
  1647. +#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
  1648. +#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
  1649. +
  1650. +#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
  1651. +#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
  1652. +#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
  1653. +#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
  1654. +
  1655. +#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
  1656. +#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
  1657. +#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
  1658. +#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
  1659. +
  1660. +#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
  1661. +#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
  1662. +#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
  1663. +#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
  1664. +
  1665. +#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
  1666. +#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
  1667. +#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
  1668. +#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
  1669. +
  1670. +#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
  1671. +#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
  1672. +#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
  1673. +#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
  1674. +
  1675. +#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
  1676. +#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
  1677. +#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
  1678. +#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
  1679. +
  1680. +#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
  1681. +#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
  1682. +#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
  1683. +#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
  1684. +
  1685. +#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
  1686. +#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
  1687. +#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
  1688. +#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
  1689. +
  1690. +#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
  1691. +#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
  1692. +#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
  1693. +#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
  1694. +
  1695. +#endif
  1696. +
  1697. +/* END */
  1698. --- /dev/null
  1699. +++ b/arch/arm/mach-bcm2709/include/mach/system.h
  1700. @@ -0,0 +1,37 @@
  1701. +/*
  1702. + * arch/arm/mach-bcm2708/include/mach/system.h
  1703. + *
  1704. + * Copyright (C) 2010 Broadcom
  1705. + * Copyright (C) 2003 ARM Limited
  1706. + * Copyright (C) 2000 Deep Blue Solutions Ltd
  1707. + *
  1708. + * This program is free software; you can redistribute it and/or modify
  1709. + * it under the terms of the GNU General Public License as published by
  1710. + * the Free Software Foundation; either version 2 of the License, or
  1711. + * (at your option) any later version.
  1712. + *
  1713. + * This program is distributed in the hope that it will be useful,
  1714. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1715. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1716. + * GNU General Public License for more details.
  1717. + *
  1718. + * You should have received a copy of the GNU General Public License
  1719. + * along with this program; if not, write to the Free Software
  1720. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  1721. + */
  1722. +#ifndef __ASM_ARCH_SYSTEM_H
  1723. +#define __ASM_ARCH_SYSTEM_H
  1724. +
  1725. +#include <linux/io.h>
  1726. +#include <mach/platform.h>
  1727. +
  1728. +static inline void arch_idle(void)
  1729. +{
  1730. + /*
  1731. + * This should do all the clock switching
  1732. + * and wait for interrupt tricks
  1733. + */
  1734. + cpu_do_idle();
  1735. +}
  1736. +
  1737. +#endif
  1738. --- /dev/null
  1739. +++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h
  1740. @@ -0,0 +1,84 @@
  1741. +/*
  1742. + * arch/arm/mach-bcn2708/include/mach/uncompress.h
  1743. + *
  1744. + * Copyright (C) 2010 Broadcom
  1745. + * Copyright (C) 2003 ARM Limited
  1746. + *
  1747. + * This program is free software; you can redistribute it and/or modify
  1748. + * it under the terms of the GNU General Public License as published by
  1749. + * the Free Software Foundation; either version 2 of the License, or
  1750. + * (at your option) any later version.
  1751. + *
  1752. + * This program is distributed in the hope that it will be useful,
  1753. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1754. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1755. + * GNU General Public License for more details.
  1756. + *
  1757. + * You should have received a copy of the GNU General Public License
  1758. + * along with this program; if not, write to the Free Software
  1759. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  1760. + */
  1761. +
  1762. +#include <linux/io.h>
  1763. +#include <linux/amba/serial.h>
  1764. +#include <mach/platform.h>
  1765. +
  1766. +#define UART_BAUD 115200
  1767. +
  1768. +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
  1769. +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
  1770. +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
  1771. +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
  1772. +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
  1773. +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
  1774. +
  1775. +/*
  1776. + * This does not append a newline
  1777. + */
  1778. +static inline void putc(int c)
  1779. +{
  1780. + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
  1781. + barrier();
  1782. +
  1783. + __raw_writel(c, BCM2708_UART_DR);
  1784. +}
  1785. +
  1786. +static inline void flush(void)
  1787. +{
  1788. + int fr;
  1789. +
  1790. + do {
  1791. + fr = __raw_readl(BCM2708_UART_FR);
  1792. + barrier();
  1793. + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
  1794. +}
  1795. +
  1796. +static inline void arch_decomp_setup(void)
  1797. +{
  1798. + int temp, div, rem, frac;
  1799. +
  1800. + temp = 16 * UART_BAUD;
  1801. + div = UART0_CLOCK / temp;
  1802. + rem = UART0_CLOCK % temp;
  1803. + temp = (8 * rem) / UART_BAUD;
  1804. + frac = (temp >> 1) + (temp & 1);
  1805. +
  1806. + /* Make sure the UART is disabled before we start */
  1807. + __raw_writel(0, BCM2708_UART_CR);
  1808. +
  1809. + /* Set the baud rate */
  1810. + __raw_writel(div, BCM2708_UART_IBRD);
  1811. + __raw_writel(frac, BCM2708_UART_FBRD);
  1812. +
  1813. + /* Set the UART to 8n1, FIFO enabled */
  1814. + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
  1815. +
  1816. + /* Enable the UART */
  1817. + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
  1818. + BCM2708_UART_CR);
  1819. +}
  1820. +
  1821. +/*
  1822. + * nothing to do
  1823. + */
  1824. +#define arch_decomp_wdog()
  1825. --- /dev/null
  1826. +++ b/arch/arm/mach-bcm2709/include/mach/vc_mem.h
  1827. @@ -0,0 +1,35 @@
  1828. +/*****************************************************************************
  1829. +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
  1830. +*
  1831. +* Unless you and Broadcom execute a separate written software license
  1832. +* agreement governing use of this software, this software is licensed to you
  1833. +* under the terms of the GNU General Public License version 2, available at
  1834. +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
  1835. +*
  1836. +* Notwithstanding the above, under no circumstances may you combine this
  1837. +* software in any way with any other Broadcom software provided under a
  1838. +* license other than the GPL, without Broadcom's express prior written
  1839. +* consent.
  1840. +*****************************************************************************/
  1841. +
  1842. +#if !defined( VC_MEM_H )
  1843. +#define VC_MEM_H
  1844. +
  1845. +#include <linux/ioctl.h>
  1846. +
  1847. +#define VC_MEM_IOC_MAGIC 'v'
  1848. +
  1849. +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
  1850. +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
  1851. +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
  1852. +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
  1853. +
  1854. +#if defined( __KERNEL__ )
  1855. +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
  1856. +
  1857. +extern unsigned long mm_vc_mem_phys_addr;
  1858. +extern unsigned int mm_vc_mem_size;
  1859. +extern int vc_mem_get_current_size( void );
  1860. +#endif
  1861. +
  1862. +#endif /* VC_MEM_H */
  1863. --- /dev/null
  1864. +++ b/arch/arm/mach-bcm2709/include/mach/vmalloc.h
  1865. @@ -0,0 +1,20 @@
  1866. +/*
  1867. + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
  1868. + *
  1869. + * Copyright (C) 2010 Broadcom
  1870. + *
  1871. + * This program is free software; you can redistribute it and/or modify
  1872. + * it under the terms of the GNU General Public License as published by
  1873. + * the Free Software Foundation; either version 2 of the License, or
  1874. + * (at your option) any later version.
  1875. + *
  1876. + * This program is distributed in the hope that it will be useful,
  1877. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  1878. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  1879. + * GNU General Public License for more details.
  1880. + *
  1881. + * You should have received a copy of the GNU General Public License
  1882. + * along with this program; if not, write to the Free Software
  1883. + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  1884. + */
  1885. +#define VMALLOC_END (0xff000000)
  1886. --- /dev/null
  1887. +++ b/arch/arm/mach-bcm2709/vc_mem.c
  1888. @@ -0,0 +1,431 @@
  1889. +/*****************************************************************************
  1890. +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
  1891. +*
  1892. +* Unless you and Broadcom execute a separate written software license
  1893. +* agreement governing use of this software, this software is licensed to you
  1894. +* under the terms of the GNU General Public License version 2, available at
  1895. +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
  1896. +*
  1897. +* Notwithstanding the above, under no circumstances may you combine this
  1898. +* software in any way with any other Broadcom software provided under a
  1899. +* license other than the GPL, without Broadcom's express prior written
  1900. +* consent.
  1901. +*****************************************************************************/
  1902. +
  1903. +#include <linux/kernel.h>
  1904. +#include <linux/module.h>
  1905. +#include <linux/fs.h>
  1906. +#include <linux/device.h>
  1907. +#include <linux/cdev.h>
  1908. +#include <linux/mm.h>
  1909. +#include <linux/slab.h>
  1910. +#include <linux/debugfs.h>
  1911. +#include <asm/uaccess.h>
  1912. +#include <linux/dma-mapping.h>
  1913. +#include <linux/platform_data/mailbox-bcm2708.h>
  1914. +
  1915. +#ifdef CONFIG_ARCH_KONA
  1916. +#include <chal/chal_ipc.h>
  1917. +#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
  1918. +#else
  1919. +#include <csp/chal_ipc.h>
  1920. +#endif
  1921. +
  1922. +#include "mach/vc_mem.h"
  1923. +
  1924. +#define DRIVER_NAME "vc-mem"
  1925. +
  1926. +// Device (/dev) related variables
  1927. +static dev_t vc_mem_devnum = 0;
  1928. +static struct class *vc_mem_class = NULL;
  1929. +static struct cdev vc_mem_cdev;
  1930. +static int vc_mem_inited = 0;
  1931. +
  1932. +#ifdef CONFIG_DEBUG_FS
  1933. +static struct dentry *vc_mem_debugfs_entry;
  1934. +#endif
  1935. +
  1936. +/*
  1937. + * Videocore memory addresses and size
  1938. + *
  1939. + * Drivers that wish to know the videocore memory addresses and sizes should
  1940. + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
  1941. + * headers. This allows the other drivers to not be tied down to a a certain
  1942. + * address/size at compile time.
  1943. + *
  1944. + * In the future, the goal is to have the videocore memory virtual address and
  1945. + * size be calculated at boot time rather than at compile time. The decision of
  1946. + * where the videocore memory resides and its size would be in the hands of the
  1947. + * bootloader (and/or kernel). When that happens, the values of these variables
  1948. + * would be calculated and assigned in the init function.
  1949. + */
  1950. +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
  1951. +unsigned long mm_vc_mem_phys_addr = 0x00000000;
  1952. +unsigned int mm_vc_mem_size = 0;
  1953. +unsigned int mm_vc_mem_base = 0;
  1954. +
  1955. +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
  1956. +EXPORT_SYMBOL(mm_vc_mem_size);
  1957. +EXPORT_SYMBOL(mm_vc_mem_base);
  1958. +
  1959. +static uint phys_addr = 0;
  1960. +static uint mem_size = 0;
  1961. +static uint mem_base = 0;
  1962. +
  1963. +
  1964. +/****************************************************************************
  1965. +*
  1966. +* vc_mem_open
  1967. +*
  1968. +***************************************************************************/
  1969. +
  1970. +static int
  1971. +vc_mem_open(struct inode *inode, struct file *file)
  1972. +{
  1973. + (void) inode;
  1974. + (void) file;
  1975. +
  1976. + pr_debug("%s: called file = 0x%p\n", __func__, file);
  1977. +
  1978. + return 0;
  1979. +}
  1980. +
  1981. +/****************************************************************************
  1982. +*
  1983. +* vc_mem_release
  1984. +*
  1985. +***************************************************************************/
  1986. +
  1987. +static int
  1988. +vc_mem_release(struct inode *inode, struct file *file)
  1989. +{
  1990. + (void) inode;
  1991. + (void) file;
  1992. +
  1993. + pr_debug("%s: called file = 0x%p\n", __func__, file);
  1994. +
  1995. + return 0;
  1996. +}
  1997. +
  1998. +/****************************************************************************
  1999. +*
  2000. +* vc_mem_get_size
  2001. +*
  2002. +***************************************************************************/
  2003. +
  2004. +static void
  2005. +vc_mem_get_size(void)
  2006. +{
  2007. +}
  2008. +
  2009. +/****************************************************************************
  2010. +*
  2011. +* vc_mem_get_base
  2012. +*
  2013. +***************************************************************************/
  2014. +
  2015. +static void
  2016. +vc_mem_get_base(void)
  2017. +{
  2018. +}
  2019. +
  2020. +/****************************************************************************
  2021. +*
  2022. +* vc_mem_get_current_size
  2023. +*
  2024. +***************************************************************************/
  2025. +
  2026. +int
  2027. +vc_mem_get_current_size(void)
  2028. +{
  2029. + return mm_vc_mem_size;
  2030. +}
  2031. +
  2032. +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
  2033. +
  2034. +/****************************************************************************
  2035. +*
  2036. +* vc_mem_ioctl
  2037. +*
  2038. +***************************************************************************/
  2039. +
  2040. +static long
  2041. +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  2042. +{
  2043. + int rc = 0;
  2044. +
  2045. + (void) cmd;
  2046. + (void) arg;
  2047. +
  2048. + pr_debug("%s: called file = 0x%p\n", __func__, file);
  2049. +
  2050. + switch (cmd) {
  2051. + case VC_MEM_IOC_MEM_PHYS_ADDR:
  2052. + {
  2053. + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
  2054. + __func__, (void *) mm_vc_mem_phys_addr);
  2055. +
  2056. + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
  2057. + sizeof (mm_vc_mem_phys_addr)) != 0) {
  2058. + rc = -EFAULT;
  2059. + }
  2060. + break;
  2061. + }
  2062. + case VC_MEM_IOC_MEM_SIZE:
  2063. + {
  2064. + // Get the videocore memory size first
  2065. + vc_mem_get_size();
  2066. +
  2067. + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
  2068. + mm_vc_mem_size);
  2069. +
  2070. + if (copy_to_user((void *) arg, &mm_vc_mem_size,
  2071. + sizeof (mm_vc_mem_size)) != 0) {
  2072. + rc = -EFAULT;
  2073. + }
  2074. + break;
  2075. + }
  2076. + case VC_MEM_IOC_MEM_BASE:
  2077. + {
  2078. + // Get the videocore memory base
  2079. + vc_mem_get_base();
  2080. +
  2081. + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
  2082. + mm_vc_mem_base);
  2083. +
  2084. + if (copy_to_user((void *) arg, &mm_vc_mem_base,
  2085. + sizeof (mm_vc_mem_base)) != 0) {
  2086. + rc = -EFAULT;
  2087. + }
  2088. + break;
  2089. + }
  2090. + case VC_MEM_IOC_MEM_LOAD:
  2091. + {
  2092. + // Get the videocore memory base
  2093. + vc_mem_get_base();
  2094. +
  2095. + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
  2096. + mm_vc_mem_base);
  2097. +
  2098. + if (copy_to_user((void *) arg, &mm_vc_mem_base,
  2099. + sizeof (mm_vc_mem_base)) != 0) {
  2100. + rc = -EFAULT;
  2101. + }
  2102. + break;
  2103. + }
  2104. + default:
  2105. + {
  2106. + return -ENOTTY;
  2107. + }
  2108. + }
  2109. + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
  2110. +
  2111. + return rc;
  2112. +}
  2113. +
  2114. +/****************************************************************************
  2115. +*
  2116. +* vc_mem_mmap
  2117. +*
  2118. +***************************************************************************/
  2119. +
  2120. +static int
  2121. +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
  2122. +{
  2123. + int rc = 0;
  2124. + unsigned long length = vma->vm_end - vma->vm_start;
  2125. + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
  2126. +
  2127. + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
  2128. + __func__, (long) vma->vm_start, (long) vma->vm_end,
  2129. + (long) vma->vm_pgoff);
  2130. +
  2131. + if (offset + length > mm_vc_mem_size) {
  2132. + pr_err("%s: length %ld is too big\n", __func__, length);
  2133. + return -EINVAL;
  2134. + }
  2135. + // Do not cache the memory map
  2136. + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  2137. +
  2138. + rc = remap_pfn_range(vma, vma->vm_start,
  2139. + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
  2140. + vma->vm_pgoff, length, vma->vm_page_prot);
  2141. + if (rc != 0) {
  2142. + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
  2143. + }
  2144. +
  2145. + return rc;
  2146. +}
  2147. +
  2148. +/****************************************************************************
  2149. +*
  2150. +* File Operations for the driver.
  2151. +*
  2152. +***************************************************************************/
  2153. +
  2154. +static const struct file_operations vc_mem_fops = {
  2155. + .owner = THIS_MODULE,
  2156. + .open = vc_mem_open,
  2157. + .release = vc_mem_release,
  2158. + .unlocked_ioctl = vc_mem_ioctl,
  2159. + .mmap = vc_mem_mmap,
  2160. +};
  2161. +
  2162. +#ifdef CONFIG_DEBUG_FS
  2163. +static void vc_mem_debugfs_deinit(void)
  2164. +{
  2165. + debugfs_remove_recursive(vc_mem_debugfs_entry);
  2166. + vc_mem_debugfs_entry = NULL;
  2167. +}
  2168. +
  2169. +
  2170. +static int vc_mem_debugfs_init(
  2171. + struct device *dev)
  2172. +{
  2173. + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
  2174. + if (!vc_mem_debugfs_entry) {
  2175. + dev_warn(dev, "could not create debugfs entry\n");
  2176. + return -EFAULT;
  2177. + }
  2178. +
  2179. + if (!debugfs_create_x32("vc_mem_phys_addr",
  2180. + 0444,
  2181. + vc_mem_debugfs_entry,
  2182. + (u32 *)&mm_vc_mem_phys_addr)) {
  2183. + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
  2184. + __func__);
  2185. + goto fail;
  2186. + }
  2187. +
  2188. + if (!debugfs_create_x32("vc_mem_size",
  2189. + 0444,
  2190. + vc_mem_debugfs_entry,
  2191. + (u32 *)&mm_vc_mem_size)) {
  2192. + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
  2193. + __func__);
  2194. + goto fail;
  2195. + }
  2196. +
  2197. + if (!debugfs_create_x32("vc_mem_base",
  2198. + 0444,
  2199. + vc_mem_debugfs_entry,
  2200. + (u32 *)&mm_vc_mem_base)) {
  2201. + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
  2202. + __func__);
  2203. + goto fail;
  2204. + }
  2205. +
  2206. + return 0;
  2207. +
  2208. +fail:
  2209. + vc_mem_debugfs_deinit();
  2210. + return -EFAULT;
  2211. +}
  2212. +
  2213. +#endif /* CONFIG_DEBUG_FS */
  2214. +
  2215. +
  2216. +/****************************************************************************
  2217. +*
  2218. +* vc_mem_init
  2219. +*
  2220. +***************************************************************************/
  2221. +
  2222. +static int __init
  2223. +vc_mem_init(void)
  2224. +{
  2225. + int rc = -EFAULT;
  2226. + struct device *dev;
  2227. +
  2228. + pr_debug("%s: called\n", __func__);
  2229. +
  2230. + mm_vc_mem_phys_addr = phys_addr;
  2231. + mm_vc_mem_size = mem_size;
  2232. + mm_vc_mem_base = mem_base;
  2233. +
  2234. + vc_mem_get_size();
  2235. +
  2236. + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
  2237. + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
  2238. +
  2239. + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
  2240. + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
  2241. + __func__, rc);
  2242. + goto out_err;
  2243. + }
  2244. +
  2245. + cdev_init(&vc_mem_cdev, &vc_mem_fops);
  2246. + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
  2247. + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
  2248. + goto out_unregister;
  2249. + }
  2250. +
  2251. + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
  2252. + if (IS_ERR(vc_mem_class)) {
  2253. + rc = PTR_ERR(vc_mem_class);
  2254. + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
  2255. + goto out_cdev_del;
  2256. + }
  2257. +
  2258. + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
  2259. + DRIVER_NAME);
  2260. + if (IS_ERR(dev)) {
  2261. + rc = PTR_ERR(dev);
  2262. + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
  2263. + goto out_class_destroy;
  2264. + }
  2265. +
  2266. +#ifdef CONFIG_DEBUG_FS
  2267. + /* don't fail if the debug entries cannot be created */
  2268. + vc_mem_debugfs_init(dev);
  2269. +#endif
  2270. +
  2271. + vc_mem_inited = 1;
  2272. + return 0;
  2273. +
  2274. + device_destroy(vc_mem_class, vc_mem_devnum);
  2275. +
  2276. + out_class_destroy:
  2277. + class_destroy(vc_mem_class);
  2278. + vc_mem_class = NULL;
  2279. +
  2280. + out_cdev_del:
  2281. + cdev_del(&vc_mem_cdev);
  2282. +
  2283. + out_unregister:
  2284. + unregister_chrdev_region(vc_mem_devnum, 1);
  2285. +
  2286. + out_err:
  2287. + return -1;
  2288. +}
  2289. +
  2290. +/****************************************************************************
  2291. +*
  2292. +* vc_mem_exit
  2293. +*
  2294. +***************************************************************************/
  2295. +
  2296. +static void __exit
  2297. +vc_mem_exit(void)
  2298. +{
  2299. + pr_debug("%s: called\n", __func__);
  2300. +
  2301. + if (vc_mem_inited) {
  2302. +#if CONFIG_DEBUG_FS
  2303. + vc_mem_debugfs_deinit();
  2304. +#endif
  2305. + device_destroy(vc_mem_class, vc_mem_devnum);
  2306. + class_destroy(vc_mem_class);
  2307. + cdev_del(&vc_mem_cdev);
  2308. + unregister_chrdev_region(vc_mem_devnum, 1);
  2309. + }
  2310. +}
  2311. +
  2312. +module_init(vc_mem_init);
  2313. +module_exit(vc_mem_exit);
  2314. +MODULE_LICENSE("GPL");
  2315. +MODULE_AUTHOR("Broadcom Corporation");
  2316. +
  2317. +module_param(phys_addr, uint, 0644);
  2318. +module_param(mem_size, uint, 0644);
  2319. +module_param(mem_base, uint, 0644);
  2320. --- a/arch/arm/mm/Kconfig
  2321. +++ b/arch/arm/mm/Kconfig
  2322. @@ -358,7 +358,7 @@ config CPU_PJ4B
  2323. # ARMv6
  2324. config CPU_V6
  2325. - bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
  2326. + bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708)
  2327. select CPU_32v6
  2328. select CPU_ABRT_EV6
  2329. select CPU_CACHE_V6
  2330. --- a/arch/arm/mm/proc-v6.S
  2331. +++ b/arch/arm/mm/proc-v6.S
  2332. @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
  2333. *
  2334. * IRQs are already disabled.
  2335. */
  2336. +
  2337. +/* See jira SW-5991 for details of this workaround */
  2338. ENTRY(cpu_v6_do_idle)
  2339. - mov r1, #0
  2340. - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
  2341. - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
  2342. + .align 5
  2343. + mov r1, #2
  2344. +1: subs r1, #1
  2345. + nop
  2346. + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
  2347. + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
  2348. + nop
  2349. + nop
  2350. + nop
  2351. + bne 1b
  2352. ret lr
  2353. ENTRY(cpu_v6_dcache_clean_area)
  2354. --- a/arch/arm/mm/proc-v7.S
  2355. +++ b/arch/arm/mm/proc-v7.S
  2356. @@ -480,6 +480,7 @@ __errata_finish:
  2357. orr r0, r0, r6 @ set them
  2358. THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
  2359. ret lr @ return to head.S:__ret
  2360. + .space 256
  2361. ENDPROC(__v7_setup)
  2362. .align 2
  2363. --- a/arch/arm/tools/mach-types
  2364. +++ b/arch/arm/tools/mach-types
  2365. @@ -522,6 +522,8 @@ torbreck MACH_TORBRECK TORBRECK 3090
  2366. prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
  2367. paz00 MACH_PAZ00 PAZ00 3128
  2368. acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
  2369. +bcm2708 MACH_BCM2708 BCM2708 3138
  2370. +bcm2709 MACH_BCM2709 BCM2709 3139
  2371. ag5evm MACH_AG5EVM AG5EVM 3189
  2372. ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
  2373. wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
  2374. --- a/drivers/clocksource/Makefile
  2375. +++ b/drivers/clocksource/Makefile
  2376. @@ -19,7 +19,7 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += noma
  2377. obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
  2378. obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
  2379. obj-$(CONFIG_ORION_TIMER) += time-orion.o
  2380. -obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
  2381. +obj-$(CONFIG_ARCH_BCM2835)$(CONFIG_ARCH_BCM2708) += bcm2835_timer.o
  2382. obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o
  2383. obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o
  2384. obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
  2385. --- a/drivers/irqchip/Makefile
  2386. +++ b/drivers/irqchip/Makefile
  2387. @@ -2,6 +2,9 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
  2388. obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
  2389. obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
  2390. +obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o
  2391. +obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2835.o
  2392. +obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o
  2393. obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
  2394. obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
  2395. obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
  2396. --- a/include/linux/mmc/host.h
  2397. +++ b/include/linux/mmc/host.h
  2398. @@ -289,6 +289,7 @@ struct mmc_host {
  2399. #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
  2400. #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
  2401. #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */
  2402. +#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
  2403. mmc_pm_flag_t pm_caps; /* supported pm features */