0335-drm-vc4-Add-support-for-gamma-ramps.patch 4.3 KB

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  1. From 716125d6733c9722b238f6d230579ead67a616bf Mon Sep 17 00:00:00 2001
  2. From: Eric Anholt <eric@anholt.net>
  3. Date: Thu, 31 Mar 2016 18:38:20 -0700
  4. Subject: [PATCH] drm/vc4: Add support for gamma ramps.
  5. We could possibly save a bit of power by not requesting gamma
  6. conversion when the ramp happens to be 1:1, but at least if all the
  7. CRTCs are off the SRAM will be disabled.
  8. This should fix brightness sliders in a lot of fullscreen games.
  9. Signed-off-by: Eric Anholt <eric@anholt.net>
  10. (cherry picked from commit e582b6c7e7f9d0b1e30e8017e4082d3a9ede3310)
  11. ---
  12. drivers/gpu/drm/vc4/vc4_crtc.c | 58 ++++++++++++++++++++++++++++++++++++++++++
  13. drivers/gpu/drm/vc4/vc4_regs.h | 6 +++++
  14. 2 files changed, 64 insertions(+)
  15. --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  16. +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  17. @@ -49,6 +49,10 @@ struct vc4_crtc {
  18. /* Which HVS channel we're using for our CRTC. */
  19. int channel;
  20. + u8 lut_r[256];
  21. + u8 lut_g[256];
  22. + u8 lut_b[256];
  23. +
  24. struct drm_pending_vblank_event *event;
  25. };
  26. @@ -147,6 +151,46 @@ static void vc4_crtc_destroy(struct drm_
  27. drm_crtc_cleanup(crtc);
  28. }
  29. +static void
  30. +vc4_crtc_lut_load(struct drm_crtc *crtc)
  31. +{
  32. + struct drm_device *dev = crtc->dev;
  33. + struct vc4_dev *vc4 = to_vc4_dev(dev);
  34. + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  35. + u32 i;
  36. +
  37. + /* The LUT memory is laid out with each HVS channel in order,
  38. + * each of which takes 256 writes for R, 256 for G, then 256
  39. + * for B.
  40. + */
  41. + HVS_WRITE(SCALER_GAMADDR,
  42. + SCALER_GAMADDR_AUTOINC |
  43. + (vc4_crtc->channel * 3 * crtc->gamma_size));
  44. +
  45. + for (i = 0; i < crtc->gamma_size; i++)
  46. + HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
  47. + for (i = 0; i < crtc->gamma_size; i++)
  48. + HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
  49. + for (i = 0; i < crtc->gamma_size; i++)
  50. + HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
  51. +}
  52. +
  53. +static void
  54. +vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
  55. + uint32_t start, uint32_t size)
  56. +{
  57. + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  58. + u32 i;
  59. +
  60. + for (i = start; i < start + size; i++) {
  61. + vc4_crtc->lut_r[i] = r[i] >> 8;
  62. + vc4_crtc->lut_g[i] = g[i] >> 8;
  63. + vc4_crtc->lut_b[i] = b[i] >> 8;
  64. + }
  65. +
  66. + vc4_crtc_lut_load(crtc);
  67. +}
  68. +
  69. static u32 vc4_get_fifo_full_level(u32 format)
  70. {
  71. static const u32 fifo_len_bytes = 64;
  72. @@ -260,8 +304,14 @@ static void vc4_crtc_mode_set_nofb(struc
  73. HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
  74. SCALER_DISPBKGND_AUTOHS |
  75. + SCALER_DISPBKGND_GAMMA |
  76. (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
  77. + /* Reload the LUT, since the SRAMs would have been disabled if
  78. + * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
  79. + */
  80. + vc4_crtc_lut_load(crtc);
  81. +
  82. if (debug_dump_regs) {
  83. DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
  84. vc4_crtc_dump_regs(vc4_crtc);
  85. @@ -613,6 +663,7 @@ static const struct drm_crtc_funcs vc4_c
  86. .reset = drm_atomic_helper_crtc_reset,
  87. .atomic_duplicate_state = vc4_crtc_duplicate_state,
  88. .atomic_destroy_state = vc4_crtc_destroy_state,
  89. + .gamma_set = vc4_crtc_gamma_set,
  90. };
  91. static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
  92. @@ -731,6 +782,7 @@ static int vc4_crtc_bind(struct device *
  93. primary_plane->crtc = crtc;
  94. vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc;
  95. vc4_crtc->channel = vc4_crtc->data->hvs_channel;
  96. + drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
  97. /* Set up some arbitrary number of planes. We're not limited
  98. * by a set number of physical registers, just the space in
  99. @@ -771,6 +823,12 @@ static int vc4_crtc_bind(struct device *
  100. vc4_set_crtc_possible_masks(drm, crtc);
  101. + for (i = 0; i < crtc->gamma_size; i++) {
  102. + vc4_crtc->lut_r[i] = i;
  103. + vc4_crtc->lut_g[i] = i;
  104. + vc4_crtc->lut_b[i] = i;
  105. + }
  106. +
  107. platform_set_drvdata(pdev, vc4_crtc);
  108. return 0;
  109. --- a/drivers/gpu/drm/vc4/vc4_regs.h
  110. +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  111. @@ -390,6 +390,12 @@
  112. #define SCALER_DISPBASE2 0x0000006c
  113. #define SCALER_DISPALPHA2 0x00000070
  114. #define SCALER_GAMADDR 0x00000078
  115. +# define SCALER_GAMADDR_AUTOINC BIT(31)
  116. +/* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
  117. + * enabled.
  118. + */
  119. +# define SCALER_GAMADDR_SRAMENB BIT(30)
  120. +
  121. #define SCALER_GAMDATA 0x000000e0
  122. #define SCALER_DLIST_START 0x00002000
  123. #define SCALER_DLIST_SIZE 0x00004000