cns3xxx_fiq.S 1.9 KB

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  1. /*
  2. * Copyright (C) 2012 Gateworks Corporation
  3. * Chris Lang <clang@gateworks.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <linux/linkage.h>
  10. #include <asm/assembler.h>
  11. #include <asm/asm-offsets.h>
  12. #define D_CACHE_LINE_SIZE 32
  13. .text
  14. /*
  15. * R8 - DMA Start Address
  16. * R9 - DMA Length
  17. * R10 - DMA Direction
  18. * R11 - DMA type
  19. * R12 - fiq_buffer Address
  20. */
  21. .global cns3xxx_fiq_end
  22. ENTRY(cns3xxx_fiq_start)
  23. str r8, [r13]
  24. ldmia r12, {r8, r9, r10}
  25. and r11, r10, #0x3000000
  26. and r10, r10, #0xff
  27. teq r11, #0x1000000
  28. beq cns3xxx_dma_map_area
  29. teq r11, #0x2000000
  30. beq cns3xxx_dma_unmap_area
  31. /* fall through */
  32. cns3xxx_dma_flush_range:
  33. bic r8, r8, #D_CACHE_LINE_SIZE - 1
  34. 1:
  35. mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line
  36. add r8, r8, #D_CACHE_LINE_SIZE
  37. cmp r8, r9
  38. blo 1b
  39. /* fall through */
  40. cns3xxx_fiq_exit:
  41. mov r8, #0
  42. str r8, [r12, #8]
  43. mcr p15, 0, r8, c7, c10, 4 @ drain write buffer
  44. subs pc, lr, #4
  45. cns3xxx_dma_map_area:
  46. add r9, r9, r8
  47. teq r10, #DMA_FROM_DEVICE
  48. beq cns3xxx_dma_inv_range
  49. teq r10, #DMA_TO_DEVICE
  50. bne cns3xxx_dma_flush_range
  51. /* fall through */
  52. cns3xxx_dma_clean_range:
  53. bic r8, r8, #D_CACHE_LINE_SIZE - 1
  54. 1:
  55. mcr p15, 0, r8, c7, c10, 1 @ clean D line
  56. add r8, r8, #D_CACHE_LINE_SIZE
  57. cmp r8, r9
  58. blo 1b
  59. b cns3xxx_fiq_exit
  60. cns3xxx_dma_unmap_area:
  61. add r9, r9, r8
  62. teq r10, #DMA_TO_DEVICE
  63. beq cns3xxx_fiq_exit
  64. /* fall through */
  65. cns3xxx_dma_inv_range:
  66. tst r8, #D_CACHE_LINE_SIZE - 1
  67. bic r8, r8, #D_CACHE_LINE_SIZE - 1
  68. mcrne p15, 0, r8, c7, c10, 1 @ clean D line
  69. tst r9, #D_CACHE_LINE_SIZE - 1
  70. bic r9, r9, #D_CACHE_LINE_SIZE - 1
  71. mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line
  72. 1:
  73. mcr p15, 0, r8, c7, c6, 1 @ invalidate D line
  74. add r8, r8, #D_CACHE_LINE_SIZE
  75. cmp r8, r9
  76. blo 1b
  77. b cns3xxx_fiq_exit
  78. cns3xxx_fiq_end: