ar8327.h 12 KB

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  1. /*
  2. * ar8327.h: AR8216 switch driver
  3. *
  4. * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #ifndef __AR8327_H
  17. #define __AR8327_H
  18. #define AR8327_NUM_PORTS 7
  19. #define AR8327_NUM_LEDS 15
  20. #define AR8327_PORTS_ALL 0x7f
  21. #define AR8327_NUM_LED_CTRL_REGS 4
  22. #define AR8327_REG_MASK 0x000
  23. #define AR8327_REG_PAD0_MODE 0x004
  24. #define AR8327_REG_PAD5_MODE 0x008
  25. #define AR8327_REG_PAD6_MODE 0x00c
  26. #define AR8327_PAD_MAC_MII_RXCLK_SEL BIT(0)
  27. #define AR8327_PAD_MAC_MII_TXCLK_SEL BIT(1)
  28. #define AR8327_PAD_MAC_MII_EN BIT(2)
  29. #define AR8327_PAD_MAC_GMII_RXCLK_SEL BIT(4)
  30. #define AR8327_PAD_MAC_GMII_TXCLK_SEL BIT(5)
  31. #define AR8327_PAD_MAC_GMII_EN BIT(6)
  32. #define AR8327_PAD_SGMII_EN BIT(7)
  33. #define AR8327_PAD_PHY_MII_RXCLK_SEL BIT(8)
  34. #define AR8327_PAD_PHY_MII_TXCLK_SEL BIT(9)
  35. #define AR8327_PAD_PHY_MII_EN BIT(10)
  36. #define AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL BIT(11)
  37. #define AR8327_PAD_PHY_GMII_RXCLK_SEL BIT(12)
  38. #define AR8327_PAD_PHY_GMII_TXCLK_SEL BIT(13)
  39. #define AR8327_PAD_PHY_GMII_EN BIT(14)
  40. #define AR8327_PAD_PHYX_GMII_EN BIT(16)
  41. #define AR8327_PAD_PHYX_RGMII_EN BIT(17)
  42. #define AR8327_PAD_PHYX_MII_EN BIT(18)
  43. #define AR8327_PAD_SGMII_DELAY_EN BIT(19)
  44. #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL BITS(20, 2)
  45. #define AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S 20
  46. #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL BITS(22, 2)
  47. #define AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S 22
  48. #define AR8327_PAD_RGMII_RXCLK_DELAY_EN BIT(24)
  49. #define AR8327_PAD_RGMII_TXCLK_DELAY_EN BIT(25)
  50. #define AR8327_PAD_RGMII_EN BIT(26)
  51. #define AR8327_REG_POWER_ON_STRIP 0x010
  52. #define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31)
  53. #define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24)
  54. #define AR8327_POWER_ON_STRIP_SERDES_AEN BIT(7)
  55. #define AR8327_REG_INT_STATUS0 0x020
  56. #define AR8327_INT0_VT_DONE BIT(20)
  57. #define AR8327_REG_INT_STATUS1 0x024
  58. #define AR8327_REG_INT_MASK0 0x028
  59. #define AR8327_REG_INT_MASK1 0x02c
  60. #define AR8327_REG_MODULE_EN 0x030
  61. #define AR8327_MODULE_EN_MIB BIT(0)
  62. #define AR8327_REG_MIB_FUNC 0x034
  63. #define AR8327_MIB_CPU_KEEP BIT(20)
  64. #define AR8327_REG_SERVICE_TAG 0x048
  65. #define AR8327_REG_LED_CTRL(_i) (0x050 + (_i) * 4)
  66. #define AR8327_REG_LED_CTRL0 0x050
  67. #define AR8327_REG_LED_CTRL1 0x054
  68. #define AR8327_REG_LED_CTRL2 0x058
  69. #define AR8327_REG_LED_CTRL3 0x05c
  70. #define AR8327_REG_MAC_ADDR0 0x060
  71. #define AR8327_REG_MAC_ADDR1 0x064
  72. #define AR8327_REG_MAX_FRAME_SIZE 0x078
  73. #define AR8327_MAX_FRAME_SIZE_MTU BITS(0, 14)
  74. #define AR8327_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
  75. #define AR8327_PORT_STATUS_TXFLOW_AUTO BIT(10)
  76. #define AR8327_PORT_STATUS_RXFLOW_AUTO BIT(11)
  77. #define AR8327_REG_HEADER_CTRL 0x098
  78. #define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
  79. #define AR8327_REG_SGMII_CTRL 0x0e0
  80. #define AR8327_SGMII_CTRL_EN_PLL BIT(1)
  81. #define AR8327_SGMII_CTRL_EN_RX BIT(2)
  82. #define AR8327_SGMII_CTRL_EN_TX BIT(3)
  83. #define AR8327_REG_EEE_CTRL 0x100
  84. #define AR8327_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
  85. #define AR8327_REG_FRAME_ACK_CTRL0 0x210
  86. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN0 BIT(0)
  87. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN0 BIT(1)
  88. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN0 BIT(2)
  89. #define AR8327_FRAME_ACK_CTRL_EAPOL_EN0 BIT(3)
  90. #define AR8327_FRAME_ACK_CTRL_DHCP_EN0 BIT(4)
  91. #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN0 BIT(5)
  92. #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN0 BIT(6)
  93. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN1 BIT(8)
  94. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN1 BIT(9)
  95. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN1 BIT(10)
  96. #define AR8327_FRAME_ACK_CTRL_EAPOL_EN1 BIT(11)
  97. #define AR8327_FRAME_ACK_CTRL_DHCP_EN1 BIT(12)
  98. #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN1 BIT(13)
  99. #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN1 BIT(14)
  100. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN2 BIT(16)
  101. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN2 BIT(17)
  102. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN2 BIT(18)
  103. #define AR8327_FRAME_ACK_CTRL_EAPOL_EN2 BIT(19)
  104. #define AR8327_FRAME_ACK_CTRL_DHCP_EN2 BIT(20)
  105. #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN2 BIT(21)
  106. #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN2 BIT(22)
  107. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN3 BIT(24)
  108. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN3 BIT(25)
  109. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN3 BIT(26)
  110. #define AR8327_FRAME_ACK_CTRL_EAPOL_EN3 BIT(27)
  111. #define AR8327_FRAME_ACK_CTRL_DHCP_EN3 BIT(28)
  112. #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN3 BIT(29)
  113. #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN3 BIT(30)
  114. #define AR8327_REG_FRAME_ACK_CTRL1 0x214
  115. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN4 BIT(0)
  116. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN4 BIT(1)
  117. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN4 BIT(2)
  118. #define AR8327_FRAME_ACK_CTRL_EAPOL_EN4 BIT(3)
  119. #define AR8327_FRAME_ACK_CTRL_DHCP_EN4 BIT(4)
  120. #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN4 BIT(5)
  121. #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN4 BIT(6)
  122. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN5 BIT(8)
  123. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN5 BIT(9)
  124. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN5 BIT(10)
  125. #define AR8327_FRAME_ACK_CTRL_EAPOL_EN5 BIT(11)
  126. #define AR8327_FRAME_ACK_CTRL_DHCP_EN5 BIT(12)
  127. #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN5 BIT(13)
  128. #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN5 BIT(14)
  129. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD_EN6 BIT(16)
  130. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN_EN6 BIT(17)
  131. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE_EN6 BIT(18)
  132. #define AR8327_FRAME_ACK_CTRL_EAPOL_EN6 BIT(19)
  133. #define AR8327_FRAME_ACK_CTRL_DHCP_EN6 BIT(20)
  134. #define AR8327_FRAME_ACK_CTRL_ARP_ACK_EN6 BIT(21)
  135. #define AR8327_FRAME_ACK_CTRL_ARP_REQ_EN6 BIT(22)
  136. #define AR8327_FRAME_ACK_CTRL_IGMP_V3_EN BIT(24)
  137. #define AR8327_FRAME_ACK_CTRL_PPPOE_EN BIT(25)
  138. #define AR8327_REG_FRAME_ACK_CTRL(_i) (0x210 + ((_i) / 4) * 0x4)
  139. #define AR8327_FRAME_ACK_CTRL_IGMP_MLD BIT(0)
  140. #define AR8327_FRAME_ACK_CTRL_IGMP_JOIN BIT(1)
  141. #define AR8327_FRAME_ACK_CTRL_IGMP_LEAVE BIT(2)
  142. #define AR8327_FRAME_ACK_CTRL_EAPOL BIT(3)
  143. #define AR8327_FRAME_ACK_CTRL_DHCP BIT(4)
  144. #define AR8327_FRAME_ACK_CTRL_ARP_ACK BIT(5)
  145. #define AR8327_FRAME_ACK_CTRL_ARP_REQ BIT(6)
  146. #define AR8327_FRAME_ACK_CTRL_S(_i) (((_i) % 4) * 8)
  147. #define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
  148. #define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12)
  149. #define AR8327_PORT_VLAN0_DEF_SVID_S 0
  150. #define AR8327_PORT_VLAN0_DEF_CVID BITS(16, 12)
  151. #define AR8327_PORT_VLAN0_DEF_CVID_S 16
  152. #define AR8327_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
  153. #define AR8327_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
  154. #define AR8327_PORT_VLAN1_OUT_MODE BITS(12, 2)
  155. #define AR8327_PORT_VLAN1_OUT_MODE_S 12
  156. #define AR8327_PORT_VLAN1_OUT_MODE_UNMOD 0
  157. #define AR8327_PORT_VLAN1_OUT_MODE_UNTAG 1
  158. #define AR8327_PORT_VLAN1_OUT_MODE_TAG 2
  159. #define AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH 3
  160. #define AR8327_REG_ATU_DATA0 0x600
  161. #define AR8327_ATU_ADDR0 BITS(0, 8)
  162. #define AR8327_ATU_ADDR0_S 0
  163. #define AR8327_ATU_ADDR1 BITS(8, 8)
  164. #define AR8327_ATU_ADDR1_S 8
  165. #define AR8327_ATU_ADDR2 BITS(16, 8)
  166. #define AR8327_ATU_ADDR2_S 16
  167. #define AR8327_ATU_ADDR3 BITS(24, 8)
  168. #define AR8327_ATU_ADDR3_S 24
  169. #define AR8327_REG_ATU_DATA1 0x604
  170. #define AR8327_ATU_ADDR4 BITS(0, 8)
  171. #define AR8327_ATU_ADDR4_S 0
  172. #define AR8327_ATU_ADDR5 BITS(8, 8)
  173. #define AR8327_ATU_ADDR5_S 8
  174. #define AR8327_ATU_PORTS BITS(16, 7)
  175. #define AR8327_ATU_PORT0 BIT(16)
  176. #define AR8327_ATU_PORT1 BIT(17)
  177. #define AR8327_ATU_PORT2 BIT(18)
  178. #define AR8327_ATU_PORT3 BIT(19)
  179. #define AR8327_ATU_PORT4 BIT(20)
  180. #define AR8327_ATU_PORT5 BIT(21)
  181. #define AR8327_ATU_PORT6 BIT(22)
  182. #define AR8327_REG_ATU_DATA2 0x608
  183. #define AR8327_ATU_STATUS BITS(0, 4)
  184. #define AR8327_REG_ATU_FUNC 0x60c
  185. #define AR8327_ATU_FUNC_OP BITS(0, 4)
  186. #define AR8327_ATU_FUNC_OP_NOOP 0x0
  187. #define AR8327_ATU_FUNC_OP_FLUSH 0x1
  188. #define AR8327_ATU_FUNC_OP_LOAD 0x2
  189. #define AR8327_ATU_FUNC_OP_PURGE 0x3
  190. #define AR8327_ATU_FUNC_OP_FLUSH_UNLOCKED 0x4
  191. #define AR8327_ATU_FUNC_OP_FLUSH_PORT 0x5
  192. #define AR8327_ATU_FUNC_OP_GET_NEXT 0x6
  193. #define AR8327_ATU_FUNC_OP_SEARCH_MAC 0x7
  194. #define AR8327_ATU_FUNC_OP_CHANGE_TRUNK 0x8
  195. #define AR8327_ATU_PORT_NUM BITS(8, 4)
  196. #define AR8327_ATU_PORT_NUM_S 8
  197. #define AR8327_ATU_FUNC_BUSY BIT(31)
  198. #define AR8327_REG_VTU_FUNC0 0x0610
  199. #define AR8327_VTU_FUNC0_EG_MODE BITS(4, 14)
  200. #define AR8327_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
  201. #define AR8327_VTU_FUNC0_EG_MODE_KEEP 0
  202. #define AR8327_VTU_FUNC0_EG_MODE_UNTAG 1
  203. #define AR8327_VTU_FUNC0_EG_MODE_TAG 2
  204. #define AR8327_VTU_FUNC0_EG_MODE_NOT 3
  205. #define AR8327_VTU_FUNC0_IVL BIT(19)
  206. #define AR8327_VTU_FUNC0_VALID BIT(20)
  207. #define AR8327_REG_VTU_FUNC1 0x0614
  208. #define AR8327_VTU_FUNC1_OP BITS(0, 3)
  209. #define AR8327_VTU_FUNC1_OP_NOOP 0
  210. #define AR8327_VTU_FUNC1_OP_FLUSH 1
  211. #define AR8327_VTU_FUNC1_OP_LOAD 2
  212. #define AR8327_VTU_FUNC1_OP_PURGE 3
  213. #define AR8327_VTU_FUNC1_OP_REMOVE_PORT 4
  214. #define AR8327_VTU_FUNC1_OP_GET_NEXT 5
  215. #define AR8327_VTU_FUNC1_OP_GET_ONE 6
  216. #define AR8327_VTU_FUNC1_FULL BIT(4)
  217. #define AR8327_VTU_FUNC1_PORT BIT(8, 4)
  218. #define AR8327_VTU_FUNC1_PORT_S 8
  219. #define AR8327_VTU_FUNC1_VID BIT(16, 12)
  220. #define AR8327_VTU_FUNC1_VID_S 16
  221. #define AR8327_VTU_FUNC1_BUSY BIT(31)
  222. #define AR8327_REG_ARL_CTRL 0x0618
  223. #define AR8327_REG_FWD_CTRL0 0x620
  224. #define AR8327_FWD_CTRL0_CPU_PORT_EN BIT(10)
  225. #define AR8327_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
  226. #define AR8327_FWD_CTRL0_MIRROR_PORT_S 4
  227. #define AR8327_REG_FWD_CTRL1 0x624
  228. #define AR8327_FWD_CTRL1_UC_FLOOD BITS(0, 7)
  229. #define AR8327_FWD_CTRL1_UC_FLOOD_S 0
  230. #define AR8327_FWD_CTRL1_MC_FLOOD BITS(8, 7)
  231. #define AR8327_FWD_CTRL1_MC_FLOOD_S 8
  232. #define AR8327_FWD_CTRL1_BC_FLOOD BITS(16, 7)
  233. #define AR8327_FWD_CTRL1_BC_FLOOD_S 16
  234. #define AR8327_FWD_CTRL1_IGMP BITS(24, 7)
  235. #define AR8327_FWD_CTRL1_IGMP_S 24
  236. #define AR8327_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
  237. #define AR8327_PORT_LOOKUP_MEMBER BITS(0, 7)
  238. #define AR8327_PORT_LOOKUP_IN_MODE BITS(8, 2)
  239. #define AR8327_PORT_LOOKUP_IN_MODE_S 8
  240. #define AR8327_PORT_LOOKUP_STATE BITS(16, 3)
  241. #define AR8327_PORT_LOOKUP_STATE_S 16
  242. #define AR8327_PORT_LOOKUP_LEARN BIT(20)
  243. #define AR8327_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
  244. #define AR8327_REG_PORT_PRIO(_i) (0x664 + (_i) * 0xc)
  245. #define AR8327_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
  246. #define AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF BITS(0, 4)
  247. #define AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S 0
  248. #define AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF BITS(4, 4)
  249. #define AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S 4
  250. #define AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF BITS(8, 4)
  251. #define AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S 8
  252. #define AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF BITS(12, 4)
  253. #define AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S 12
  254. #define AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF BITS(16, 4)
  255. #define AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF_S 16
  256. #define AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF BITS(20, 4)
  257. #define AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF_S 20
  258. #define AR8327_PORT_HOL_CTRL0_EG_PORT_BUF BITS(24, 6)
  259. #define AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S 24
  260. #define AR8327_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
  261. #define AR8327_PORT_HOL_CTRL1_ING_BUF BITS(0, 4)
  262. #define AR8327_PORT_HOL_CTRL1_ING_BUF_S 0
  263. #define AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
  264. #define AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
  265. #define AR8327_PORT_HOL_CTRL1_WRED_EN BIT(8)
  266. #define AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
  267. #define AR8337_PAD_MAC06_EXCHANGE_EN BIT(31)
  268. enum ar8327_led_pattern {
  269. AR8327_LED_PATTERN_OFF = 0,
  270. AR8327_LED_PATTERN_BLINK,
  271. AR8327_LED_PATTERN_ON,
  272. AR8327_LED_PATTERN_RULE,
  273. };
  274. struct ar8327_led_entry {
  275. unsigned reg;
  276. unsigned shift;
  277. };
  278. struct ar8327_led {
  279. struct led_classdev cdev;
  280. struct ar8xxx_priv *sw_priv;
  281. char *name;
  282. bool active_low;
  283. u8 led_num;
  284. enum ar8327_led_mode mode;
  285. struct mutex mutex;
  286. spinlock_t lock;
  287. struct work_struct led_work;
  288. bool enable_hw_mode;
  289. enum ar8327_led_pattern pattern;
  290. };
  291. struct ar8327_data {
  292. u32 port0_status;
  293. u32 port6_status;
  294. struct ar8327_led **leds;
  295. unsigned int num_leds;
  296. /* all fields below are cleared on reset */
  297. bool eee[AR8XXX_NUM_PHYS];
  298. };
  299. #endif