falcon.dtsi 7.8 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "lantiq,falcon";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips34kc";
  8. };
  9. };
  10. aliases {
  11. serial0 = &serial0;
  12. serial1 = &serial1;
  13. gpio0 = &gpio0;
  14. gpio1 = &gpio1;
  15. gpio2 = &gpio2;
  16. gpio3 = &gpio3;
  17. gpio4 = &gpio4;
  18. };
  19. chosen {
  20. stdout-path = "serial0:115200n8";
  21. };
  22. clocks {
  23. compatible = "simple-bus";
  24. cpu_clk: cpu {
  25. compatible = "fixed-clock";
  26. #clock-cells = <0>;
  27. clock-frequency = <400000000>;
  28. clock-output-names = "cpu";
  29. };
  30. io_clk: io {
  31. compatible = "fixed-clock";
  32. #clock-cells = <0>;
  33. clock-frequency = <200000000>;
  34. clock-output-names = "io";
  35. };
  36. fpi_clk: fpi {
  37. compatible = "fixed-clock";
  38. #clock-cells = <0>;
  39. clock-frequency = <100000000>;
  40. clock-output-names = "fpi";
  41. };
  42. };
  43. ebu_cs0: localbus@10000000 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. compatible = "lantiq,localbus", "simple-bus";
  47. reg = <0x10000000 0x4000000>;
  48. ranges = <0x0 0x10000000 0x4000000>;
  49. };
  50. ebu_cs1: localbus@14000000 {
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. compatible = "lantiq,localbus", "simple-bus";
  54. reg = <0x14000000 0x4000000>;
  55. ranges = <0x0 0x14000000 0x4000000>;
  56. };
  57. ebu@18000000 {
  58. compatible = "lantiq,ebu-falcon";
  59. reg = <0x18000000 0x100>;
  60. };
  61. sbs2@1D000000 {
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. compatible = "lantiq,sysb2", "simple-bus";
  65. reg = <0x1D000000 0x1000000>;
  66. ranges = <0x0 0x1D000000 0x1000000>;
  67. clock_sysgpe: clock-controller@700000 {
  68. compatible = "lantiq,sysgpe-falcon";
  69. reg = <0x700000 0x100>;
  70. #clock-cells = <1>;
  71. };
  72. mps@4000 {
  73. compatible = "lantiq,mps-falcon", "lantiq,mps-xrx100";
  74. reg = <0x4000 0x1000>;
  75. interrupt-parent = <&icu0>;
  76. interrupts = <154 155>;
  77. lantiq,mbx = <&mpsmbx>;
  78. };
  79. gpio0: gpio@810000 {
  80. compatible = "lantiq,falcon-gpio";
  81. gpio-controller;
  82. #gpio-cells = <2>;
  83. interrupt-controller;
  84. #interrupt-cells = <2>;
  85. interrupt-parent = <&icu0>;
  86. interrupts = <44>;
  87. reg = <0x810000 0x80>;
  88. clocks = <&clock_syseth 16>;
  89. };
  90. gpio2: gpio@810100 {
  91. compatible = "lantiq,falcon-gpio";
  92. gpio-controller;
  93. #gpio-cells = <2>;
  94. interrupt-controller;
  95. #interrupt-cells = <2>;
  96. interrupt-parent = <&icu0>;
  97. interrupts = <46>;
  98. reg = <0x810100 0x80>;
  99. clocks = <&clock_syseth 17>;
  100. };
  101. clock_syseth: clock-controller@B00000 {
  102. compatible = "lantiq,syseth-falcon";
  103. reg = <0xB00000 0x100>;
  104. #clock-cells = <1>;
  105. };
  106. pad@B01000 {
  107. compatible = "lantiq,pad-falcon";
  108. reg = <0xB01000 0x100>;
  109. lantiq,bank = <0>;
  110. clocks = <&clock_syseth 20>;
  111. };
  112. pad@B02000 {
  113. compatible = "lantiq,pad-falcon";
  114. reg = <0xB02000 0x100>;
  115. lantiq,bank = <2>;
  116. clocks = <&clock_syseth 21>;
  117. };
  118. };
  119. fpi@1E000000 {
  120. #address-cells = <1>;
  121. #size-cells = <1>;
  122. compatible = "lantiq,fpi", "simple-bus";
  123. reg = <0x1E000000 0x1000000>;
  124. ranges = <0x0 0x1E000000 0x1000000>;
  125. serial1: serial@100B00 {
  126. status = "disabled";
  127. compatible = "lantiq,asc";
  128. reg = <0x100B00 0x100>;
  129. interrupt-parent = <&icu0>;
  130. interrupts = <112 113 114>;
  131. line = <1>;
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&asc1_pins>;
  134. clocks = <&clock_sys1 11>;
  135. };
  136. serial0: serial@100C00 {
  137. compatible = "lantiq,asc";
  138. reg = <0x100C00 0x100>;
  139. interrupt-parent = <&icu0>;
  140. interrupts = <104 105 106>;
  141. line = <0>;
  142. pinctrl-names = "default";
  143. pinctrl-0 = <&asc0_pins>;
  144. clocks = <&clock_sys1 12>;
  145. };
  146. spi: spi@100D00 {
  147. status = "disabled";
  148. compatible = "intel,falcon-spi", "intel,xrx100-spi", "lantiq,spi-lantiq-ssc";
  149. interrupts = <22 23 24 25>;
  150. interrupt-names = "spi_tx", "spi_rx", "spi_err", "spi_frm";
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. reg = <0x100D00 0x100>;
  154. interrupt-parent = <&icu0>;
  155. clocks = <&clock_sys1 13>;
  156. base_cs = <1>;
  157. num_cs = <2>;
  158. };
  159. gptc@100E00 {
  160. compatible = "lantiq,gptc-falcon";
  161. reg = <0x100E00 0x100>;
  162. };
  163. i2c: i2c@200000 {
  164. status = "disabled";
  165. #address-cells = <1>;
  166. #size-cells = <0>;
  167. compatible = "lantiq,lantiq-i2c";
  168. reg = <0x200000 0x10000>;
  169. interrupt-parent = <&icu0>;
  170. interrupts = <18 19 20 21>;
  171. gpios = <&gpio1 7 0 &gpio1 8 0>;
  172. pinctrl-names = "default";
  173. pinctrl-0 = <&i2c_pins>;
  174. clocks = <&clock_sys1 14>;
  175. };
  176. gpio1: gpio@800100 {
  177. compatible = "lantiq,falcon-gpio";
  178. gpio-controller;
  179. #gpio-cells = <2>;
  180. interrupt-controller;
  181. #interrupt-cells = <2>;
  182. interrupt-parent = <&icu0>;
  183. interrupts = <45>;
  184. reg = <0x800100 0x100>;
  185. clocks = <&clock_sys1 16>;
  186. };
  187. gpio3: gpio@800200 {
  188. compatible = "lantiq,falcon-gpio";
  189. gpio-controller;
  190. #gpio-cells = <2>;
  191. interrupt-controller;
  192. #interrupt-cells = <2>;
  193. interrupt-parent = <&icu0>;
  194. interrupts = <47>;
  195. reg = <0x800200 0x100>;
  196. clocks = <&clock_sys1 17>;
  197. };
  198. gpio4: gpio@800300 {
  199. compatible = "lantiq,falcon-gpio";
  200. gpio-controller;
  201. #gpio-cells = <2>;
  202. interrupt-controller;
  203. #interrupt-cells = <2>;
  204. interrupt-parent = <&icu0>;
  205. interrupts = <48>;
  206. reg = <0x800300 0x100>;
  207. clocks = <&clock_sys1 18>;
  208. };
  209. pad@800400 {
  210. compatible = "lantiq,pad-falcon";
  211. reg = <0x800400 0x100>;
  212. lantiq,bank = <1>;
  213. clocks = <&clock_sys1 20>;
  214. };
  215. pad@800500 {
  216. compatible = "lantiq,pad-falcon";
  217. reg = <0x800500 0x100>;
  218. lantiq,bank = <3>;
  219. clocks = <&clock_sys1 21>;
  220. };
  221. pad@800600 {
  222. compatible = "lantiq,pad-falcon";
  223. reg = <0x800600 0x100>;
  224. lantiq,bank = <4>;
  225. clocks = <&clock_sys1 22>;
  226. };
  227. status@802000 {
  228. compatible = "lantiq,status-falcon";
  229. reg = <0x802000 0x80>;
  230. };
  231. clock_sys1: clock-controller@F00000 {
  232. compatible = "lantiq,sys1-falcon";
  233. reg = <0xF00000 0x100>;
  234. #clock-cells = <1>;
  235. };
  236. };
  237. sbs0@1F000000 {
  238. #address-cells = <1>;
  239. #size-cells = <1>;
  240. compatible = "simple-bus";
  241. reg = <0x1F000000 0x400000>;
  242. ranges = <0x0 0x1F000000 0x400000>;
  243. mpsmbx: mpsmbx@200000 {
  244. reg = <0x200000 0x200>;
  245. };
  246. };
  247. sbs1@1F700000 {
  248. };
  249. biu@1F800000 {
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. compatible = "lantiq,biu", "simple-bus";
  253. reg = <0x1F800000 0x800000>;
  254. ranges = <0x0 0x1F800000 0x800000>;
  255. icu0: icu@80200 {
  256. #interrupt-cells = <1>;
  257. interrupt-controller;
  258. compatible = "lantiq,icu";
  259. reg = <0x80200 0x28
  260. 0x80228 0x28
  261. 0x80250 0x28
  262. 0x80278 0x28
  263. 0x802a0 0x28>;
  264. };
  265. watchdog@803F0 {
  266. compatible = "lantiq,wdt";
  267. reg = <0x803F0 0x10>;
  268. clocks = <&io_clk>; /* currently no effect */
  269. };
  270. };
  271. pinctrl {
  272. compatible = "lantiq,pinctrl-falcon";
  273. pinctrl-names = "default";
  274. pinctrl-0 = <&state_default>;
  275. state_default: pinctrl0 {
  276. /*ntr {
  277. lantiq,groups = "ntr8k";
  278. lantiq,function = "ntr";
  279. };*/
  280. hrst {
  281. lantiq,groups = "hrst";
  282. lantiq,function = "rst";
  283. };
  284. };
  285. asc0_pins: asc0 {
  286. asc0 {
  287. lantiq,groups = "asc0";
  288. lantiq,function = "asc";
  289. };
  290. };
  291. asc1_pins: asc1 {
  292. asc1 {
  293. lantiq,groups = "asc1";
  294. lantiq,function = "asc";
  295. };
  296. };
  297. i2c_pins: i2c {
  298. i2c {
  299. lantiq,groups = "i2c";
  300. lantiq,function = "i2c";
  301. };
  302. };
  303. bootled_pins: bootled {
  304. bootled {
  305. lantiq,groups = "bootled";
  306. lantiq,function = "led";
  307. };
  308. };
  309. ntr_ntr8k: ntr8k {
  310. ntr8k {
  311. lantiq,groups = "ntr8k";
  312. lantiq,function = "ntr";
  313. };
  314. };
  315. ntr_pps: pps {
  316. pps {
  317. lantiq,groups = "pps";
  318. lantiq,function = "ntr";
  319. };
  320. };
  321. ntr_gpio: gpio {
  322. gpio {
  323. lantiq,pins = "io5";
  324. lantiq,mux = <1>;
  325. lantiq,output = <0>;
  326. };
  327. };
  328. slic_pins: slic {
  329. slic {
  330. lantiq,groups = "slic";
  331. lantiq,function = "slic";
  332. };
  333. };
  334. };
  335. pinselect-ntr {
  336. compatible = "lantiq,onu-ntr","lantiq,pinselect-ntr";
  337. pinctrl-names = "ntr8k", "pps", "gpio";
  338. pinctrl-0 = <&ntr_ntr8k>;
  339. pinctrl-1 = <&ntr_pps>;
  340. pinctrl-2 = <&ntr_gpio>;
  341. };
  342. pinselect-asc1 {
  343. compatible = "lantiq,onu-asc1","lantiq,pinselect-asc1";
  344. pinctrl-names = "default", "asc1";
  345. pinctrl-0 = <&slic_pins>;
  346. pinctrl-1 = <&asc1_pins>;
  347. };
  348. };